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Channel code demodulation method and device Group of inventions relates to computer engineering and communication and can be used in local area networks and external storage devices. The device comprises a clocking unit, a clock pulse generating unit, an error detection unit and a channel code conversion unit. |
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Method of filtering and detecting pulsed signals with robust system of partial channels Method of filtering and detecting pulsed signals with a robust system of partial channels includes observing an additive mixture of pulsed video- or radio signals on a noise background, channel robust and resultant in-phase filtering of pulses, wherein after preliminary one-dimensional functional conversion with corresponding standardisation of the observed additive mixture for the pulsed signal, partial estimates are generated via robust nonlinear filtering in each channel in the robust system of partial channels, then based on said estimates, multidimensional robust processing of output signals of the partial channels is performed using cognitive methods or image identification methods for both video signals and radio signals, while realising coherent and in-phase summation, which is in-phase for signals and not in-phase for noise; detection and estimation of signal parameters is then performed. |
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Analogue-to-digital converter and zero offset calibration method High-speed N-bit combined analogue-to-digital converter (ADC) includes an input parallel M-bit ADC1, an M-bit digital-to-analogue converter (DAC1), a sampling and storage device (SSD) and a pipelined (N-M+1)-bit ADC2. The M-bit ADC1 and DAC1 employ a common serial resistance divider. The SSD with double sampling, consisting of an amplifier and two samplers, generates a different signal of the input voltage of the ADC and the output voltage of the DAC. The entire analogue circuit of the ADC is differential. The ADC implements individual zero offset calibration for different samplers, for which are used two identical calibration DACs and a switch which transmits to the amplifier of the SSD a calibration signal corresponding to the sampler in storage mode, from one of the calibration DACs. During calibration, a zero differential signal with an in-phase level equal to or close to the in-phase level of the input signal is transmitted to the input of the SSD. |
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Rejection LC-filter comprises a low-pass filter which consists of N inductance coils connected in series to each other, wherein each of the leads of said inductance coils is connected to a capacitor and second leads of the capacitors are connected to a common bus. The first lead of the first inductance coil of the low-pass filter is connected to a first circuit consisting of parallel-connected inductance coil and capacitor; the second lead of the last inductance coil of the low-pass filter is connected to a second circuit consisting of parallel-connected inductance coil and capacitor; the second lead of the second circuit is connected to the output potential terminal of the filter. |
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Analogue-to-digital converter and method for calibration thereof High-speed N-bit combined analogue-to-digital converter (ADC) includes an input parallel M-bit ADC1, an M-bit digital-to-analogue converter (DAC1), using a common serial resistance divider, a reference voltage Vref source, a sampling and storage device (SSD) for the difference signal of the input of the ADC and output voltage of the DAC and a pipelined (M-M+1)-bit ADC2. Calibration includes calculating and loading into DAC2 a calibration code CR and calibration codes CSi of each segment, used during normal operation as additive adjustments to the output code of the ADC, wherein a signal close to zero is generated through a unit transmission coefficient of the first stage of an ADC2 pipeline. In ADC, using SSD and ADC2 with double sampling, the DAC2 and Vref2 source are doubled and generate voltages Vref2A and Vref2B separately for each of two samplers A and B. |
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Controlled selective amplifier Invention relates to radio engineering, and specifically to controlled selective amplifiers. The selective amplifier comprises a signal source connected to the base of a first input transistor, a second input transistor, a first current-stabilising two-terminal element connected between the emitter of the first input transistor and a first power supply bus, a second current-stabilising two-terminal element connected between the emitter of the second input transistor and the first power supply bus, a first balancing capacitor connected between the emitter of the first and second input transistors, a first frequency-setting resistor connected between the collector of the first input transistor and a second power supply bus, a second balancing capacitor and a second frequency-setting resistor. The second balancing capacitor is connected between the base of the second input transistor and the collector of the first input transistor; the second frequency-setting resistor is connected between the base of the second input transistor, which is connected to the output of the device and a common power supply bus, wherein the frequency-setting resistor is connected in parallel via alternating current to an additional balancing capacitor. |
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Selector of two input currents difference module Selector of two input currents difference module contains current input (1) and current output (2), the first (3) front-end transistor, which emitter is connected to current input (1) of the device, the base is connected to the first (4) source of auxiliary voltage while collector is connected to the input of current mirror (5) matched to the first (6) bus of the power supply source, the second (7) front-end transistor, which emitter is connected to current input (1) of the device and the base is connected to the second (8) source of auxiliary voltage. The collector of the second (7) front-end transistor is connected to current output (2) of the device, at that the current output (2) of the device is matched to the second (9) bus of the power supply source. |
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Converter for converting periodic signal to frequency and period Invention relates to pulse engineering and can be used in automatic control systems, measuring devices, controlled phase changers and in designing multi-phase generators. The device comprises comparators, monovibrators, a sampling-storage device, a dc voltage source, a switch, resistors, a capacitor, an operational amplifier and a signal former, proportional to the frequency of the input signal. |
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Invention relates to a communication system which employs low-density parity check (LDPC) codes. The method of encoding a channel using a LDPC code includes a step of determining the number of parity bits for puncturing. The method also includes a step of generating sets of parity bits from dividing parity bits through predefined intervals. Further, the number of sets of parity bits is determined based on the number of parity bits for puncturing. |
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Invention relates to a communication system which employs low-density parity check (LDPC) codes. The method for channel decoding using a LDPC code includes a step of demodulating a signal transmitted from a transmitter. The method also includes a step of determining positions of punctured parity bits by evaluating information on a predetermined order of sets of parity bits to be punctured and the number of sets of parity bits. Further, data are decoded using said positions of punctured parity bits. |
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Method for pulse length reduction of powerful shf radiation and method for its implementation Method for pulse length reduction of powerful SHF radiation and method for its implementation is characterised by introduction of SHF pulses into waveguide section with gas-filled tubes, under influence of downward powerful SHF radiation SHF-discharges are excited in the gas-filled tubes thus leading to formation of an electromagnetic band structure and pulse narrowing. The device for pulse length reduction of powerful SHF radiation contains a waveguide section with three gas-filled tubes connected by its one end through a coaxial transition and ferrite isolator to SHF-generator and by its other end through a coaxial transition and ferrite isolator to SHF-detector, the three gas-filled tubes are placed along the waveguide section perpendicular to its wide walls with distance l=Λ0/2÷Λ0, where Λ0=λ0(1-(λ0/2a)2)-1/2 is wave length in the waveguide, λ0 is wave length of downward SHF-radiation; a is a size of the wide wall in the waveguide section. |
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Signal demodulation system relates to demodulation of a phase- or frequency-modulated signal and can be used to detect a moving object. The signal demodulation system comprises: a complex demodulator (110) having a first input (111) for receiving a phase-modulated input signal (Si) and designed to perform complex multiplication of said signal with approximation of the inverse of the phase modulation value; a spectrum analyser (130) which receives the demodulated multiplied signal, generated by the complex demodulator (110), and capable of analysing the frequency spectrum of the demodulated multiplied signal, and a modulation controller (140). |
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Invention relates to radio engineering and electronics and can be used to protect information of computer equipment, automated workstations and wire lines from information leakage as a result of stray electromagnetic radiation and cross talk. The noise signal generator has two outputs which are controlled based on signal strength. The additional noise signal generator used is an impact avalanche transit time noise diode with an amplifier and a variable resistor for controlling the additional noise signal strength, and the emitting low-frequency element used is an inductance coil with distributed parameters, which enables to generate the low-frequency part of the magnetic component o the electromagnetic field of the noise signal. |
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Composite transistor contains an input transistor (1) which base is the base (2) and emitter is the emitter (3) of the composite transistor, an output transistor (4) which collector is the collector (5) of the composite transistor and its emitter is connected to the collector of the input transistor (1), at that in the circuit there is an additional transistor (6) which static mode against the emitter current is set by an additional reference power supply source (7) coupled between the first (8) power supply bus and the emitter of the additional transistor (6), at that the base of the additional transistor (6) is connected to the base of the input transistor (1), its collector is connected to the emitter of the input transistor (1) and the emitter is connected to the base of the output transistor (4). |
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Invention relates to radio engineering and communication and can be used in filtering radio signals, television and radar. The selective amplifier comprises an input voltage source (1), a voltage-to-current converter (2), an output transistor (3), a first power supply bus (4), a first frequency-setting resistor (5), a first (6) and a second (7) balancing capacitor, a second (8) and a third (9) frequency-setting resistor, an auxiliary voltage source (10), a negative power supply bus (11), a common power supply bus (12), an output of the device (13), a first additional current-stabilising two-terminal element (14), an additional transistor (15) an additional capacitor (16). |
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Complementary differential amplifier with expanded active operation range Complementary differential amplifier with an expanded active operation range comprises a first (1) and a second (2) input transistor, inputs (3), (4) of the device, a first (5) and a second (6) output transistor, a reference current source (7), a first (8) and a second (9) current-limiting resistor, first (10) and second (11) series-connected auxiliary resistors, an auxiliary forward-biased p-n junction (12), a common node (13), a first group of antiphase current outputs (14, 15), a second group of antiphase current outputs (16, 17), an emitter p-n junction of an additional transistor (18), a power supply bus (19). |
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Invention relates to flexible wall for microwave-filters with cavity resonator equipped with mechanical device of temperature compensation to be used in telecommunication. Proposed system comprises at least two separate elastic membranes arranged one above the other. Every said membrane has central area (C), mid area (I) and peripheral area (P), end to end. Note here that elastic membranes are thermally and mechanically bolded at central area (C) and peripheral area (P) and are not connected at mid area (I). |
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Invention relates to computer engineering. A method for electronic transmission of data using one or more transmitters involves: generating a set of intermediate symbols from an ordered set of source symbols, wherein the source symbols can be regenerated from the set of intermediate symbols; designating sets of the intermediate symbols, before transmission, such that each intermediate symbol is designated as a member of one of the sets of intermediate symbols and there are at least a first set of intermediate symbols and a second set of intermediate symbols, and wherein each set of intermediate symbols is associated with its distinct encoding parameters and has as members at least one intermediate symbol; wherein said first set of intermediate symbols are designated as symbols for belief propagation decoding and the second set of intermediate symbols are designated as symbols to be inactivated for belief propagation decoding, wherein the inactivated symbols are symbols that must be found separately from belief propagation decoding; and generating a plurality of encoded symbols. |
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Analogue-to-digital converter comprises an n-bit priority encoder, a flip-flop Tg0, an AND circuit I0, an n-bit register, n flip-flops Tg1, …, Tgn with AND circuits I1, …, In, an n-bit number-to-voltage converter, a comparator circuit, a trigger bus, n analogue voltage comparators K1, …, Kn, n blocks of reference voltages Uet1, …, Uetn, an n-bit demultiplexer and a clock-pulse generator. |
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Power attenuator comprises N series-connected matched links on identical substrates mounted with equal spacing on a heat-conducting base; each subsequent link, for the same power losses therein, has higher attenuation than the previous link and the power transfer coefficient of the links (KP<1) is a function of at least two parameters, e.g. KPM=f(N, M,…), where N is the number of links; M is the index number of a link (M=1, 2, 3,…, N). The attenuator has a terminal connected to the output of the corresponding link, which corresponds to the parameters: number of links to said terminal and power transfer coefficient from the input to said terminal. |
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Highly selective narrow-band lc-filter Invention pertains to radio electronics and can be used for frequency selection of signals. The highly selective narrow-band LC-filter comprises two structurally identical band-pass filter links, each consisting of three capacitors and an inductance coil, eleven capacitors, two inductance coils, an input and an output potential terminal and a common bus. |
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Selective amplifier comprises a first (1) input transistor, the base of which is connected to the input (2) of the device, and the collector is connected to the output (3) of the device and is connected through a first (4) frequency-setting resistor to a first (5) power supply bus, a first (6) balancing capacitor connected via alternating current in parallel to the first (4) ) frequency-setting resistor, a second (7) input transistor, the collector of which is connected to a second (8) power supply bus, and the emitter is connected to the emitter of the first (1) input transistor, a second (9) frequency-setting resistor, the first lead of which is connected to the base of the second (7) input transistor, a second (10) balancing capacitor, the first lead of which is connected to the base of the second (7) input transistor. The second lead of the second (10) balancing capacitor is connected to the output (3) of the device, and the second lead of the second (9) frequency-setting resistor is connected to a first (11) auxiliary voltage source. |
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Transimpedance converter of signals of avalanche photodetectors and silicon photomultipliers Transimpedance converter of signals of avalanche photodetectors and silicon photomultipliers comprises a current signal source (1), connected to the current input of the device (2) and the emitter of an input transistor (3), a current-stabilising two-terminal element (4), connected between the emitter of the input transistor (3) and the first (5) power supply bus, a first (6) auxiliary voltage source, connected to the base of the input transistor (3), a second (7) auxiliary voltage source, connected to the base of an output transistor (8), the emitter of which is connected to the collector of the input transistor (3), a collector load two-terminal element (9), connected between the collector of the output transistor (8) and a second (10) power supply bus, a buffer amplifier (11), the input of which is connected to the collector of the output transistor (8), and the output is the output of the device (12). The output of the device (12) is connected to the emitter of the output transistor 8 through a balancing capacitor (13). |
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Instrumentation amplifier with controlled frequency response parameters Instrumentation amplifier with controlled frequency response parameters comprises a signal source, an input differential stage, balancing capacitors, power supply buses, current outputs of the input differential stage, current-stabilising two-terminal elements, a current mirror and an emitter. |
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Broadband voltage repeater comprises an input transistor (1), the control terminal (2) of which is connected to an input signal source (3), the injecting terminal (4) is connected to a first (5) power supply bus through a current-stabilising two-terminal element (6) and is connected to the main output of the device (7), and the charge-collecting terminal (8) is connected to a second (9) power supply bus, wherein the main output of the device (7) is alternating current-shunted by an equivalent load capacitor (10). The circuit includes an additional voltage repeater (11), the input of which is connected to the main output of the device (7), the output is connected to the additional output (12) of the device and through a balancing capacitor (13) to the input of an additional non-inverting current repeater (14), the current output of which is connected to the main output of the device (12). |
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Hybrid differential amplifier comprises a first (1) input transistor, the base of which is connected to the non-inverting input (2) of the device, the collector is connected to a first (3) power supply bus, and the emitter is connected to emitter of a second (4) input transistor, wherein the base of the second (4) input transistor is connected to the inverting input (5) of the device, and the collector is connected to the output (6) of the device and is connected to a second (7) power supply bus through a load circuit (8). The first (1) input transistor used is a first (1) junction field-effect transistor, the gate of which corresponds to the base, the source to the emitter and the drain to the collector of a bipolar transistor, and the load circuit (8) comprises a second (9) junction field-effect transistor, the gate of which is connected to the second (7) power supply bus, the drain is connected to the collector of the second (4) input transistor, and the source is connected to second (7) power supply bus through an additional p-n junction (10), identical to the emitter-base junction of the second (4) input transistor. |
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Controlled amplifier and analogue signal mixer based on darlington differential stage Invention can be used in radio receivers, phase detectors and modulators, as well as in frequency multiplier systems or as an amplifier whose voltage transfer ratio from inputs of channel X depends on the control signal strength in channel Y. The method is carried out using a controlled amplifier and an analogue signal mixer based on a Darlington differential stage which comprises first (1) and second (2) anti-phase input voltage sources, bases of a first (3) and a second (4) input transistor, the emitter of the first (3) input transistor, a first (5) current-stabilising two-terminal element, a first (6) power supply, the emitter a second (4) input transistor, a second (7) current-stabilising two-terminal element, a first (6) power supply, a third (8) input transistor, the emitter of a fourth (9) input transistor, a third (10) current-stabilising two-terminal element, a differential load circuit (11), a second (12) power supply, first (13) and second (14) outputs of the device. |
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Controlled selective amplifier Controlled selective amplifier comprises an input signal source, two input transistors, two current-stabilising two-terminal elements, a power supply, a current mirror, two balancing capacitors, a resistor and a buffer amplifier. The input transistors used are field-effect transistors, whose sources correspond to the emitter, the drain to the collector and the gate to the base of a bipolar transistor. |
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Instrumentation amplifier comprises: an input precision converter of (1) of a first (2) and a second (3) input voltage source connected to a common power supply bus (4), a first (9), a second (10) and a third (11) feedback resistor, an active adder (12) with an inverting (13) and a non-inverting (14) input. |
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Invention relates to radio engineering and communication and can be used in devices for microwave filtering of radio signals in cellular communication systems, satellite television and radar. The selective microwave amplifier comprises an output transistor (1), the base of which is connected to an auxiliary voltage source (2), and the collector is connected through a first (3) resistor to a first (4) power supply bus, a voltage-to-current converter (5), matched with a second (6) power supply bus, the output (7) of which is connected to the emitter of output transistor (1), an input voltage source (8), connected to the input of the voltage-to-current converter (5), a first (9) and a second (10) balancing capacitor. The collector of the first (1) output transistor is connected via alternating current to the first (4) power supply bus through the series-connected first (9) and second (10) balancing capacitors, the common node of which is connected to the output of the device (11) and the output (7) of the voltage-to-current converter (5). |
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Ultra-high-speed parallel analogue-to-digital converter with differential input Disclosed is an ultra-high-speed parallel analogue-to-digital converter with a differential input, having N sections of identical architecture. Each of the sections includes a voltage comparator, the first input of which is connected to a first input voltage source through a first reference resistor, and the second input of the voltage comparator is connected to a second input anti-phase voltage source through a second reference resistor, wherein the first input of the voltage comparator is connected to a first reference current source and a first parasitic capacitor, the second input of the voltage comparator is connected to a second reference current source and a second parasitic capacitor. The first reference current source is connected in form of a first current mirror which is matched with a first power supply bus, and a first auxiliary reference current source connected to the input of the first current mirror, wherein the output of the first current mirror is the output of the first reference current source, and the second input anti-phase voltage source is connected to the input of the first current mirror through a first balancing capacitor. |
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Invention relates to a broadband wireless mobile communication system. In a wireless mobile communication system, which supports a resource block group (RBG) distribution scheme for distributed mapping of successively distributed virtual resource blocks to physical resource blocks, when zeros are added to a block interleaver used for mapping, said zeros are uniformly distributed into ND divided groups of the block interleaver, the number of which is equal to the number ND of physical resource blocks to which one virtual resource block is mapped. |
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Reduced dc gain mismatch and dc leakage in overlap transform processing Invention relates to means of generating an equalised multichannel audio signal. Inverse frequency transformation of digital media data is performed. A plurality of overlap operators are applied to results of the inverse frequency transformation. The plurality of overlap operators include at least a first overlap operator and a second overlap operator. The first overlap operator is an interior overlap operator. The second overlap operator is an edge or corner overlap operator. Each of the plurality of overlap operators is characterised by substantially equivalent DC gain. |
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Parallel single signal counter Invention can be used in digital computer systems as a means of pre-processing discrete information. The device includes sixteen XOR elements and twelve AND elements. |
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In supramed operation (τ1,…,τ7) τ1,…,τ7 there are lengths of positive pulse signals x1,…,x7∈{0.1} synchronised against the front edge. The device contains a resistor and twenty four keys grouped in six groups. |
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Method and apparatus for selective data encryption Invention relates to data encryption and specifically to encryption of image data organised into bit streams. A layered audiovisual packet data stream (CNT'), such as one obtained by a JPEG2000 encoder (810), is received together with information (metadata) about the contribution of each packet to the reduction of image distortion. The distortion-to-rate ratio for each packet is calculated (710) and the packets are ordered (720) in descending ratio. The non-encrypted packet having the highest ratio is encrypted (730) until the target distortion is obtained. |
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Device for components of high-voltage pulse testing system Invention is related to a device for components of high-voltage pulse testing system, preferably to quality control of high-power transformers. The invention concept is as follows: in the device for components of high-voltage pulse testing system containing a pulse generator and auxiliary components, and namely a limiting discharger (2), voltage divider (3) and overload compensator (4) at least two of the auxiliary components are installed on a common frame with the only main electrode (11) for auxiliary components. |
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Method of determining violations and correcting violated codes of bit positions in "1 from 4" coding In the encoding device of the transmitting side of a communication channel, information coming from a source in a binary code is converted to a "1 from 4" code with an active zero; the converted information is generated in form of an array of words which can be presented in the form of a table comprising P1 rows (words), each comprising P2 quaternary bits in a "1 from 4" code, wherein like quaternary bits in rows form P2 vertical columns of the array; a check code, Kr and Kv, is formed for each word and vertical column, respectively, via successive summation of bits of the word and the vertical column without carry over; in the control device, the received information is checked for conformity with the "1 from 4" code and check codes Kr and Kv; upon detecting a fault, the information is corrected and transmitted to the end device. |
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Differential operational amplifier with passive parallel channel Differential operational amplifier with a passive parallel channel comprises two input transistors, two output transistors which are junction gate field-effect transistors, a non-inverting stage and a controlled current source. |
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Selective amplifier with extended frequency band Device includes a main operational amplifier, between the output and the inverting input of which a first frequency-dependent resistor is connected, first and second frequency-setting capacitors connected in series between the output of the main operational amplifier and its inverting input, a second frequency-setting resistor, the first lead of which is connected to the common node of the series-connected frequency-setting capacitors, an input voltage source, first and second power supply buses; the second frequency-setting resistor is connected between the common node of the first and second frequency-setting capacitors and the first power supply bus; the input voltage source is connected to the inverting input of an additional voltage-to-current converter, the non-inverting input of which is connected to the inverting input of the main operational amplifier; the common emitter circuit of the additional voltage-to-current converter is connected to the second power supply bus, and the current output of the additional voltage-to-current converter is connected to the common node of the frequency-setting capacitors. |
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Voltage-controlled generator comprises two field-effect transistors, five inductance coils, seven capacitors, a conducting bias circuit, an automatic cutoff bias circuit, a control circuit and an external load. |
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Frequency synthesiser with switched frequency reduction channels Device includes two frequency-phase detectors (1 and 9), two low-pass filters (2 and 10), a voltage-controlled generator (3), a power splitter (4), a frequency divider (5), a low-frequency switch (6), a mixer (7), a reference frequency generator (8) and a control unit (12). |
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Digital modular for control over synchronous motor Modulator comprises rectangular pulse generator, counters, OR elements, triggers, inverter, limiting circuit, decoders, pulse shapers, AND elements, reset circuit, adders, registers, AND-NO elements, binary-sextic counter, input signal bus, sign bus, bus of the signal describing engine design version, rotor position transducer signal bus and output buses. |
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Present invention relates to radio electronics and can be used to determine carrier frequency and type of modulation of signals received in a given frequency band. The panoramic receiver comprises a receiving antenna 1, an input circuit 2, a search unit 3, a high frequency amplifier 4, a heterodyne 5, mixer 6, an intermediate frequency amplifier 7, amplitude detectors 8, 16.1, 16.2 and 16.3, a video amplifier 9, a frequency sweep device 10, cathode-ray tubes 11, 17.1, 17.2, 17.3, 20, 24 and 31, a switch 12, a phase doubler 13.1, a phase quadrupler 13.2, an eight-times phase multiplier 13.3, a phase halver 14.1, a four-times phase divider 14.2, an eight-times phase divider 14.3, band-pass filters 15.1, 15.2, 15.3, 27 and 29, switches 18, 21 and 25, frequency detectors 19, 23 and 30, 90° phase changers 22 and 28. |
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Resonance power amplifier contains an input transformer, n amplifying cascades from n step-down power transformers interconnected by means of n in-series resonance circuits where n=2, 3, …, m, and a feedback device providing unidirectional motion of electric energy from the secondary winding of the last power transformer to the primary winding of the input transformer. |
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Switchover unit contains a source of control signal, an actuator electromagnetic relay, two control electromagnetic relays with a group of changeover contacts which control circuits are connected to buses of the respective data channels, a capacitor and a resistor. |
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Invention is related to the field of electric engineering and may be used in industries for in-process control of articles represented by non-linear composite loads. Method for reduction of a non-linear current distortion in a non-linear composite load is characterised by representation of alternating current setting current in the circuit with the non-linear composite load as Fourier series, calculation of coefficients for these Fourier series when compensation is made for higher harmonics formed in result of the impact of the non-linear composite load by means of Fourier inversion and on the basis of calculated coefficients formation of alternating voltage, which sets current in the circuit with the non-linear composite load with a less level of non-linear distortion. The device for reduction of the non-linear current distortion in the non-linear composite load includes an amplifier, a control unit, a digital-to-analogue converter, the non-linear composite load, an analogue-to-digital converter and a current sensor. |
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Invention relates to radio electronics and can be used as a pre-selector of a professional grade radio receiver. The tunable band-pass ARC-filter comprises a first capacitor connected to the input potential terminal of a device, a second capacitor connected to the output potential terminal of the device and two structurally identical general resistance converters, each comprising a first and a second operational amplifier, first, second and third resistors and a third capacitor, second leads of the first and second capacitors of which are connected to a common bus. The device further includes fourth, fifth, sixth, seventh, eighth, ninth and tenth capacitors and two electronic potentiometers. |
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Pulse selector is designed to reproduce the med(τ1,…,τ5) operation, where τ1,…,τ5 denote the duration of positive pulses of signals x1,…,x5∈{0,1}, synchronised on the leading edge, and can be used in automatic control systems as an information preprocessing means. The pulse selector comprises a resistor (1) and fourteen switches (211,…,242). |
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Wideband polyharmonic generator Wideband polyharmonic generator comprises an active element, an outlet circuit, which matches an active element with a load, and a wideband inlet circuit, at the same time parameters of the outlet circuit in the working band of frequencies from the set ratios. |
Another patent 2513526.