Broadband voltage repeater

FIELD: radio engineering, communication.

SUBSTANCE: broadband voltage repeater comprises an input transistor (1), the control terminal (2) of which is connected to an input signal source (3), the injecting terminal (4) is connected to a first (5) power supply bus through a current-stabilising two-terminal element (6) and is connected to the main output of the device (7), and the charge-collecting terminal (8) is connected to a second (9) power supply bus, wherein the main output of the device (7) is alternating current-shunted by an equivalent load capacitor (10). The circuit includes an additional voltage repeater (11), the input of which is connected to the main output of the device (7), the output is connected to the additional output (12) of the device and through a balancing capacitor (13) to the input of an additional non-inverting current repeater (14), the current output of which is connected to the main output of the device (12).

EFFECT: wide operating frequency range of the broadband voltage repeater when there is a capacitance Cn at the output, which can be reduced for objective reasons, shorter time for establishing a transient process with pulsed variation of the input voltage.

3 cl, 8 dwg

The present invention relates to the field of radio and communication and can be used in various analog devices in the field and bipolar transistors as the output (buffer) amplifier.

The base node of the modern analog devices is a broadband voltage follower (SNH), which is implemented as a common-drain (on field) or as a common-collector bipolar transistors. This structure (figure 1) [1-25] is widely used in analog (class H03F)and digital (class H03K) devices. In the latter case, SNH performs the functions of a driver - cascade control lines or matching network. Typically, the load is known SNH [1-25] contains the active resistance R_Hand capacity With_nnegatively affect small-signal frequency range and the speed with pulse input signal of high amplitude.

The closest prototype of the proposed device is a classic voltage follower described in patent US 6.043.690 fig.1. It contains the input transistor 1, the control pin which 2 (gate) is connected with the input source 3, an injecting pin 4 (source) connected to the first 5 bus power supply through dakotabilities dvukhpolosnykh 6 and is connected to the primary output device 7, and the FDS is a rising charges output 8 (drain) is connected with the second 9-bus power supply, moreover, the main output device 7 shunted by AC equivalent, as a rule, the parasitic capacitor load 10.

A significant disadvantage of the known device is that it has a relatively narrow operating frequency range small signal, which is determined by the time constant of the load circuit (τ_in).

Indeed, in the first approximation, the upper cutoff frequency f_in(-3 dB) classic SNH 1 is not better than

$$f_{\mathrm{in}}\le \frac{1}{2\pi t_{\mathrm{in}}},\left(1\right)$$

where τ_in- the time constant of the load circuit. And

$$t_{\mathrm{in}}\approx \left(\frac{1}{S}\left|\right|R_{\mathrm{the}}\right)C_n,\left(2\right)$$

where S is the slope of the input field-effect transistor SNH-prototype 1;

R_nequivalent load resistance;

C_nequivalent load capacitance. The main objective of the invention is the extension of the operating frequency range SNH in the presence of capacitance at the output With_nthat may not be reduced due to objective reasons - is an integral part of the load circuit, for example, a piezoceramic transducer, etc.

An additional objective is the reduction of the time of the transition process when the pulse changing the input voltage.

This object is achieved in that in the broadband voltage follower figure 1, containing I is ne transistor 1, the control pin 2 which is connected with the input source 3, an injecting pin 4 is connected to the first 5 bus power supply through dakotabilities dvukhpolosnykh 6 and is connected to the primary output device 7, and collecting charges the output 8 is connected with the second 9-bus power supply, and the main output device 7 shunted by AC equivalent capacitor of the load 10, there are new elements and the communication scheme introduced additional voltage follower 11, an input connected to the primary output device 7, the output associated with access device 12 and through the adjustment capacitor 13 is connected to the input einverseremove the current repeater 14, the current output of which is connected with the main output device 12.

In the drawing figure 1 is a diagram SNH prototype.

In the drawing figure 2 presents the diagram of the inventive device in accordance with claim 1 and claim 2.

In the drawing figure 3 presents a diagram of the inventive broadband voltage follower figure 2 on field transistor in the environment of computer simulation Cadence.

In the drawing figure 4 shows the logarithmic amplitude-frequency characteristics of the gain voltage (_y≤1) SNH figure 3 for dierent values of capacitance adjustment capacitor 13 figure 2). From these graphs it follows that the operating frequency range of the claimed device expands to 6.4 GHz, while the upper cutoff frequency of the SNH-prototype (-3 dB) is set to 44 MHz.

In the drawing figure 5 presents the transient output voltage SNH 3 when increasing the input pulse with amplitude 1 and shows the time values of the transition process (t_ustar.the output SNH 3 when the capacitance adjustment capacitor 13 (SC). These graphs show that the proposed scheme figure 3 performance increases to 47.5 PS that 138 times better than SNH prototype.

Drawing 6 shows a transition process SNH 3 when falling of the input pulse and the time values of the transition process (t_Ustad.) output SNH under different values of capacitance adjustment capacitor 13 (SC).

In the drawing 7 presents a diagram of the inventive device 2 is a bipolar p-n-p transistor in accordance with section 3 of the claims.

The diagram in the drawing Fig implemented on the p-n-p composite transistor 1, which includes a bipolar transistor 16 and the resistor 17.

Broadband voltage follower figure 2 contains the input transistor 1, the control pin 2 which is connected with the input source 3, an injecting pin 4 are connected to the EN to the first 5 bus power supply through dakotabilities dvukhpolosnykh 6 and is connected to the primary output device 7, and collecting charges the output 8 is connected with the second 9-bus power supply, and the main output device 7 shunted by AC equivalent capacitor of the load 10. The scheme introduced additional voltage follower 11, an input connected to the primary output device 7, the output associated with access device 12 and through the adjustment capacitor 13 is connected to the input einverseremove repeater DC 14, the current output of which is connected with the main output device 12.

In the drawing of figure 2, in accordance with claim 2, as an input transistor 1 is used field-effect transistor, the gate of which corresponds to the control output 2, source - injects the output 4, and the flow - collecting charges to the output 8 of the input transistor 1.

In the drawing 7, in accordance with section 3 of the claims, as the input transistor 1 is used bipolar n-p-n transistor, the base of which corresponds to the control output 2, the emitter - injects the output 4 and the collector - collects the charges to the output 8 of the input transistor 1.

The diagram in the drawing Fig implemented on the p-n-p composite transistor 1, which includes a bipolar transistor 16 and the resistor 17.

Consider the circuit of figure 2.

The static mode of the input transistor 1 is set in a private the beam by dvukhpolosnykh 6. Additional voltage follower 11 and an additional non-inverting current repeater 14 in this case do not affect the static schema.

The change of input voltagetransmitted to the load circuit

where$$K_0=\frac{1}{1+\frac{1}{S_1{R}_{n.eK\mathrm{in}}}}=\frac{{\stackrel{}{U}}_{\mathrm{in}sx.7}}{{\stackrel{}{U}}_{\mathrm{in}x}},\left(4\right)$$

$$t_n=C_{10}{R}_{15}\Vert \frac{1}{S_1},\left(5\right)$$

R.=R15 - equivalent load resistance;

S₁- slope input (field) of the transistor (or$$S_1=r_{e1}^{-1}$$the steepness of the input bipolar transistor, where r_E1- resistance emitter junction of a bipolar transistor).

Voltageis transmitted to the additional output of the voltage follower 11, which creates an input ($${\stackrel{}{I}}_{13}$$), and then output ($${\stackrel{}{I}}_{14}$$) current additional current amplifier 14:

$${\stackrel{}{I}}_{13}=\frac{{\stackrel{}{U}}_{\mathrm{in}sx.7}{\stackrel{}{K}}_{y11}}{1/j\omega C_{13}},\left(6\right)$$

$${\stackrel{}{I}}_{14}=j{\stackrel{}{K}}_{i14}{\stackrel{}{K}}_{y11}\omega C_{13}.\left(7\right)$$.

where$${\stackrel{}{K}}_{i14}$$complex coefficient transfer current additional einverseremove repeater DC 14;

$${\stackrel{}{K}}_{y11}$$complex coefficient transfer voltage optional voltage follower 11;

In the linear mode for complexes input () and output () stresses SNH you can write the following equations:

$${\stackrel{}{U}}_{\mathrm{in}s}$$ x .7 = Z H I u 1 1 - j ω C 13 K i 14 K y 11 . ( 8 )

where$${\stackrel{}{U}}_{C\mathrm{and}}={\stackrel{}{I}}_{u1}/S_1$$complex voltage gate-source field-effect transistor 1;

S1 is the slope of the field-effect transistor 1;

$${\stackrel{}{Z}}_H$$complex equivalent load resistance, and

$${\stackrel{}{Z}}_H=\frac{R_n}{1+j\omega C_n{R}_n}.\left(10\right)$$

The solution of equations (6)-(9) can be obtained, which in the present scheme, silos complex transmission coefficient voltage

$$msub>\stackrel{}{K}y=\frac{{\stackrel{}{U}}_{\mathrm{in}sx.7}}{{\stackrel{}{U}}_{\mathrm{in}x}}=\frac{1}{1+\frac{1}{S_1{R}_n}+j\omega t_{\mathrm{in}}},\left(11\right)$$

where$${\stackrel{}{t}}_{\mathrm{in}}=\left[{\mathrm{With\; a}}_{10}-C_{13}{\stackrel{}{K}}_{y11}{\stackrel{}{K}}_{i14}\right]S_1^{-1}-K\mathrm{about}mpleK\mathrm{with\; a}n\mathrm{and}Ip\mathrm{about}\mathrm{with\; a}t\mathrm{about}Inn\mathrm{and}I\mathrm{in}pemen\mathrm{and}Cep\mathrm{and}n\mathrm{and}gpyC\mathrm{the}\mathrm{and}.\left(12\right)$$

If$${\stackrel{}{K}}_{y11}=1$$,$${\stackrel{}{K}}_{i14}=1$$then the condition for reducing the influence of the load capacity With₁₀on the amplitude-frequency characteristic of the SNH 2 will be equality

$$\{\begin{array}{l}{t}_{\mathrm{in}}=0\\ \frac{C_{13}}{C_{10}}{K}_{y11}{K}_{i14}=1\end{array}.\left(13\right)$$

Therefore, in first approximation, the capacitance of the capacitor 13 is 10 must satisfy the condition C ₁₃≤C₁₀.

Thus, in the present scheme, the conditions for a substantial expansion of the small-signal frequency range, which in practice will be determined (and limited) by the additional inertia einverseremove current amplifier 14 and the additional voltage follower 11. However, these functional units can be performed at higher frequency (the field) bipolar transistors, because of their construction are not required to have a high input resistance and other properties that are not valid for the input transistor 1 (low noise level close to zero input conductivity, a wide range of linear operation and the like).

Performed the above analysis, and computer simulation results show that in the inventive scheme solved one of the problems of modern analog micro-circuitry - frequency range extension stokovyh (emitter) repeaters voltage at low input signal.

Besides, as follows from the graphs 5, 6, in the present scheme, when a capacitive load is significantly increased performance in large-signal mode - time transition process and the slew rate of the output voltage improve in the tens to hundreds of times.

Thus, the proposed device has significant mainly who define the company over the range of operating frequencies (small signal) and the speed (pulse when the input voltage).

BIBLIOGRAPHIC LIST

1. Patent US 6.919.743 fig.9

2. Patent US 7.898.339 fig.4

3. Patent US 6.727.729 fig.5B

4. Patent US 7.733.182 fig.1

5. Patent US 6.043.690 fig.1, fig.2

6. Patent US 3.678.402 fig.2, fig.7

7. Patent US 4.855.625 fig.1

8. Patent US 5.469.085 fig.2

9. Patent US 4.492.932 fig.4a

10. Patent US 4.092.701

11. Patent US 4.698.526 fig.2

12. Patent US 6.469.562 fig.A, fig.2A

13. Patent US 6.154.580

14. Patent US 8.248.161

15. Patent US 7.304.540

16. Patent US 7.944.303 fig.1

17. Patent US 8.148.962 fig.2

18. Patent US 4.123.723 fig.2, fig.3

19. Patent US 5.083.095 fig.4

20. Patent US 5.045.808

21. Patent US 4.101.788 fig.2

22. Patent US 3.436.672

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24. Patent 5.365.19

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1. Broadband voltage follower, containing the input transistor (1), managing the output of which (2) is connected with the input source (3)that injects the conclusion (4) is connected to the first (5) bus power supply through dakotabilities dvukhpolosnykh (6) and is connected to the primary output device (7)and collecting the charges output (8) associated with the second (9) bus of the power source and the primary output device (7) shunted by AC equivalent capacitor load (10), characterized in that thethe scheme introduced additional voltage follower (11), the input of which is connected to the primary output device (7), the output associated with additional output (12) of the device and through the ADJ is the tank capacitor (13) is connected with the input of additional einverseremove repeater power supply (14), the current output of which is connected with the main output device (12).

2. Broadband voltage follower according to claim 1, characterized in that as the input transistor (1) used field-effect transistor, the gate of which corresponds to the control output (2), the source - injects the conclusion (4), and the flow - collecting charges the output (8) of the input transistor 1.

3. Broadband voltage follower according to claim 1, characterized in that as the input transistor (1) is used bipolar transistor, the base of which corresponds to the control output (2), the emitter - injects the conclusion (4), and collector - collects the charges to the output (8) of the input transistor (1).