Analogue-to-digital converter and method for calibration thereof

FIELD: radio engineering, communication.

SUBSTANCE: high-speed N-bit combined analogue-to-digital converter (ADC) includes an input parallel M-bit ADC1, an M-bit digital-to-analogue converter (DAC1), using a common serial resistance divider, a reference voltage Vref source, a sampling and storage device (SSD) for the difference signal of the input of the ADC and output voltage of the DAC and a pipelined (M-M+1)-bit ADC2. Calibration includes calculating and loading into DAC2 a calibration code CR and calibration codes CSi of each segment, used during normal operation as additive adjustments to the output code of the ADC, wherein a signal close to zero is generated through a unit transmission coefficient of the first stage of an ADC2 pipeline. In ADC, using SSD and ADC2 with double sampling, the DAC2 and Vref2 source are doubled and generate voltages Vref2A and Vref2B separately for each of two samplers A and B.

EFFECT: high accuracy of calibrating an N-bit combined ADC by reducing the conversion error of the ADC by reducing the effect of mismatch of parameters of components via calibration.

8 cl, 6 dwg, 1 tbl

The invention relates to electronics and can be used in microelectronic processing systems analog signals and convert the analog information to digital, in particular in high-speed analog-to-digital converters (ADC).

The purpose of the invention is the reduction of error of the ADC conversion by reducing the influence of the error element parameters using calibration.

There are many schemes of high-speed ADC and methods for their calibration. For example, in U.S. patent 6617992 B2 from 09.09.2003,, MKI NM 1/38 "Capacitor mismatch independent gain stage for differential pipeline analog to digital converters" presents a pipelined ADC with calibration mismatch of the capacitors in the cascades ADC. In this ADC, the influence of the error of the capacitors on the conversion error is eliminated by introducing additional units switchable capacitors and use a special calculation method codes generated by cascades ADC, and the ADC output code.

Methods of calibration of ADC and their effectiveness is largely determined by the architecture and features of the ADC. The object of the present invention is the circuit implementation and the method of calibrating the ADC, using a combined architecture with parallel ADC input and subsequent pipelined ADC with reduced range of signals.

Most Blimber is Kimi to declare, is high-speed ADC and the method of its calibration, presented in the patent of the Russian Federation No. 2442279, MKI NM 1/14 published 10.02.2012, salient features of the scheme known ADC prototype is depicted in figure 1.

Known N-bit ADC includes:

M-bit parallel ACP 110, the inlet of which is connected to the input of the ADC 100, the M-bit digital-to-analogue Converter (CAP) 120, the input of which is controlled by the output ACP, and ACP and CAP use a common serial resistive divider 130, connected to the reference voltage Vref 135;

device sampling and storage (water economy Department) 140 that generates an output signal equal to or a multiple of the difference between the input signal of the ADC and the output signal TAP;

- (N-M+1) - bit pipelined ACP 150 with the input connected to the output of the water economy Department;

- reference source Vref2 152 with the lower voltage of the voltage source Vref;

block logic ADC 160, forming of the output codes ACP 162 and ASP 164 ADC output code 166;

- 171 first and second Comparators 172 calibration, switching when the input signal ACP equal to its full scale and negative full scale, respectively;

- CAPC calibration 270 forming during calibration, the input signal of the water economy Department;

- CAPC 180 that controls the voltage source Vref2 152;

the logic block calibration 190, the input of which is connected to the output ACP Comparators 164 and is alibabki 171 and 172, and outputs control inputs CAP, CAPC and CAPC.

Known for the prototype ADC is as follows.

ACP 110 connected to the reference voltage Vref 135, produces a parallel analog-to-digital conversion of the input signal voltage range Vref, and determines the M high-order bits of the output code of the ADC. The result of the conversion ACP is fed to the input M-bit CAP 120, which forms at its output a voltage equal to one of the 2^M+1 the reference levels of the divider 130 closest to the input signal. The water economy Department 140 generates at its output a signal equal to or a multiple of the difference between the input signal of the ADC 100 and the output voltage CAP.

To create optimal from the point of view of speed and accuracy conditions amplifiers and key water economy Department and ACP output range of the water economy Department reduce and shift down. The output range of the water economy Department becomes less voltage source Vref, and to work ACP necessary additional source of reference voltage Vref2 is smaller than a voltage source Vref. In practice, the gain of the water economy Department is chosen equal to 1 or 2.

The logic block ADC 160 forms of M-bit code ACP 162 and (N-M+1)-bit code ACP 164 N-bit output code of the ADC 166 using excessive discharge for digital error correction.

The advantage of considering known ADC are mind is Glennie relative to the input signal of the ADC amplitude and phase of the signal level at the output of the water economy Department and ACP. This allows to significantly increase the speed of the ADC, to reduce its power consumption and the accuracy of the transformation. However, there is a need for additional reference voltage Vref2. For the formation voltage Vref2 may be, for example, used the appropriate tap of a resistive divider 130 (hereinafter - bend) with a buffer amplifier. The inevitable errors of the formation voltage Vref2 are eliminated by calibration zero offset of the buffer amplifier using CAPC 180-driven logic block calibration 190. As a source of reference voltage for calibration of used segments of the resistive divider 130. The calibration results for all segments are averaged. In the description of the prototype is given a rigorous proof that this method of calibration mismatch of the resistors of the divider 130 does not generate error calibration.

During calibration block calibration logic 190 delivers on CAP and CAPC related codes so that the differential input voltage is the water economy Department is equal to the voltage on one of the segments of the resistive divider. In this state, the voltage at the input ACP corresponds to full scale or minus full scale, depending on the polarity of the differential voltage at the inputs of the water economy Department. When this analog input of the ADC 100 is disconnected from the water economy Department. Next, a method consistent with what Ligeia define this input code CAPC 180, when switches 171 first (or second 172) comparator calibration. After averaging over all segments receive a code C_Rthat corresponds to the reference voltage source Vref2, matching full scale ACP with the magnitude of the output signal of the water economy Department, defined the input reference voltage Vref. Code C_Rdownload in Capk after calibration during normal operation of the ADC.

Another advantage of the known ADC is the elimination of errors caused by misalignment of the divider resistors. In the calibration process in addition to code calibration C_Rsource Vref2 also calculate additive amendments of segments C_Si292 (see figure 1), compensating the random deviations of the resistors. This type of calibration is particularly important for the ADC with a resolution of more than 12 bits.

In the calibration process ACP processes in the pipeline voltage close to full scale (or minus full scale). In this mode, the calibration accuracy is limited by the errors of the establishment.

Calibration source Vref2, allows to compensate the following sources of errors:

the zero offset of the buffer amplifier reference voltage Vref2;

- mismatch of the resistors of the divider in the reference point of diversion source Vref2;

error gain the water economy Department;

error scale ACP.

The last two errors call the Ana by the mismatch of the capacitors, respectively, in the water economy Department and in all stages of the pipeline ACP. If the water economy Department and ACP perform double sampling samplers and errors in different samples differ. A method of calibrating the prototype does not take into account different errors samplers.

Thus, significant deficiencies described ADC and method of its calibration are:

- limiting the accuracy of the calibration error setting when processing in the pipeline ACP voltage close to full scale;

the inability of individual calibration mismatch of capacitors in different samples of the water economy Department and ASP.

The aim of the present invention is to reduce the error of the ADC conversion by reducing errors setting in the pipeline ACP during calibration and the introduction of individual calibration source Vref2 for different samples in ADC with dual sample.

This goal is achieved by the fact that in the N-bit ADC with calibration, including M-bit parallel ACP, whose input is connected to the ADC input, the M-bit CAP, the entrance of which is controlled by the output ACP, water economy Department that generates an output signal equal to or a multiple of the difference between the input signal of the ADC and the output signal CAP, CAPC, forms the input signal of the water economy Department during calibration, and ACP, CAP and CAPC use is connected to the reference voltage Vref common serial resistive divider, the taps of which are connected to CAP and CAPC, Oprah is elaut boundaries of the calibrated segments, (N-M+1)-bit pipelined ACP connected to the output of the water economy Department and a reference voltage Vref2, a smaller voltage Vref, the logic block ADC that generates output codes ACP and ACP output code ADC, CAPC, managing voltage Vref2, the logic block calibration, the input of which is connected to the output ACP, and the output controls CAP, CAPC and CAPC, when calibrating the first stage of the pipeline ACP has a unit gain and forms in the pipeline close to zero difference signals exit the water economy Department and voltage Vref2.

This goal is achieved by way of calibration, in which for each i=1÷2^Minput CAP served code i, and the input CAPC served code i-1 and define With_+Ficodes CAPC corresponding Nicodemou transition (2^N-M) ASP, and C_+Dicodes CAPC corresponding Nicodemou transition (2^N-MD) ACP, where D≥1, for each i=1÷2^Minput CAP served code i-1, and the input CAPC code i define a C_-Ficodes CAPC corresponding Nicodemou transition (2^N-M) ASP, and C_-Dicodes CAPC corresponding Nicodemou transition (2^N-M+D) ACP, where D≥1, for each i=1÷2^Mcalculate the average code values C_Fi=(C_+Fi+C_-Fi)/2 and C_Di=(C_+Di+C_-Di)/2, code C_Ficalculate and load in CAPC code C_Rcalibration source Vref2, code C_Fiand C_Dicalculate codes C_{Si calibration of each segment used during normal operation as additive corrections to the output code of the ADC.}

_{This goal is achieved by the fact that in the N-bit ADC with calibration, including M-bit parallel ACP, whose input is connected to the ADC input, the M-bit CAP, the entrance of which is controlled by the output ACP, water economy Department with double sampling, to be completed by samples a and b, and generates an output signal equal to or a multiple of the difference between the input signal of the ADC and the output signal CAP, CAPC, forms the input signal of the water economy Department during calibration, and ACP, CAP and CAPC use is connected to the reference voltage Vref common serial resistive divider, the taps of which are connected to CAP and CAPC, define the boundaries of the calibrated segments (N-M+1)-bit pipelined ACP with double sampling, to be completed by samples a and b in each stage of the pipeline connected to the output of the water economy Department and a reference voltage Vref2, a smaller voltage Vref, the logic block ADC that generates output codes ACP and ACP output code ADC, CAPC, managing voltage Vref2, the logic block calibration, the input of which is connected to the output ACP, and the output controls CAP, CAPC and CAPC, when calibrating the first stage of the pipeline ACP has a single gear ratio and forms in the pipeline is close to zero the difference is Ignatov exit the water economy Department and voltage Vref2, the logic block calibration defines the codes calibration source Vref2 individually for the samples a and b, and the source Vref2, managed dual CAPC with the switch forms when the work of the ADC voltage Vref2A or Vref2B corresponding to the sampler And or In the first stage of the pipeline.}

_{This goal is achieved also by a method of calibration, in which for each i=1÷2^Minput CAP served code i, and the input CAPC served code i-1 and define C+Ficodes CAPC corresponding Nicodemou transition (2^N-M) ASP, and C+Dicodes CAPC corresponding Nicodemou transition (2^N-MD) ACP, where D≥1, for each i=1÷2^Minput CAP served code i-1, and the input CAPC code i define a C-Ficodes CAPC corresponding Nicodemou transition (2^N-M) ASP and C-Dicodes CAPC corresponding Nicodemou transition (2^N-M+D) ACP, where D≥1, for each i=1÷2^Mcalculate the average code values CFi=(C+Fi+C-Fi)/2 and CDi=(C+Di+C-Di)/2, code CFicalculate and load in a dual CAPC codes CRAand CRBcalibration source Vref2, code CFiand CDicalculate codes CSicalibration of each segment used during normal operation as additive corrections to the output code of the ADC.}

In the particular case of ADC performance goal is achieved SPO is obom, which codes calibration source Vref2 is calculated by the formula

$$C_{RA}=\stackrel{}{C_{FAi}},C_{RB}=\stackrel{}{C_{FBi}},gdei=1÷2^M,$$

a C_FAiC_FBithere are codes C_Fidetermined during calibration through samplers a and b, respectively, code calibration of each segment is calculated by the formula

$$C_{Si}=\left[{\displaystyle \underset{k=1}{\overset{i}{\sum }}\left(C_{RA}+C_{RB}-C_{FAk}-C_{FBk}\right)\cdot Q/2}\right],gdei=1÷\left(2^M-1\right),$$

and the weight Q of the same bit ACP, expressed in bits CAPC, calculated by the formula

$$Q=\frac{2^{N-M}}{2^{N-M}-D}\cdot \frac{2D}{\stackrel{}{C_{DAi}}+\stackrel{}{C_{DBi}}-C_{RA}-C_{RB}},gdei=1÷2^M,$$

a C_DAiC_DBithere are codes C_Didetermined during calibration through samplers a and b, respectively, or by approximate formula

$$Q=\frac{2D}{\stackrel{}{C_{DAi}}+\stackrel{}{C_{DBi}}-C_{RA}-C_{RB}}$$

The goal even more is achieved by the N-bit ADC with calibration includes M-bit parallel ACP, whose input is connected to the ADC input, the M-bit CAP, the entrance of which is controlled by the output ACP, water economy Department with double sampling, to be completed by samples a and b, and generates an output signal equal to or a multiple of the difference between the input signal of the ADC and the output signal CAP, CAPC, forms the input signal of the water economy Department during calibration, and ACP, CAP and CAPC use is connected to the reference voltage Vref common serial resistive divider, the taps of which are connected to CAP and CAPC, define the boundaries of the calibrated segments (N-M+1)-bit pipelined ACP with double sampling, to be completed by samples a and b in each stage of the pipeline connected to the output of the water economy Department and a reference voltage Vref2, a smaller voltage Vref, the logic block ADC that generates output codes ACP and ACP output code ADC, CAPC, managing voltage Vref2, the logic block calibration, the input of which is connected to the output ACP, and the output controls CAP, CAPC and CAPC, when calibrating the first stage of the pipeline ACP has a unit gain and forms in the pipeline close to zero difference signals exit the water economy Department and voltage Vref2, the logic block calibration defines the codes calibration source Vref2 individually for the samples a and b, and the source Vref2 and CAPC dual and form in the work of the ADC voltage is agenia Vref2A and Vref2B respectively for samples a and In all stages of the pipeline.

This goal is achieved also by a method of calibration, in which for each i=1÷2^Minput CAP served code i, and the input CAPC served code i-1 and define With_+Ficodes CAPC corresponding Nicodemou transition (2^N-M) ASP, and C_+Dicodes CAPC corresponding Nicodemou transition (2^N-MD) ACP, where D≥1, for each i=1÷2^Minput CAP served code i-1, and the input CAPC code i define a C_-Ficodes CAPC corresponding Nicodemou transition (2^N-M) ASP, and C_-Dicodes CAPC corresponding Nicodemou transition (2^N-M+D) ACP, where D≥1, for each i=1÷2^Mcalculate the average code values C_Fi=(C_+Fi+C_-Fi)/2 and C_Di=(C_+Di+C_-Di)/2, code C_Ficalculate and load in a dual CAPC codes C_RAand C_RBcalibration dual source Vref2, code C_Fiand C_Dicalculate codes C_Sicalibration of each segment used during normal operation as additive corrections to the output code of the ADC.

In the particular case of ADC performance goal is achieved by the method in which the codes of the calibration source Vref2 is calculated by the formula

$$C_{RA}=\stackrel{}{C_{FAi}},C_R=\stackrel{}{C_{FBi}},gdei=1÷2^M,$$

and C_FAiC_FBithere are codes C_Fidetermined during calibration through samplers a and b, respectively, code calibration of each segment is calculated by the formula

$$C_{Si}=\left[{\displaystyle \underset{k=1}{\overset{i}{\sum }}\left(C_{RA}+C_{RB}-C_{FAk}-C_{FBk}\right)\cdot Q/2}\right],gdei=1÷\left(2^M-1\right),$$

and the weight Q of the same bit ACP, expressed in bits CAPC, calculated by the formula

$$Q=\frac{2^{N-M}}{2^{N-M}-D}\cdot \frac{2D}{\stackrel{}{C_{DAi}}+\stackrel{}{C_{DBi}}-C_{RA}-C_{RB}},gdei=1÷2^M,$$

and C_DAiC_DBithere are codes C_Didetermined during calibration through samplers a and b, respectively, or by approximate formula

$$Q=\frac{2D}{\stackrel{}{C_{DAi}}+\stackrel{}{C_{DBi}}-C_{RA}-C_{RB}}$$

The invention is illustrated by drawings:

- figure 1 shows the structural diagram is closest to declare known ADC (prototype);

- figure 2 presents a structural diagram of the inventive ADC according to claim 1 of the Formula;

- 3 shows the structural diagram of the first cascade ACP according to claims 1 and 3 Formulas;

- figure 5 presents a structural diagram of the inventive ADC according to claim 6 of the Formula;

- figure 6 presents the structural diagram of the first cascade ACP according to claim 6 of the Formula;

Below is a description of the structure and operation of the inventive ADC.

Figure 2 presents a structural diagram of the inventive ADC according to claim 1 of the Formula. The input signal 100 is supplied to the inputs ACP 110 and the water economy Department 140. ACP connected to the reference voltage Vref 135, produces a parallel analog-to-digital conversion of the input signal and determines the M high-order bits of the output code of the ADC. The result of the conversion ACP is fed to the input M-bit CAP 120 that generates the output voltage equal to the voltage of one of the 2^M+1 the reference levels of the divider 130 closest to the input signal. The water economy Department 140 generates at its output a voltage equal to or a multiple of the difference between the input signal of the ADC and the output voltage CAP. The output signal of the water economy Department arrives on the input conveyor (N-M+1)-bit ACP 150. The logic block ADC 160 collects the M-bit code ACP 162 and (N-M+1)-bit code ACP 164 in the N-bit output code of the ADC 166. Redundancy codes used for error correction Comparators ACP.

The output range of the water economy Department and, therefore, the range of signals ACP choose a smaller range of input to the ADC. For example, the R, when M=4, the strengthening of the water economy Department, equal to 2, and taking into account twice margin for error correction Comparators ACP output range of the water economy Department equal to V_ref/2^M-2or V_ref/4. Reduced range of signals the water economy Department and ACP allows you to reduce errors, and reduce power consumption and increase performance by reducing the speed requirements and the gain of the amplifiers. As a consequence, for ACP necessary source 152 reference voltage Vref2 equal to the output range of the water economy Department. Source Vref2 may be, for example, used the tap of a resistive divider 130 with a buffer amplifier. When the formation voltage Vref2 are the inevitable errors associated in particular with the mismatch of the resistors of the divider and the zero offset of the buffer Vref2. The mismatch of the resistors of the divider causes the error segments requiring calibration.

3 shows the structural diagram of the first cascade ACP representing differential Redundant Signed Digit (RSD) stage with double sampling, including two differential sampler on switched capacitors. Sampler 310 And includes two shoulder 312 and 314. Sampler 320 includes two shoulder 322 and 324. Figure 3 shows the details of only one positive shoulder a sampler 312 And 310. Other shoulders 314, 322 and 324 have the same structure. Signals Vip 330 and 332 Vin form the door the AUX input. Signals Vrp 340 and Vrn 342 form a differential reference signal. Signals Vop 350 and 352 Von form a differential output signal. Cascade has two samplers differential amplifier 360. Key 376 connects the left on the diagram the capacitor plate SR 371 to a reference voltage. The well-known scheme of RSD stage has 3 key that connects the left capacitor plate SR 371 to a reference voltage, the ground potential or negative reference voltage depending on the magnitude of the input signal. In this part of the proposed solution does not differ from the known, and to simplify figure 3 shows only one key 376 instead of three.

In accordance with paragraph 1 of the Formula when calibrating the first stage of the pipeline ACP has a single gear ratio. This is achieved by introducing an additional key 373 in the first stage of the pipeline ACP during calibration. This key is not present in the prototype and in all stages of the inventive ADC, except the first.

Figure 3 keys 374, 375, 378 are in a conducting state, the keys 376, 377, 379 are in non-conductive state, and the entire sampler - state sample. Mentioned keys of the sampler are in the opposite state, and the sampler In - store. When the calibration status of the sample instead of the key 374 is transferred to the conducting state key 373. Configured ka is the CR has a transfer function during normal operation V _ON=2·V_I-V_Rand when calibrating the V_OC=1·V_I-V_R. When calibrating to the input of the cascade voltage is applied to one segment of the divisor, that is, a voltage close to Vref2: V_I≈V_R. Therefore, V_OC≈0, and close to zero voltage is processed in the subsequent stages ACP. Obviously, in these conditions, the error establishing a calibration minimum even at the maximum conversion frequency because it does not require time to establish a signal with finite rate of growth to the level of the reference voltage. This provides a positive effect in the inventive ADC.

In accordance with paragraph 2 of the Formula calibration is performed as follows. For each i=1÷2^Minput CAP served code i, and the input CAPC served code i-1 and define C_+Ficodes CAPC corresponding Nicodemou transition (2^N-M) ASP, and C_+Dicodes CAPC corresponding Nicodemou transition (2^N-MD) ACP, where D≥1. It is important that the conveyor ACP handles close to zero signal, and the comparator calibration 171 and 172 (Fig 1)used in the prototype is no longer needed. Next, for each i=1÷2^Minput CAP served code i-1, and the input CAPC code i define a C_-Ficodes CAPC corresponding Nicodemou transition (2^N-M) ASP, and C_-Dicodes CAPC corresponding Nicodemou transition (2^-M +D) ACP, where D≥1, for each i=1÷2^Mcalculate the average code values C_Fi=(C_+Fi+C_-Fi)/2 and C_Di=(C_+Di+C_-Di)/2. Code C_Ficalculate and load in CAPC code C_Rcalibration source Vref2, code C_Fiand C_Dicalculate codes C_Sicalibration segments used during normal operation as additive corrections to the output code of the ADC.

Code C_Rcalibration source Vref2 is calculated by the formula:

Codes calibration segments calculated by the formula

$$C_{Si}=\left[{\displaystyle \underset{k=1}{\overset{i}{\sum }}\left(C_R-C_{Fk}\right)\cdot Q}\right],gdei=1÷\left(2^M-1\right),(2)$$

and the weight Q of the same bit ACP, expressed in bits CAPC, calculated by the formula

$$Q=\frac{2^{N-M}}{2^{N-M}-D}\cdot \frac{2D}{\stackrel{}{C_{Di}}-C_R},gdei=1÷2^M,(3)$$

or approximate formula

$Q=\frac{D}{\stackrel{}{C_{Di}}-C_R}(4)$

Conclusion expressions (1÷4) are given in the description of the prototype.

The calibration method proposed in section 2 Formulas that involves a twofold definition of the codes C_Fiand C_Difor each segment with different polarity signals at the output of the water economy Department with subsequent averaging. However, perhaps the single defining C_Fiand C_Dias in claim 4 f is rmula prototype. This calibration results become dependent on the offset of the ADC, and to eliminate this dependence requires a preliminary calibration zero offset. This option calibration discussed in the description of the prototype.

4 shows a structural diagram of the inventive ADC according to claim 3 of the Formula, including additional switch 482 and use a dual CAPC 480. This scheme is proposed for ADC with double sampling. Different mismatch of capacitors in different samplers and In the water economy Department and the cascades ACP leads to different errors scale ACP when converting via samplers a and B. These errors affect determined during calibration code C_Rand ADC and method of calibration according to claims 1 and 2 of the Formula does not allow for different errors in the samples a and B. the ADC according to claim 3 of Formula (4) dual CAPC 480 generates individual signals for the calibration of samplers a and b, and the switch 482 submits to the source Vref2, the signal calibration corresponding to the first sampler cascade ACP, in the storage mode. It is important to note that when passing through the pipeline ACP there is an alteration of the samples a and b, in the storage mode. Therefore, only odd samplers will have the exact value Vref2. However, due to the fact that the contribution of the errors in each of the next cascade ACP in the overall error of the ADC decreases in 2 times, pre is proposed in clause 3 of the Formula solution allows to reduce the error of the error of samplers at least 2 times.

It should be noted that for efficiency calibration and reduce calibration errors caused by the process of setting the output voltage dual CAPC at a high frequency, it is advisable to perform CAPC with current outputs and to use as a switch circuit switching the current calibration signals supplied to the buffer amplifier Vref2 and changing the zero offset.

To declare according to claim 3 of the Formula ADC is proposed modified method of calibration. In accordance with paragraph 4 of Formulas similar codes C_Fiand C_Didefine the codes C_FAiC_FBiC_DAiC_DBiduring calibration through samplers a and b, respectively. Code C_FAiC_FBicalculate and load in a dual CAPC codes C_RAand C_RBcalibration source Vref2, code C_FAiC_FBiC_DAiC_DBicalculate codes C_Sicalibration segments used during normal operation as additive corrections to the output code of the ADC.

In accordance with paragraph 4 of Formula codes C_RAand C_RBcalculated by the formula:

$$C_{RA}=\stackrel{}{C_{FAi}},C_{RB}=\stackrel{}{C_{FBi}},gdei=1÷2^M(5)$$

Codes calibration segments calculated by the formula:

$$C_{Si}=\left[{\displaystyle \underset{k=1}{\overset{i}{\sum }}\left(C_{RA}+C_{RB}-C_{FAk}-C_{FBk}\right)\cdot Q/2}\right],gdei=1÷\left(2^M-1\right),(6)$$

and the weight Q of the same bit ACP, expressed in bits CAPC, calculated by the formula:

$$Q=\frac{2^{N-M}}{2^{N-M}-D}\cdot \frac{2D}{\stackrel{}{C_{DAi}}+\stackrel{}{C_{DBi}}-C_{RA}-C_{RB}},gdei=\mathrm{}÷2^M,(7)$$

or approximate formula:

$$Q=\frac{2D}{\stackrel{}{C_{DAi}}+\stackrel{}{C_{DBi}}-C_{RA}-C_{RB}}(8)$$

In other words, each of the calibration codes C_RAand C_RBin the expression (5) depends on the mismatch of the capacitors only in their samplers, respectively a and b, while codes of calibration segments C_Siand the weight Q of the same bit ACP in expressions (6, 7, 8) depend on both samplers. These expressions are similar to the expressions (2, 3, 4), but involve averaging over the samples.

Figure 5 presents a structural diagram of the inventive ADC according to claim 6 of the Formula, using dual CAPC 480 & source Vref2 552. This scheme allows you to apply the exact value Vref2 on each of the samples a and b in all stages ATP and, consequently, to fully calibrate different errors scale ACP for samples a and B. figure 6 presents a structural diagram of the first stage ACP, which captures the details of the connection of the dual source Vref2 to different samplers. The sampler 310 And is connected to the positive shoulder Vrap 344 is negative shoulder Vran 345 of the first dual source Vref2. The sampler 320 is connected to the positive shoulder Vrbp 346 and a negative shoulder Vrbn 347 of the second output dual source Vref2.

Methods for the calibration of the ADC, the claimed PP and 6 Formulas similar, so that a separate description of the calibration method according to claims 7 and 8 is not required.

Verification of the claimed ADC and methods for their calibration is performed by comparing the simulation results known for the prototype and declare the ADC.

Thus, the results of circuit simulation, 16-bit ADC technology 180 nm RMS error setting during calibration at a frequency of 125 MHz is 1.0 units LSB (EMP) for the prototype and 0.2 EMP for the proposed in claim 1 of the Formula solution.

To assess the effectiveness of pastelero calibration of the ADC on PP and 6 Formulas and corresponding methods of calibration conducted statistical modeling 16-bit ADC using the manufacturer information on the spread of the divider resistors ACP and CAP and condensers the water economy Department and RSD cascades to 180 nm CMOS process. The sample size is 1000 ADC.

The simulation results are presented in the table below:

Thus, the claimed PP and 6 Formula ADC with ways calibration claims 4, 5, and 7, 8 Formulas allow to implement ADC 16-bit. Electrical simulation of the ADC according to claim 3 Formula, 180 nm CMOS technology showed the achievable accuracy of the parameters, the corresponding 14-bit ADC, the sampling rate of 125 MHz.

Thus, the claimed ADC and the method of its calibration have novelty, can be implemented and can significantly improve the accuracy of the calibration of the ADC, allowing the implementation of high-speed ADC with a resolution of more than 12.

1. N-bit analog-to-digital Converter (ADC) with calibration, including M-bit parallel ACP, whose input is connected to the ADC input, M-R is Sredny digital to analog Converter (CAP), the entrance of which is controlled by the output ACP, device selection, and retention (water economy Department)that generates an output signal equal to or a multiple of the difference between the input signal of the ADC and the output signal CAP, CAPC, forms the input signal of the water economy Department during calibration, and ACP, CAP and CAPC use is connected to the reference voltage Vref common serial resistive divider, the taps of which are connected to CAP and CAPC, define the boundaries of the calibrated segments (N-M+1)-bit pipelined ACP connected to the output of the water economy Department and a reference voltage Vref2, a smaller voltage Vref, the logic block ADC, forming of the output codes ACP and ACP output code ADC, CAPC, managing voltage Vref2, the logic block calibration, the input of which is connected to the output ACP, and the output controls CAP, CAPC and CAPC, and characterized in that when calibrating the first stage of the pipeline ACP has a unit gain and forms in the pipeline close to zero difference signals exit the water economy Department and voltage Vref2.

2. A method of calibrating the ADC according to claim 1, characterized in that for each i=1÷2^Minput CAP served code i, and the input CAPC served code i-1 and define With_+Ficodes CAPC corresponding Nicodemou transition (2^N-M) ASP, and C_+Dicodes CAPC corresponding Nicodemou transition (2^N-MD) ACP, where D≥1, for each i=1÷2^Minput CAP serves the code i-1, and the input CAPC code i define a C_-Ficodes CAPC corresponding Nicodemou transition (2^N-M) ASP, and C_-Dicodes CAPC corresponding Nicodemou transition (2^N-M+D) ACP, where D≥1, for each i=1÷2^Mcalculate the average code values C_Fi=(C_+Fi+C_-Fi)/2 and C_Di=(C_+Di+C_-Di)/2, code C_Ficalculate and load in CAPC code C_Rcalibration source Vref2, code C_Fiand C_Dicalculate codes C_Sicalibration of each segment used during normal operation as additive corrections to the output code of the ADC.

3. N-bit ADC with calibration, including M-bit parallel ACP, whose input is connected to the ADC input, the M-bit CAP, the entrance of which is controlled by the output ACP, water economy Department with double sampling, to be completed by samples a and b, and generates an output signal equal to or a multiple of the difference between the input signal of the ADC and the output signal CAP, CAPC, forms the input signal of the water economy Department during calibration, and ACP, CAP and CAPC use is connected to the reference voltage Vref common serial resistive divider, the taps of which are connected to CAP and CAPC, define the boundaries of the calibrated segments (N-M+1)-bit pipelined ACP with double sampling, to be completed by samples a and b in each stage of the pipeline, under the prison to release the water economy Department and a reference voltage Vref2, lower voltage Vref, the logic block ADC that generates output codes ACP and ACP output code ADC, CAPC, managing voltage Vref2, the logic block calibration, the input of which is connected to the output ACP, and the output controls CAP, CAPC and CAPC, and characterized in that when calibrating the first stage of the pipeline ACP has a unit gain and forms in the pipeline close to zero difference signals exit the water economy Department and voltage Vref2, the logic block calibration defines the codes calibration source Vref2 individually for the samples a and b, and the source Vref2, managed dual CAPC with the switch, forms in the work of the ADC voltage Vref2A or Vref2B corresponding to the sampler And or In the first stage of the pipeline.

4. A method of calibrating the ADC according to claim 3, characterized in that for each i=1÷2^Minput CAP served code i, and the input CAPC served code i-1 and define With_+Ficodes CAPC corresponding Nicodemou transition (2^N-M) ASP, and C_+Dicodes CAPC corresponding Nicodemou transition (2^N-MD) ACP, where D≥1, for each i=1÷2^Minput CAP served code i-1, and the input CAPC code i define a C_-Ficodes CAPC corresponding Nicodemou transition (2^N-M) ASP, and C_-Dicodes CAPC corresponding Nicodemou transition (2^N-M+D) ACP, where D≥1, for each i=1÷2^Mcalculate the average code values C_Fi=C _+Fi+C_-Fi)/2 and C_Di=(C_+Di+C_-Di)/2, code C_Ficalculate and load in a dual CAPC codes C_RAand C_RBcalibration source Vref2, code C_Fiand C_Dicalculate codes C_Sicalibration of each segment used during normal operation as additive corrections to the output code of the ADC.

5. A method of calibrating the ADC according to claim 4, characterized in that the codes of the calibration source Vref2 is calculated by the formula
,
a C_FAiC_FBithere are codes C_Fidetermined during calibration through samplers a and b, respectively, code calibration of each segment is calculated by the formula
,
and the weight Q of the same bit ACP, expressed in bits CAPC, calculated by the formula
,
a C_DAiC_DBithere are codes C_Didetermined during calibration through samplers a and b, respectively, or by approximate formula

6. N-bit ADC with calibration, including M-bit parallel ACP, whose input is connected to the ADC input, the M-bit CAP, the entrance of which is controlled by the output ACP, water economy Department with double sampling, to be completed by samples a and b, and generates an output signal equal to or a multiple of the difference between the input signal of the ADC and the output signal CAP, CAPC forming the input signal is the water economy Department during calibration, and ACP, CAP and CAPC use is connected to the reference voltage Vref common serial resistive divider, the taps of which are connected to CAP and CAPC, define the boundaries of the calibrated segments (N-M+1)-bit pipelined ACP with double sampling, to be completed by samples a and b in each stage of the pipeline connected to the output of the water economy Department and a reference voltage Vref2, a smaller voltage Vref, the logic block ADC that generates output codes ACP and ACP output code ADC, CAPC, managing voltage Vref2, the logic block calibration, the input of which is connected to the output ACP, and the output controls CAP, CAPC and CAPC, and characterized in that when calibrating the first stage of the pipeline ACP has a unit gain and forms in the pipeline close to zero difference signals exit the water economy Department and voltage Vref2, the logic block calibration defines the codes calibration source Vref2 individually for the samples a and b, and the source Vref2 and CAPC dual and form in the work of the ADC voltage Vref2A and Vref2B respectively for samples a and In all stages of the pipeline.

7. A method of calibrating the ADC according to claim 6, characterized in that for each i=1÷2^Minput CAP served code i, and the input CAPC served code i-1 and define C_+Ficodes CAPC corresponding Nicodemou transition (2^N-M) ASP, and C_+Dicodes CAPC correspond to the s Nicodemou transition (2 ^N-MD) ACP, where D≥1, for each i=1÷2^Minput CAP served code i-1, and the input CAPC code i define a C_-Ficodes CAPC corresponding Nicodemou transition (2^N-M) ASP, and C_-Dicodes CAPC corresponding Nicodemou transition (2^N-M+D) ACP, where D≥1, for each i=1÷2^Mcalculate the average code values C_Fi=(C_+Fi+C_-Fi)/2 and C_Di=(C_+Di+C_-Di)/2, code C_Ficalculate and load in a dual CAPC codes C_RAand C_RBcalibration dual source Vref2, code C_Fiand C_Dicalculate codes C_Sicalibration of each segment used during normal operation as additive corrections to the output code of the ADC.

8. A method of calibrating the ADC according to claim 7, characterized in that the codes of the calibration source Vref2 is calculated by the formula
,
a C_FAiC_FBithere are codes C_Fidetermined during calibration through samplers a and b, respectively, code calibration of each segment is calculated by the formula
,
and the weight Q of the same bit ACP, expressed in bits CAPC, calculated by the formula
,
a C_DAiC_DBithere are codes C_Di,determined during calibration through samplers a and b, respectively, or by approximate formula
.