Hybrid differential amplifier. RU patent 2519373.
 Controlled selective amplifier / 2519035Controlled selective amplifier comprises an input signal source, two input transistors, two current-stabilising two-terminal elements, a power supply, a current mirror, two balancing capacitors, a resistor and a buffer amplifier. The input transistors used are field-effect transistors, whose sources correspond to the emitter, the drain to the collector and the gate to the base of a bipolar transistor. |
 Instrumentation amplifier / 2519032Instrumentation amplifier comprises: an input precision converter of (1) of a first (2) and a second (3) input voltage source connected to a common power supply bus (4), a first (9), a second (10) and a third (11) feedback resistor, an active adder (12) with an inverting (13) and a non-inverting (14) input. |
 Differential operational amplifier with passive parallel channel / 2517699Differential operational amplifier with a passive parallel channel comprises two input transistors, two output transistors which are junction gate field-effect transistors, a non-inverting stage and a controlled current source. |
 Low current consumption selective amplifier for sige technological processes / 2515544Invention relates to radio engineering. The device has first and second input transistors, emitters of which are connected through a first current-stabilising two-terminal element to a first power supply bus, an input voltage source connected to the base of the second input transistor, first and second frequency-setting resistors, a first balancing capacitor, wherein the collector of the first input transistor is connected to a second power supply bus. The collector of the second input transistor is connected to the second power supply bus through the first frequency-setting resistor and is connected through alternating current to the second power supply bus through series-connected first and second additional balancing capacitors, the common node of which is connected to the output of the device and the base of the first input transistor, wherein the base of the first input transistor is connected through alternating current to the common power supply bus through the second frequency-setting resistor. |
 Broadband cascade amplifier / 2513486Invention relates to radio engineering and communication and can be used as an analogue signal amplifier in analogue microcircuit structures of various purposes (e.g. broadband and selective HF and UHF amplifiers) The broadband cascade amplifier includes an input transistor (1) whose source is connected to a first (2) power supply bus, the gate is connected to an input voltage source (3) and the drain is connected to a first (4) output transistor and the inverting input of an auxiliary voltage amplifier (5), the output of which is connected to the gate of the first (4) output transistor, and the non-inverting input is connected to a reference voltage source (6), a load circuit (7), connected between the output of the device (8) and a second power supply bus (9). The drain of the first (4) output transistor is connected to the source of an additional transistor (10), the drain of which is connected to the output of the device (8) and the gate is connected to the input of an additional non-inverting current amplifier (11), the output of which is connected to the source of the first (4) output transistor or the source of the additional transistor (10), wherein an additional current-stabilising two-terminal element (12) is connected between the second (9) power supply bus and the input of the additional non-inverting current amplifier (11). |
 Selective amplifier / 2507676Selective amplifier has an input signal source, a voltage-to-current converter, an input transistor, an auxiliary voltage source, first and second frequency-setting resistors, first and second balancing capacitors, an additional current mirror and two current-stabilising two-terminal elements. The input signal source is connected to the input of the voltage-to-current converter. The base of the input transistor is connected to the auxiliary voltage source. The output of the voltage-to-current converter is connected to the collector of the input transistor and through the first frequency-setting resistor to the first power supply bus, and is also connected to the input of the additional current mirror. The common emitter output of the additional current mirror is connected to the second power supply bus through the first additional current-stabilising two-terminal element. |
 Selective amplifier / 2507675Selective amplifier has an input voltage source, an additional power supply, a voltage-to-current converter, output and additional transistors, two frequency setting resistors, two current-stabilising two-terminal elements, two balancing capacitors. The output transistor has a collector which is connected through a first frequency setting resistor to a first power supply bus. The output of the voltage-to-current converter is connected to the collector of the output transistor and through series-connected first and second balancing capacitors through alternating current to the common power supply bus. The common node of the first and second balancing capacitors is connected through the second frequency setting resistor to the output of the device and is connected to the emitter of the output transistor. The emitter of the output transistor is connected through the first current-stabilising two-terminal element to the second power supply bus. The base of the output transistor is connected to the emitter of the additional transistor and through the second current-stabilising two-terminal element to the first power supply bus. |
 Selective amplifier with paraphase output / 2504073In the selective amplifier, the emitter-base junctions of the first (3) and second (5) output transistors are connected in parallel to corresponding additional first (17) and second (18) forward-biased p-n junctions, wherein the first (7) output of the device is connected to the base of the second (4) input transistor through a second (13) capacitor, the base of the second (4) input transistor is connected to the common bus of power sources (19) through a first (20) additional resistor, and the base of the first (3) output transistor is connected to the base of the second (5) output transistor. |
 Non-inverting current amplifier-based selective amplifier / 2488955Non-inverting current amplifier-based selective amplifier has an input voltage source (1), a voltage-to-current converter (2), an output transistor (3), an auxiliary voltage source (4), a first (7) and second (8) balancing capacitor, a second (9) frequency-setting resistor. |
 Differential amplifying device / 2487468Differential amplifier amplifies the difference between a signal fed to the non-inverting lead through a capacitor and a signal fed to the inverting lead. A switch switches input/non-input of a signal to the non-inverting lead through a capacitor. A resistor is connected between the non-inverting lead and the inverting lead. A bias voltage corrector corrects bias voltage of the differential amplifier based on the output signal of the differential amplifier during the correction period, wherein the switch is controlled such that a signal is not fed to the non-inverting lead through a capacitor. |
 Differential amplifier / 2248085Proposed differential amplifier has first and second parallel-balanced stages 1, 2 whose inputs are connected in parallel with transistors 1.1, 1.2 of first stage 1 whose polarity of conductivity is other than that of transistors 2.1, 2.2 of second stage 2; emitters of transistors 1.1, 1.2 are coupled with base of first additional transistor 5 whose emitter is connected through first auxiliary resistor 6 to integrated emitters of transistors 2.1, 2.2; integrated emitters of transistors 2.1, 2.2 are connected to base of second additional transistor 7 whose emitter is connected through auxiliary resistor 8 to integrated emitters of transistors 1.1, 1.2. |
 Operational amplifier / 2255416Proposed operational amplifier designed for amplifying broadband signals, including pulsed ones, in analog interface structures of various functional applications has input stage 1 made in the form of differential amplifiers whose output current is unlimited at input voltage fluctuations up to several volts; p-n-p transistors 8, 9; and n-p-n transistors 10, 11. Emitters of transistors 8 through 11 are connected to respective antiphase current outputs of stage 1; collectors of transistors 9, 11 are integrated and coupled with correcting capacitor 16 and with output buffer amplifier 17. Current followers 19, 18 are introduced between collectors of transistors 8, 9 and collectors of transistors 10, 11. Use of micron technologies with layout standards of 1.5 to 2 μm provides for speed growth at level of 4000 - 6000 V/μs. |
 Differential amplifier / 2255417Proposed differential amplifier is designed for operation in miscellaneous analog integrated circuits (for instance, in high-speed operational amplifiers, analog signal multipliers, and the like), within a wide range of 50 to 60 mV up to units of Volts in nonlinear modes limited by final speed of differential amplifier. Speed of the latter rises due to dynamic growth of recharge currents through correcting capacitor at maximal rate of output voltage rise comparable with its speed in linear modes. Differential amplifier has input transistors 1, 3, reference current supplies 2, 4, auxiliary resistor 5 inserted between emitters of transistors 1, 3, and load circuit connected to collectors of transistors 1, 3. Newly introduced are transistors 8, 9 of different structure whose emitters are connected through additional resistors 10, 11 to emitters of transistors 3 and 1, respectively. Bases of transistors 8, 9 are connected to those of transistors 3, 1, respectively. |
 Differential amplifier / 2257002Proposed differential amplifier that can be used in miscellaneous microelectronic devices for amplifying and converting analog signals has input parallel-balance stage 1 incorporating first and second inputs 2, 3, as well as first and second antiphase current outputs 4, 5 and first output transistor 6 whose emitter is connected to second current output 5 of input parallel-balance stage 1, base of first output transistor 6 being coupled at ac end with first input 2 of input parallel-balance stage 1. |
 Broadband amplifier / 2277752Proposed broadband amplifier has differential stage built around transistors 3, 4 with main input 1 that functions as amplifier input and auxiliary input 2; emitters of these transistors are interconnected and collectors are coupled with load-circuit resistors 5, 6; it also has non-inverting current amplifier built around output transistor 7; differential-stage transistors 3, 4 have different polarities of conductivity and non-inverting current amplifier is provided in addition with input transistor 8 whose collector and base are integrated and connected to current supply 9 and to differential-stage auxiliary input 2, and its emitter is coupled with that of output transistor 7 having reverse polarity of conductivity whose collector is connected to differential-stage main input 1. |
 Differential bridge amplifier / 2277753Proposed amplifier (Fig. 3) that functions to amplify broadband and pulse signals in structure of various interfaces has input transistors 1 - 4 whose emitters are coupled with bases of respective output transistors 15 - 18, emitters of the latter being connected to those of respective input transistors 1 - 4 through additional resistors 24 - 26; inserted between emitters of output transistors 15 - 18 is resistor-diode matching sub-circuit 19. |
 Method for raising speed of operational amplifiers having directly coupled stages / 2277754Proposed method designed for application in broadband and pulse signal amplifiers of miscellaneous analog interface structures to enhance their speed by 5 to 10 times using micron technology with layout standards equal to or higher than 1.5 - 2 μm includes generation of additional charge-discharge current for correcting capacitor 3 (Fig. 1) proportional to difference 8 between current value of voltage across correcting capacitor and instant output voltage of auxiliary differential stage 6 identical to limited-output-current nonlinear input differential stage 1 connected to its inputs. |
 Differential amplifier with increased depletion of cophased signal / 2278466Differential amplifier contains input differential cascade on first and second input transistors, emitters of which are connected to output of first current mirror, first and second transistors of input current compensation channel, bases of which are connected to bases of first and second input transistors, while emitters are connected to outputs of static mode stabilization circuit. Collectors of first and second transistors of input current compensation channel are connected to input of first current mirror. |
 Operational amplifier / 2280318Proposed operational amplifier designed for amplifying broadband and pulse signals in miscellaneous analog interface structures and characterized in maximum output voltage growth to 10 000 - 160 000 V/μs using micron technologies has input differential stage 1 built around transistors 2, 3 with first reference current supply 4; input differential stage 5 built around transistors 6, 7 with second reference current supply 8, main inputs 9, 10 of differential stage 1 being connected to inputs 11, 12 of differential stage 5; intermediate push-pull stage built around intermediate amplifiers 13, 15 whose inverting inputs are connected to collectors of transistors 2, 6, respectively, and their outputs 17, 29 are coupled through ac circuit with input 18 of output stage 19 and also with correcting capacitor 21. Output 22 of ac circuit of output stage 19 is coupled through first and second resistors 25 and 26, respectively, with emitters of transistors 2, 3 and with those of transistors 6, 7. |
 Differential amplifier with nonlinear parallel channel / 2282303Differential amplifier (dwg.2) contains input differential cascade 1 on input transistors 2,3, emitters of which are connected to supporting current source 4 and through voltage repeater 6 - to bases of output transistors 11,12, emitters of which are connected to collectors of input transistors 2,3, bases of which are connected to bases of appropriate auxiliary transistors 9,10, emitters of which through provided additional transistors 18,19 are connected to current outputs 14,15 of output transistors 11,12, bases of transistors 18,19 are connected to collectors of transistors 2,3, while collectors of transistors 18,19 and 9,10 perform functions of appropriate current outputs (20,21 and 22,23) of parallel channel, providing amplification of large amplitudes of input signal. |
FIELD: radio engineering, communication.
SUBSTANCE: hybrid differential amplifier comprises a first (1) input transistor, the base of which is connected to the non-inverting input (2) of the device, the collector is connected to a first (3) power supply bus, and the emitter is connected to emitter of a second (4) input transistor, wherein the base of the second (4) input transistor is connected to the inverting input (5) of the device, and the collector is connected to the output (6) of the device and is connected to a second (7) power supply bus through a load circuit (8). The first (1) input transistor used is a first (1) junction field-effect transistor, the gate of which corresponds to the base, the source to the emitter and the drain to the collector of a bipolar transistor, and the load circuit (8) comprises a second (9) junction field-effect transistor, the gate of which is connected to the second (7) power supply bus, the drain is connected to the collector of the second (4) input transistor, and the source is connected to second (7) power supply bus through an additional p-n junction (10), identical to the emitter-base junction of the second (4) input transistor.
EFFECT: reducing the systematic component of the zero bias voltage and temperature and radiation drift thereof.
2 cl, 11 dwg
The invention relates to the field of radio engineering and communication and can be used as a device strengthening of analog signals in the structure of analog chips of different functional purposes (for example, in photoreception devices, solving amplifiers with low input conductivity etc).
In modern electronic equipment are used differential amplifiers (DU) with significant different parameters.
A special place is occupied by the complement cascade differential amplifiers [1-11]. These do have a very simple structure and are characterized by the lowest power consumption.
The present invention relates to this class of devices.
The closest to the nature of the proposed technical solution is a classical scheme of complementary differential cascade figure 1 presented in U.S. patent №6.781.459 fig. 4, which is also present in a large number of other patents and books, for example, [1-11]. It contains the first 1 input transistor, the base of which is connected to not inverting input 2 devices, the collector is connected with the first 3 bus power supply, and the emitter is connected to the emitter of the second 4 input transistor, and the base of the second 4 input transistor is connected to the inverting input 5 device, and its manifold connected to the output of 6 device and is connected with the second 7 bus power supply via load circuit 8.
A significant disadvantage Doo figure 1 is that it has increased the importance of the systematic component of the voltage offset (U cm =1,4% to 1,5 B), due to the asymmetry of its architecture.
The main objective of the proposed invention consists in reducing the absolute value U SEE , as well as its temperature and radiation drift.
The task is achieved that complementary differential amplifier figure 1, containing the first 1 input transistor, the base of which is connected to not inverting input 2 devices, the collector is connected with the first 3 bus power supply and the emitter connected to the emitter of the second 4 input transistor, and the base of the second 4 input transistor is connected to the inverting input 5 device, and its manifold connected to the output of 6 device and is connected with the second 7 bus power supply via load circuit 8, there are new elements and communications, as the first 1 input transistor is used first 1 field-effect transistor with managing the p-n junction, the gate of which corresponds to the base, the source of the emitter, and the river - reservoir bipolar transistor, and the load circuit 8 9 contains the second field-effect transistor with the Manager of p-n the transition, the gate of which is connected with the second 7 bus power supply, runoff associated with header second 4 input transistor, and the source is associated with the second 7 bus power supply through additional p-n junction 10, identical emitter-base transition of the second 4 input transistor.
The amplifier circuit prototype is shown on the drawing figure 1. On the drawing figure 2 presents the scheme of the claimed device in accordance with paragraph 1 of the claims.
Scheme DU corresponding to claim 2, shown on the drawing figure 3.
On the drawing figure 4 shows a diagram of the operational amplifier on the basis of the proposed control, which included additional buffer amplifier transistor 13 and the source of bias potentials 14, and entered 100% negative feedback from the exit 15 on the entrance 5.
Scheme of du in the environment of the PSpice models transistors analog base matrix crystal corresponding to the drawing figure 4, is shown in the drawing figure 5, and the dependence of the gain on the voltage of the frequency of this (broken) shelter is presented on the drawing 6. Offset voltage of zero OS 5 corresponds U cm =-8,2 mV.
On the drawing Fig.7 shows the dependence of the gain on the voltage of the frequency OS 5 at 100% negative feedback.
The scheme Fig corresponds to the drawing figure 5, however, the output buffer amplifier is designed in the form of a composite transistor Q7, Q8, and voltage offset this OS corresponds U cm =-3,1 mV.
On the drawing figure 9 presents the frequency dependence of gain voltage OS Fig without feedback.
On the drawing figure 10 shows the dependence of the gain on the voltage of the frequency OS peg at 100% negative feedback.
On the drawing 11 shows a diagram of OU Fig, which by reducing resistor R1 guaranteed low offset voltage of zero (U cm =-22,2 MACs).
Hybrid differential amplifier figure 2 contains the first 1 input transistor, the base of which is connected to not inverting input 2 devices, the collector is connected with the first 3 bus power supply, and the emitter connected to the emitter of the second 4 input transistor, and the base of the second 4 input transistor is connected to the inverting input 5 device, and its manifold connected to the output of 6 device and is connected with the second 7 bus power supply via load circuit 8. As the first 1 input transistor is used first 1 field-effect transistor with managing the p-n junction, the gate of which corresponds to the base, the source of the emitter, and the river - reservoir bipolar transistor, and the load circuit 8 9 contains the second field-effect transistor with managing the p-n junction, the gate of which is connected with the second 7 bus power supply, runoff associated with header second 4 input transistor, and the source is associated with the second 7 bus power supply through additional p-n junction 10, identical emitter-base transition of the second 4 input transistor.
On the drawing figure 3, in accordance with claim 2, in the chain of source 1 first and second 9 field transistors p-transition included respectively the first 11 and the second 12 additional resistors.
On the drawing figure 4 the scheme includes additional buffer amplifier transistor 13 and the source of the bias voltage 14, the output of which is connected to the output device 15.
Consider the factors that determine systematic component voltage offset U see in the diagram of figure 2, i.e. depending on the circuitry of the shelter.
Current source and drain of the FET 9 (I =I =I 0 ) depends on the steepness of its statesattorney characteristics when U I =U AB ≈0,7V. When identical to the p-n transitions of the second 4 input transistor and extra p-n junction 10 and identical field-effect transistors 1 and 9 emitter current of the transistor 4 and current source of the transistor 1 will be equal to the value of I is 0 . Therefore, the voltage offset in question do according to his definition [12]
U with m = U E. b .4 - U C and .1 ≈ 0, (1) as U A B = U E. b .10 = U C and .9 , U A B = U E. b .10 = U E. b .4 = U ARomanova
BRomanova
, (2) U zi .1 = U C and .9 .Thus, in this scheme provides low offset voltage of zero.
The differential gain voltage claimed Doo 2:
K y = u in s x .6 u in x .1 - u in x .2 = u in s x .6 u in x .1.2 ≈ R n . E. to in r E. 4 + S 1 - 1 where r E. 4 ≈ ' t I 0- resistance-emitter junction transistor 4;
S 1 - slope statesattorney features field-effect transistor 1;
Phi t =26 mV - temperature potential;
R naqu - equivalent load resistance control.
And R n . E. to in ≈ ( ' t I 0 + 1 S 9 ) / h 12.9 3 , (4)where S 9 - slope statesattorney features FET 9;
h 12.9 3 = 10 - 2 ASP 10 - 4- coefficient of internal feedback field-effect transistor 9, depending on its design and manufacturing technology.
When the temperature changes (and radiation) changes the drain current of the transistor 9. However, exactly the same (in connection with the symmetry of the emitter circuit) a change in the current source of the transistor 1 and collector transistor current 4. In the U see schemes varies slightly.
Thus, the declared device decreases the systematic component of the voltage offset U see .
Thus, the proposed device has significant advantages in comparison with the prototype largest static errors strengthening of DC signals and can be used as the IP modules modern system-on-chip, sold, for example, technology analog base matrix crystals ABMC.
The bibliographic list
1. US patent # 4.415.868 fig. 3
2. The patent of the FRG №2928841 fig. 3
3. The Japan patent JP 54-34589, CL 98(5) a014 select the active portion
4. The Japan patent JP 154-10221, CL H03F 3/45
5. The Japan patent JP 54-102949, CL 98(5) A21
6. US patent # 4.366.442 fig. 2
7. US patent # 6.426.678
8. Patent application US 2007/0152753 fig. 5
9. US patent # 6.531.920, fig.4
10. US patent # 4.262.261
11. Ejkov Y.A Reference circuitry amplifiers. - 2-e Izd., Rev.): IE the Radiosoftware, 2002. - 272 S. - RIS (p.235).
12. Operational amplifiers with direct connection cascades / V.I. Anisimov, Kapitonov M.V., Prokopenko N., Sokolov, Y.M. - L.: "Energy", 1979. - 148 S.