Analogue-to-digital converter

FIELD: information technology.

SUBSTANCE: analogue-to-digital converter comprises an n-bit priority encoder, a flip-flop Tg₀, an AND circuit I₀, an n-bit register, n flip-flops Tg₁, …, Tg_n with AND circuits I₁, …, I_n, an n-bit number-to-voltage converter, a comparator circuit, a trigger bus, n analogue voltage comparators K₁, …, K_n, n blocks of reference voltages U_et1, …, U_etn, an n-bit demultiplexer and a clock-pulse generator.

EFFECT: improved performance of the analogue-to-digital converter and specifically operational reliability and reduced weight and size.

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The invention relates to computer technology and can be used as input devices for digital computer systems for registration of fast electrical processes.

Known n-bit analog-to-digital Converter (ADC)containing the control unit (CU), the comparison circuit (CC) and n-bit code Converter-voltage (CRC, DAC). The SU consists of a n-bit register (RG) and n-triggers with schemes I. comparison Circuit presents an analog voltage comparator, the input of which is fed the input voltage and the voltage output from the CRC. CS, SS, and n-bit CRC combined into n-bit conversion unit (PSU). The outputs of the PSU is formed of n-informational outputs, which outputs n-triggers. [1]

The disadvantage of analog is low performance. For n-bit ADC performance is n clock cycles.

The closest in technical essence is analog-to-digital Converter bit n that contains the trigger circuit And the n-bit multiplexer, n from 1 to n-bit conversion blocks, each of which includes n-bit register (RG), n triggers Tg₁,..., Tg_nschemes And And₁And_nn-bit code Converter-a voltage comparison circuit, and:

to the counting input C of the n-bit register connected to yhod schemes And, to the input of which is connected to the bus clock and trigger output to the input S of which is connected to the bus run, and to the input R output of the low order n-bit register;

outputs n-bit register n,...,1 are connected to the inputs of the circuits And₁..., And_nto the input S of trigger Tg₁Tg_n-1connected to the outputs 1,..., n-1 n-bit register, to another input of the schemes And And₁... , And_nconnected to the output of the comparison circuit, the inputs of which are connected to the measurement channel and output n-bit code Converter-voltage, output circuits And₁... , And_nconnected to the inputs R triggers Tg₁,..., Tg_n;

the bus is running is connected to the input of the invoice V n-bit register to the input S of trigger Tg_nand also to the input R triggers Tg₁,..., Tg_n-1; output triggers Tg₁,..., Tg_n-1respectively connected to the inputs a₁,...,a_nn-bit Converter code voltage.

The prototype also includes an n-bit multiplexer (MP), n-bit priority encoder (PSH, CD). The bits of the digital code in the generated output circuits multiplexers, starting from the n-th multiplexer.

The disadvantage of the prototype is a low reliability and a significant weight and dimensions through the use of a large number of analog and digital logic devices.

This objective is achieved in that in the known bit ADC n, containing n-bit priority encoder, trigger Tg₀the scheme And₀n-bit register, n triggers Tg₁,..., Tg_nschemes And And₁... , And_nn-bit code Converter-a voltage comparison circuit, in which: to the counting input of the n-bit register connected to the output of the circuit And₀to the input of which is connected to the output of trigger Tg₀to the input S of which is connected to the bus start-up; outputs n-bit register F₀,..., F_n-1connected to the inputs of circuits And₁... , And_nto the input S of trigger Tg₁,..., Tg_n-1respectively connected to the outputs of the F_n-1,..., F₁n-bit register to the input of the schemes And And₁... , And_nconnected to the output of the comparison circuit, the inputs of which are connected to the measurement channel and output n-bit code Converter-voltage, output circuits And₁... , And_nrespectively connected to the inputs R triggers Tg₁,...,Tg_n; bus run is connected to the input of the invoice V n-bit register to the input S of trigger Tg_nand also to the input R triggers Tg₁,·, Tg_n-1the output of trigger Tg₁,..., Tg_{n respectively connected to the inputs a1,..., ann-bit Converter code-voltage. Further comprises n analog comparator voltage To1,..., Knn blocks of the reference voltages Uat,..., UETPand n-bit demultiplexer (DMS) and the generator of clock pulses, and a generator of clock pulses connected to the input schema And0; to the input analog voltage Comparators connected to the measurement channel, to another input of the analog comparator voltage To1,..., Knrespectively connected to the outputs of the blocks of the reference voltages Uat,...,UETPto the input of which is connected to bus supply voltage UPetethe outputs of the analog Comparators voltage To1,..., Knrespectively connected to the inputs x0,..., xn-1n-bit priority encoder; the outputs of the priority encoder y0,..., yk-1connected to the address inputs of the n-bit demultiplexer And0,..., Ak-1the bus is running is connected to the input D of the n-bit demultiplexer and to the input R of the n-bit register; outputs n-bit demultiplexer Fn-1,..., F0respectively connected to the inputs of the D0,..., Dn-1n-bit register, and also to the inputs S of trigger Tgn,..., Tg1, the low-order n-bit register under the offline to the input of the R trigger Tg 0; bits of the digital code in the generated output circuits triggers Tgn,..., Tg1starting from the 1st trigger.}

The use of new nodes and new functional connections reduces the number of analog and digital logic devices, thereby increasing the reliability of analog-to-digital Converter and reduced weight and dimensions.

Figure 1 presents a functional diagram of the n-bit ADC.

Figure 2 shows a functional diagram of the four-digit ADC implementation.

n-bit ADC contains: n-bit priority encoder 1; clock 2; n-bit demultiplexer 3; a comparison circuit 4; an n-bit register 5; n-bit code Converter-voltage 6; n blocks of the reference voltages U_at,..., U_ETP; n analog comparator voltage To₁,..., K_n; trigger Tg₀; scheme And₀; n triggers Tg₁,..., Tg_nschemes And And₁... , And_n.

Where: analog comparator voltage To₁,..., K_nconnected to the measuring channel U_Ito another input of the analog comparator voltage To₁,..., K_nrespectively connected to the outputs of the blocks of the reference voltages U_at,..., U_ETPto the input of which is connected to bus supply voltage U_Petein the passages analog Comparators voltage To ₁,..., K_nrespectively connected to the inputs x₀,..., x_n-1n-bit priority encoder 1; the outputs of the priority encoder 1 y₀,..., y_k-1connected to the address inputs a₀,..., A_k-1n-bit demultiplexer 3; outputs n-bit demultiplexer 3 F_n-1,...,F₀respectively connected to the inputs of the D₀,..., D_n-1n-bit register 5, and also to the inputs S of trigger Tg_n,..., Tg₁the low-order n-bit of the register 5 is connected to the input R of trigger Tg₀; to the counting input C of the n-bit register 5 is connected to the circuit output And₀to the input of which is connected to the clock 2 and the output of trigger Tg₀to the input S, which is connected to the bus start-up; outputs n-bit register 5 F₀,..., F_n-1connected to the inputs of circuits And₁... , And_nto the input S of trigger Tg₁,...,Tg_n-1respectively connected to the outputs of the F_n-1,...,F₁n-bit register 5, to the other input circuits And₁... , And_nconnected to the output of the comparison circuit 4, the inputs of which are connected to the measurement channel and output n-bit code Converter-voltage 6, the outputs of circuits And₁... , And_nrespectively connected to the inputs R triggers Tg₁,..., Tg_n; bus run is connected to the input D of the n-bit demultiplexer 3, to the input R and V n-RA the row register 5, to the input S of the trigger Tgp, and also to the input R triggers Tg₁,..., Tr_n-1; output triggers Tg₁,..., Tg_nrespectively connected to the inputs a₁,..., a_nn-bit Converter code-voltage 6.

The values of the reference voltages with blocks U_at,..., U_ETPcorrespond to the voltage equal to one digit of a digital code according to the sequence number of the block of the reference voltage.

Analog-to-digital Converter operates as follows.

In the first cycle of the ADC on the arrival of the pulse on the bus start reset values on n-bit priority encoder 1, the n-bit register 5 and triggers Tg₁,..., Tg_nand the trigger Tg₀translated in one state, and supplies one of the inputs of the circuit And 2 logical unit, analog Comparators voltage To₁,..., K_nproduce pulses on informational inputs x₀,..., x_n-1n-bit priority encoder 1, which reads the values of the information inputs x₀,..., x_n-1and generates the code received at the address inputs of the demultiplexer 3, which switches the input D to one of the outputs of F₀,..., F_n-1when this signal passes through the n-bit register 5 and sets in one state trigger, for example Tg_kwhich takes a single EIT is giving to the input of a _kPKN 6, the comparison circuit 4 compares the voltage of the measuring channel U_Iand the reference voltage output PKN 6, if the voltage from the measuring channel U_Iless voltage output PKN 6, the comparison circuit 4 generates a pulse which, after passing scheme And_ksets the trigger Tg_kin state 0. n-bit register produces a shift unit with output F_kon exit F_k-1when this trigger Tg_k-1translated in one state, if the voltage measurement channel UBX more voltage output PKN 6, the trigger Tg_k-1saves the state 1. The cycles of operation analog-to-digital Converter repeated until then, until the low order digit of the n-bit register 5 will not be a unit, and the trigger Tg₀translated in the zero state, thereby closing the circuit And₀. The bits of the digital code generated output circuits triggers starting from the 1st trigger.

As an example the following is an analog-to-digital conversion of the four-digit analog-to-digital Converter 2 is a voltage measuring channel U_Icorresponding digital code 0011.

In the first step of trigger Tg₀translated in one state, and supplies one of the inputs of the circuit And 2 logical unit, while analog comparat the ry voltage To ₁,..., K₄produce pulses on the information inputs of the priority encoder 1, the priority encoder 1 reads the value of information inputs x₀- 1, x₁- 1, x₂- 0, x₃- 0 and generates code y₀- 1, y₁- 0, received at address inputs and₀and a₁the demultiplexer 3. The demultiplexer 3 commutes input D output F₁when this trigger Tg₂translated in one state, input and₂PKN 6 enters the unit, respectively, it outputs a reference voltage corresponding to the digital code 0010. The output of the comparison circuit 4, the pulse is not generated, the trigger Tg₂retains its value, the four-digit register 5 produces a shift of the unit at the output of the F₃the trigger Tg₁translated in one state, and the trigger Tg₀in state 0, thereby closes the circuit And₀.

Using the described analog-to-digital Converter allows to reduce the required number of analog and digital logic devices relative to the prototype with preservation of specified performance, namely for n-bit ADC:

n n-bit multiplexers;

n-1 from 1 to n-1-bit conversion blocks, for example, k-bit conversion unit includes: a comparison circuit; a k-bit Converter code-atragene; k-bit register; k triggers; k schemes I.

A useful effect of the use of the device is increased reliability and structural simplification of the ADC and the reduced mass and size parameters.

As a positive economic effect, you can select the lower cost analog-to-digital Converter in comparison with the prototype.

Positive effects from the use of analog-to-digital Converter are achieved through the use of original technical solutions that reduce the number of analog and digital logic devices.

The industrial feasibility of the proposed ADC is substantiated by the fact that in the example of the technical implementation are well-known for its intended functional purpose nodes and links.

Sources of information

1. Gittis AI, Piskulov E.A. Analog-to-digital converters: Textbook. manual for schools. - M.: Energoizdat, 1981. - 360 S.(str-236) is similar.

2. Patent for useful model Analog-to-digital Converter, No. 119190, publ. 10.08.2012, the authors Krivonogov A.N., Konstantinov E.N., the patentee of the FSUE "18 the Central research Institute" of the Ministry of defense - the prototype.

Analog-to-digital Converter comprising n-bit priority encoder, trigger Tg₀the scheme And₀n-bit register, n triggers Tg₁, ..., Tg_nwhat about the schemes And And ₁... , And_nn-bit code Converter-a voltage comparison circuit, in which:
to the counting input C of the n-bit register connected to the output of the circuit And₀to the input of which is connected to the output of trigger Tg_0,to the input S of which is connected to the bus run;
outputs n-bit register F₀, ..., F_n-1connected to the inputs of circuits And₁... , And_nto the input S of trigger Tg_n-1, ..., Tg₁respectively connected to the outputs of the F₁, ..., F_n-1n-bit register, to another input of the schemes And And₁... , And_nconnected to the output of the comparison circuit, the inputs of which are connected to the measurement channel and output n-bit code Converter-voltage, output circuits And₁... , And_nrespectively connected to the inputs R triggers Tg₁, ..., Tg_n;
the bus is running is connected to the input of the invoice V n-bit register to the input S of trigger Tg_nand also to the input R triggers Tg₁, ..., Tg_n-1the output of trigger Tg₁, ..., Tg_nrespectively connected to the inputs a₁, ..., a_nn-bit Converter code-power;
characterized in that it further comprises n analog voltage Comparators K₁, ..., K_nn blocks of the reference voltages U_at, ..., U_ETPand n-bit demultiplexer and clock, and:br/> the generator of clock pulses connected to the input schema And₀;
to the input analog voltage Comparators connected to the measurement channel, to another input of the analog comparator voltage To₁, ..., K_nrespectively connected to the outputs of the blocks of the reference voltages U_at, ..., U_ETP,to the input of which is connected to bus supply voltage U_Petethe outputs of the analog Comparators voltage To₁, ..., K_nrespectively connected to the inputs x₀, ..., x_n-1n-bit priority encoder;
the outputs of the priority encoder y₀, ..., y_k-1connected to the address inputs of the n-bit demultiplexer A₀, ..., A_k-1;
the bus is running is connected to the input D of the n-bit demultiplexer and to the input R of the n-bit register;
outputs n-bit demultiplexer F_n-1, ..., F₀respectively connected to the inputs of the D₀, ..., D_n-1n-bit register, and also to the inputs S of trigger Tg_n, ..., Tg₁;
the low-order n-bit register connected to the input R of trigger Tg₀;
the bits of the digital code in the generated output circuits triggers Tg_n, ..., Tg₁starting from the 1st trigger.