Ultra-high-speed parallel analogue-to-digital converter with differential input |
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IPC classes for russian patent Ultra-high-speed parallel analogue-to-digital converter with differential input (RU 2518997):
 Digital angle converter / 2517055
Method is carried out by using simplest functional digital to analogue converters in the main channel with the base function of the type f(x)=(1+k)x/(l+kx), and in the correction channel - a shaper of a certain voltage used as an additional component for the signal of the circuit of mismatch in current values of the angle α and the binary code N.
 Method of expanding signal spectrum estimation bandwidth / 2516763
Method employs original signal processing concurrently on multiple analogue-to-digital converters (ADC) with different sampling frequencies; calculating the amplitude spectrum on each digitised sequence; further scanning the obtained spectra on a single frequency axis in the Nyquist zone in an order which is inverse to the arrangement thereof during sampling; selecting signals in the spectral range by comparing with a given threshold of amplitude spectra from each ADC; selecting spectral lines from all ADC matching on frequency position; a decision on the existence of a narrow-band signal at said frequency is made by finding lines which match on the position on the frequency axis from all ADC.
 Digital angle data transmitter with sign digit / 2515965
Digital angle data transmitter contains an induction pickoff of a synchro resolver type, analogue-to-digital converter of the synchro resolver signals to angle digit (ADC) of a starter type with auxiliary cue signal of the rotation direction and F-counter (LSDV change pulse), a microprocessor controller, a binary bidirectional counter with a number of digits per one most significant bit more than for the ADC, a digital comparator with a number of digits equal to the ADC number of digits, a null code setter with a number of digits equal to a number of digits of the digital comparator.
 Digital converter and energy conversion device / 2513913
Group of inventions is related to analogue-to-digital converters and can be used in energy conversion devices for power electronics. The device contains a number of data signals storage units which can select data signals with delay equal to the preset time interval, moreover these signals specify instant value change, and store these selected values with simultaneous selection of each of these signals; a deleting unit capable to delete the maximum and minimum value from values stored at the number of data signals storage units; an averaging unit capable to take an average of values which are not deleted by the deleting unit; and a converter capable of analogue-to-digital conversion of the value outputted from the averaging unit and displaying this converted value as digital information.
 High-speed analogue-to-digital converter with differential input / 2513716
Unlike the existing high-speed analogue-to-digital converter with a differential input, in the present invention a first input voltage source is connected to the input of a first additional buffer amplifier, the output of which is connected to first inputs of each voltage comparator through corresponding balancing capacitors of a first group, and the second input antiphase voltage source is connected to the input of a second additional buffer amplifier, the output of which is connected to second inputs of each voltage comparator through corresponding balancing capacitors of a second group.
 Redundant source of current / 2512890
Invention contains in ACS structure resonance probes (thermal resistance probes, potentiometric pickups for actuator feedback), which require flow of permanent stable current in order to collect data from them; as a rule probes are connected in series and they require maintenance of stable current at load change and degradation of semiconductor parameters with time due to temperature change and accumulation of dose changes, and in result of such changes operation of transistors is violated and value of output current is changed. To this end the claimed device contains three identical converters of input power to output stable current; output currents of converters through cut-off unit are delivered to balancing unit, from output of the balancing unit through ballast reference resistor they come to load; outputs of the converters are also connected to control and monitoring unit by control outputs to cut-off unit and by control outputs to auxiliary power supply source; output signal comes to voltage-to-frequency converter, which control output through galvanic decoupling element to chopper transistor control module.
 Digital-to-analogue converter / 2510979
Digital-to-analogue converter, having multiple current sources and the same number of differential amplifiers based on transistors, wherein the currents of the current sources are in a ternary relationship with each other, in order to solve the set task, includes an adder, positive and negative busbars, wherein each differential amplifier forms a three-way switch, the current sources can be connected by the three-way switches to the positive or negative busbar, or can be disconnected, wherein the positive and negative busbars are connected to the adder which generates the bipolar output signal of the digital-to-analogue converter from the difference in currents of the busbars. One output of each differential amplifier is connected to the positive busbar and the second output of each differential amplifier is connected to the negative busbar.
 Pseudorandom code scale / 2510572
Pseudorandom code scale includes an information track made in form of gradations of a pseudorandom binary sequence with maximum period length M=2n-1, n information reading elements, arranged along the information track with angular spacing which is a multiple of the value of the quantum of the scale δ=360°/M, with the possibility of obtaining therefrom M different n-bit code combinations, k correcting reading elements, arranged along the information track with possibility of obtaining therefrom, along with n information reading elements, M different (n+k)-bit code combinations which represent a Hamming code with detection and correction of a single error, a control reading element arranged along the information track with possibility of obtaining therefrom, along with (n+k) reading elements, M different (n+k+1)-bit code combinations which represent a Hamming code with correction of a single error and detection of a double error, outputs of n information reading elements.
 Method and apparatus for detecting nonlinear distortions caused by analogue-to-digital converter / 2507681
Invention is based on change in the average value of a random process as a result of nonlinear conversion thereof. After passing through a device with a monotonous nonlinear characteristic, a random process with a zero average changes its spectral composition such that a constant component which depends on the degree of manifestation of nonlinearity arises therein. Thus, the technical result is achieved by measuring and analysing the average value of a digital code at the output of the investigated analogue-to-digital converter. The apparatus for detecting nonlinear distortions has a subtractor unit, a unit for measuring the magnitude of the average value of the digital code and a decision unit. In another version, the apparatus consists of a unit for measuring the average value of the digital code and a decision unit.
 Method to increase accuracy of measurement of analog signal, device for measurement of analog signal / 2506697
Invention relates to analog-to-digital measurement techniques to measure an analogue signal. In the proposed method measuring the analog signal is carried out using the ADC, and at the same time the error in the form of the said linear displacement of readings is reduced by control means to compensate for this by the linear displacement, and the error in the form of these oscillations is reduced with the help of readings averaging means by averaging readings during averaging time C, using the control means to compare the rate of change of the analog signal with a predetermined threshold value. Averaging of readings is performed dynamically by changing the control means using the averaging time from zero to a predetermined maximum value in the event of changes in the analog signal at a speed less than the preset threshold. In case of exceeding the specified speed preset threshold specified averaging of readings is stopped by control means.
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FIELD: radio engineering, communication. SUBSTANCE: disclosed is an ultra-high-speed parallel analogue-to-digital converter with a differential input, having N sections of identical architecture. Each of the sections includes a voltage comparator, the first input of which is connected to a first input voltage source through a first reference resistor, and the second input of the voltage comparator is connected to a second input anti-phase voltage source through a second reference resistor, wherein the first input of the voltage comparator is connected to a first reference current source and a first parasitic capacitor, the second input of the voltage comparator is connected to a second reference current source and a second parasitic capacitor. The first reference current source is connected in form of a first current mirror which is matched with a first power supply bus, and a first auxiliary reference current source connected to the input of the first current mirror, wherein the output of the first current mirror is the output of the first reference current source, and the second input anti-phase voltage source is connected to the input of the first current mirror through a first balancing capacitor. EFFECT: multifold expansion of the frequency range of processed analogue-to-digital converter signals by reducing the transmission error of input differential voltages from input voltage sources to voltage comparator inputs. 3 cl, 7 dwg
The present invention relates to the field of measurement and computer engineering, radio engineering, communications and can be used in the structure of different processing devices analog information, measuring instruments, systems, telecommunications, etc. In the modern technology have found an extensive use of parallel analog-to-digital converters (ADCS)that provide the highest conversion speed analog signals (uIdigital signals [1-27]. With increasing frequency of the input voltage uIin such microelectronic ADC substantial conversion error due to the influence of parasitic capacitors formed by the containers on a substrate of active and passive components [28-29]. A further increase in speed parallel ADC is one of the problems of modern information and measuring equipment, which will enable the practical implementation of new communication and telecommunication systems with higher quality characteristics. Closest to the technical nature of the claimed device is parallel ADC of Fig. 1 described in the patent US 7.394.420, fig.3, fig.4. Analysis of the limiting frequency range (fvmag), as well as attempts to increase the fvmagby optimizing the absolute values of the reference resistance through the stores, articles [28-29], including co-author of this application [29]. ADC prototype contains N identical architecture sections (figure 1). Each section contains a voltage comparator 1, the first 2 input connected with the first 3 source of input voltage through the first 4 reference resistor 5 and the second input of the voltage comparator 1 is connected to the second 6 source antiphase input voltage 7 through the second reference resistor, and the first 2 input of the voltage comparator 1 is connected with the first 8 reference current and the first 9 of the parasitic capacitor, the second 5, the input of the voltage comparator 1 is connected with the second 10 reference current 11 and the second parasitic capacitor. A significant disadvantage of the ADC prototype (figure 1), schema, one section of which is shown in Fig. 2, is that it limits the frequency range conversion analog input signals to digital (even when implemented on microwave transistors with fmax=200 GHz process SGB25H1, IHP, Germany [28, 29]) is limited due to decrease at high frequencies the gain of the signal with the ADC inputs to the inputs of voltage Comparators. The main objective of the present invention is to increase several times the frequency range of the processed signals of the ADC by reducing the errors of the transmission input diff the account of the differential voltages from input voltages of 3 and 6 to the inputs of the voltage Comparators 1. This object is achieved in that in a parallel analog-to-digital Converter with a differential input (figure 1), each of the N sections (figure 2) contains a voltage comparator 1, the first 2 input connected with the first 3 source of input voltage through the first 4 reference resistor 5 and the second input of the voltage comparator 1 is connected to the second 6 source antiphase input voltage 7 through the second reference resistor, and the first 2 input of the voltage comparator 1 is connected with the first 8 reference current and the first 9 of the parasitic capacitor, the second 5, the input of the voltage comparator 1 is connected with the second 10 the reference current 11 and the second parasitic capacitor, there are new elements and connections of the first 8 reference current is performed in the first 12 current mirror that is consistent with the first 13 bus power source 14 and the first auxiliary reference current connected to the input of the first 12 of the current mirror, and the output of the first 12 of the current mirror is the output of the first 8 of the reference current and the second 6 the input phase voltage is connected to the input of the first 12 of the current mirror through the first 15 correction capacitor. Figure 1 shows a diagram of the ADC prototype, which contains N-parallel connected sections with the same architect is the established levels (figure 2), but different absolute values of the resistance of the reference resistor 4 (7) and current I8(I10sources of reference currents 8 (10). In Fig. 2 shows the equivalent circuit of one section of the ADC of Fig. 1, the corresponding ADC prototype. In Fig. 3 shows a diagram of one of the sections of the proposed ADC, the corresponding PP. 1, 2 claims. In Fig. 4 shows the equivalent circuit of the inventive ADC in Cadence environment models SiGe transistors (npn 200-n; the process SG25H1, IHP, Ccah = 4 mA. A high-performance 0.25 µm technology with npn-HBTs up to fT/fmax=180/220 GHz.), taking into account the parasitic capacity of the real current mirrors, capacitance to the substrate of the passive components and the input capacitance of the voltage Comparators 1 on the basis of real differential cascades. In Fig. 5 shows the logarithmic amplitude-frequency characteristic of the gain from input voltages of 3 and 6 to a differential comparator input # 2 (channels: 32, 48) of the ADC circuit of Fig. 4. In Fig. 6 shows the logarithmic amplitude-frequency characteristic of the gain from input voltages of 3 and 6 to a differential comparator input # 2 (channels: 32, 48) of the ADC circuit of Fig. 4. In this scheme: - takes into account the capacitance to the substrate of the reference resistors 4 and 7; consistently with each correction capacitor 15 and 18 Cthe included additional resistor R=50 Ohm; - parasitic output capacitance of the current mirrors 12 and 16 has a relatively small value Withn=70 FF; in the scheme used real Comparators voltage 1 (differential cascades) with the parasitic capacitances of their transistors. In Fig. 7 shows the logarithmic amplitude-frequency characteristic of the gain from sources of stress 3 and 6 to a differential comparator input # 2 (channels: 32, 48) of the ADC circuit of Fig. 4. In the circuit of Fig. 4: - takes into account the capacitance to the substrate of the reference resistors 4 and 7; - consistently with the capacity of each corrective capacitors 15 and 18 (Cto) included an additional resistor R=50 Ohm; - parasitic output capacitance of the current mirrors 12 and 16 has a high value Withn=300 FF; - used real Comparators voltage 1 (differential cascades) with the parasitic capacitances of its transistors. Ultrahigh-speed parallel analog-to-digital Converter with a differential input contains N identical architecture sections of Fig. 3. Each section includes a voltage comparator 1, the first 2 input connected with the first 3 source of input voltage through the first 4 reference resistor 5 and the second input of the voltage comparator 1 is connected to the second 6 source input about ilopango voltage through the second 7 reference resistor, the first 2 input of the voltage comparator 1 is connected with the first 8 reference current and the first 9 of the parasitic capacitor, the second 5, the input of the voltage comparator 1 is connected with the second 10 reference current 11 and the second parasitic capacitor. The first 8 reference current is performed in the first 12 current mirror that is consistent with the first 13 bus power source 14 and the first auxiliary reference current connected to the input of the first 12 of the current mirror, and the output of the first 12 of the current mirror is the output of the first 8 of the reference current and the second 6 the input phase voltage is connected to the input of the first 12 of the current mirror through the first 15 correction capacitor. The state of the outputs of the voltage Comparators is judged on the digital equivalent of the input signal. Figure 3, in accordance with claim 2, the second 10, the reference current is made in the form of 16 second current mirror that is consistent with the first 13 bus power source, and the second 17 auxiliary source of reference voltage connected to the input 16 second current mirror and the second output 16 of the current mirrors is an output of the second 10 of the reference current and the first 3 source of input voltage connected to the input 16 second current mirror 18 through the second corrective condensate is R. In figure 4, in accordance with section 3 of the claims, consistently with each correction capacitor 15 and 18 includes additional resistors. Consider the analog sections ADC figure 1, figure 2 and figure 3, including the reference resistors 4, 7, sources of reference voltage 8, 10, the voltage comparator 1. The ADC prototype figure 1 performance of the analog section figure 2 (limiting the frequency range fvmag) is determined by the parasitic capacitors 9 and 11. Almost upper cutoff frequency (- 1 dB) ADC prototype during its implementation in SiGe technology does not exceed 2-7 GHz (figure 5, 6), while the performance of the comparator 1, implemented on microwave SiGe transistors [28, 29] with fT=200 GHz, allows you to work in a wider frequency range (20÷50 GHz). In the inventive device of Fig. 3 due to the introduction of new connections limit the operating frequency range of the analog section of the ADC is expanding 2-6 times (figure 5-7). This allows analog-to-digital conversion of the higher frequency signals. Introduction in series with corrective capacitors 18 and 15 adjustment resistors (figure 4) allows you to optimize the flatness of the amplitude-frequency characteristics of the analog section of the ADC, which creates conditions for further expansion of the frequency range (Fig.6, Fig.7). the thus, the the inventive device is characterized by significant advantages in comparison with the prototype over the frequency range of the processed signals. BIBLIOGRAPHIC LIST 1. Patent US 6.437.724 fig.4 2. Patent US 6.882.294 3. Patent US 4.229.729 fig.1 4. Patent US 4.058.806 fig.2a 5. Patent US 4.831.379 fig.8 6. Patent US 5.598.161 fig.9 7. Patent application US 2010/0231430 fig.11 8. Patent US 4.912.469 fig.5, fig.6 9. Patent US 6.437.724 fig.4 10. Patent US 5.175.550 fig.2 11. Patent US 6.847.320 fig.2 12. Patent US 6.882.294 fig.3 13. Patent DE 2009/002062 fig.3 14. Patent US 5.307.067 fig.1 15. Patent US 4.745.393 fig.1 16. Patent US 5.204.679 fig.1 17. Patent US 4.719.447 fig.1 18. Patent US 4.774.498 fig.13 19. Patent US 4.768.016 fig.1 20. Patent US 7.196.649 fig.1 21. Patent US 4.752.766 fig.5 22. Patent DE 2009/002062 fig.1 23. Patent US 5.231.399 fig.2 24. Patent US 4.578.715 fig.4 25. Patent US 4.831.379 fig.4 26. Patent application US 2008/036536 27. Patent US 4.763.106 fig.1 28. Y.Borokhovych. 4-bit, 16 GS/s ADC with new Parallel Reference Network. / Y.Borokhovych, H.Gustat, C.Scheytt // COMCAS 2009-2009 IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems 29. Serebryakov A.I. Method of improving performance of a parallel ADC. / Ahikereru, Abbrogated. // Solid-state electronics. Complex functional blocks REA: materials of the scientific-technical conference. - M.: MENTORES them. Popov Central Museum of communications, 2012. - P.150-155. 1. Ultrahigh-speed parallel analog-to-digital Converter with differentia inim entrance each of the N sections of which contains a voltage comparator (1), first (2) an input connected to the first (3) a source of input voltage through the first (4) reference resistor, and the second (5) comparator input voltage (1) is connected to the second (6) the input phase voltage through the second (7) reference resistor, and the first (2) comparator input voltage (1) associated with the first (8) the reference current and the first (9) of the parasitic capacitor, the second (5) comparator input voltage (1) associated with the second (10) the reference current and the second (11) of the parasitic capacitor, characterized in that the first (8) the reference current is made in the form of the first (12) current mirrors, consistent with the first (13) bus power source, and first (14) the auxiliary reference current connected to the input of the first (12) of the current mirror, and the output of the first (12) of the current mirror is the output of the first (8) reference current, and the second (6) input phase voltage associated with the input the first (12) of the current mirror through a first (15) corrective capacitor. 2. Ultrahigh-speed parallel analog-to-digital Converter with a differential input according to claim 1, characterized in that the second (10) the reference current is made in the form of the second (16) of the current mirror that is consistent with the first of the (13) bus power supply, and second (17) auxiliary reference current connected to the input of the second (16) of the current mirror, and the output of the second (16) of the current mirror is the output of the second (10) reference current, and (3) the source of input voltage connected to the input of the second (16) of the current mirror via a second (18) the correction capacitor. 3. Ultrahigh-speed parallel analog-to-digital Converter with a differential input according to claim 2, characterized in that in series with each correction capacitor (15) and (18) includes additional resistors.
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