Pulse selector

IPC classes for russian patent Pulse selector (RU 2518638):

H03K5/26 - the characteristic being duration, interval, position, frequency, or sequence

Another patents in same IPC classes:

Pulse selector / 2517295

Pulse selector is designed to reproduce the med(τ₁,…,τ₅) operation, where τ₁,…,τ₅ denote the duration of positive pulses of signals x₁,…,x₅∈{0,1}, synchronised on the leading edge, and can be used in automatic control systems as an information preprocessing means. The pulse selector comprises a resistor (1) and fourteen switches (2₁₁,…,2₄₂).

Pulse selector / 2516568

In operations min(τ₁, τ₂) or max(τ₁, τ₂), where τ₁, τ₂ are lengths of positive pulse signals x₁, x₂ ∈ {0, 1} synchronised at their leading edge. The pulse selector contains an opening key and a resistor connected between the output of the opening key and the third input of the pulse selector, which first and second inputs and output are connected to the control input, input and output of the opening key respectively.

Pulse selector / 2514782

Invention can be used for logic processing of positive pulse signals x₁,…,x_n∈{0.1} synchronised against their leading edge and having pulse lengths of τ₁,…,τ_n. The operations min(τ₁,…,τ_n), supramin(τ₁,…,τ_n), submax(τ₁,…,τ_n), max(τ₁,…,τ_n) are described. The device contains n-1 of EXCLUSIVE OR (1₁,…,1_n-1) elements, n-1 of locking keys (2₁,…,2_n-1), a resistor (3), n-2 of unlocking keys (4₁,…,4_n-1) and n-2 of additional locking keys (5₁,…,5_n-2).

Pulse selector / 2479119

Method is realised by enabling selection of a component τ_i=τ ⁽²⁾ from a sequence (τ₁,…, τ_n), where said component occupies a given position in a relationship of the order τ⁽¹⁾≤…≤τ⁽ⁿ⁾, obtained by non-decreasing ranking of the component τ₁,…, τ_n, where τ₁,…, τ_n denote time intervals defined by duration of leading-edge synchronised positive pulse signals x₁,…, x_n ∈ {0,1}. The pulse selector has 3n-4 switches (1₍₁₎₍₁₎,…, 1_(3)(n-2), 1_3n-5, 1_3n-4) and a resistor (2).

Pulse selector / 2469471

Pulse selector is designed for selection from sequence (τ₁, …, τ_n) of component τ^(r) occupying the specified r (r∈{1, …, n}) place in the ratio of the order τ⁽¹⁾≤….≤τ⁽ⁿ⁾, which has been obtained by non-decreasing rating of components τ₁, …, τ_n, where τ₁, …, τ_n are time intervals determined with durations of positive pulse signals x₁, …, x_n∈{0,1} synchronised as to front edge, and can be used in automatic control and monitoring systems as preliminary information processing device. Pulse selector includes closing switches (1₁, …, 1_n), resistors (2₁, …, 2_n), operating amplifier (3), comparator (4), delay elements (5₁, …, 5_n), elements EXCLUSIVE OR (6₁, …, 6_n) and RS-triggers (7₁, …, 7_n). Due to EXCLUSIVE OR elements, delay elements and RS-triggers there provided is identification of number of information input on which a selective pulse signal acts.

Time interval selector / 2465722

Device has read-only memory and n closing switches. The time interval selector is meant for selecting a component τ^(r) from a sequence (τ₁,…, τ_n), where said component occupies a given place r-e (r∈{1,…,n}) in the order τ⁽¹⁾≤…≤τ⁽ⁿ⁾, obtained by non-decreasing ranking of the component τ₁,…,τ_n, where τ₁,…,τ_n are time intervals defined by duration of leading edge-synchronised positive pulsed signals x₁,…,x_n∈{0,1}.

Pulse selector / 2417516

Proposed selector serves to reproduce operations min(τ₁,…,τ_n), max(τ₁,…,τ_n), where (τ₁,…,τ_n) is duration of positive pulse signals (x₁,…,x_n),∈{0,1}, synchronised by leading edge, and may be used in ACS as data preprocessor. Proposed device comprises n-1 elements EXLUSIVE OR, and n-1 closing switches and resistor.

Pulse selector by repetition cycle / 2415509

Device comprises generator, address counter, memorising unit, six triggers, four "AND" circuits, two "OR" circuits, counter of digitisation intervals, three circuits of comparison, frequency divider, controlled frequency divider, counter-decoder, period counter, summator.

/ 2332784

/ 2332783

/ 2264030

/ 2273090

/ 2286009

/ 2325756

/ 2328070

/ 2332783

/ 2332784

Pulse selector by repetition cycle / 2415509

Pulse selector / 2417516

Time interval selector / 2465722

FIELD: electricity.

SUBSTANCE: in supramed operation (τ₁,…,τ₇) τ₁,…,τ₇ there are lengths of positive pulse signals x₁,…,x₇∈{0.1} synchronised against the front edge. The device contains a resistor and twenty four keys grouped in six groups.

EFFECT: implementation of supramed operation.

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The invention relates to a pulse technique and can be used for building automation, functional units of the control systems and other

Known pulse selectors (see, for example, rise on p.15 in the book Potemkin I.S. Functional units of digital automation. M.: Energoatomizdat, 1988), which reproduce the operation supramed (τ₁τ₂τ₃), where τ₁τ₂τ₃have a duration of three positive pulse signals that are synchronized on the leading edge.

For the reason that impede the achievement of specified following technical result when using the known pulse selectors include limited functionality due to the fact that no Pets processing seven pulse signals.

The closest device to the same destination to the claimed invention by the combination of features is adopted for the prototype pulse selector (RIS on s in the book: Handbook of digital computing. Malinowski, B., Alexandrov VA, Boun VP and others/edited by B.N. Malinowski. Kyiv: Tekhnika, 1974), which contains a resistor and reproduces the operation supramed (τ₁τ₂τ₃), where τ₁τ₂τ₃is the duration of the positive pulse signals x₁x₂x₃∈{0,1}, synchronize avannah on the leading edge.

For the reason that impede the achievement of specified following technical result when using the prototype include limited functionality due to the fact that no Pets processing seven pulse signals.

The technical result of the invention is the extension of functionality by providing playback operation supramed (τ₁,...,τ₇), where τ₁,...,τ₇is the duration of the positive pulse signals x₁,...,x₇∈{0,1}, synchronized on the leading edge.

This technical result in the implementation of the invention is achieved in that in the pulse selector containing a resistor, the peculiarity lies in the fact that it introduced the twenty-four keys, which are grouped into six groups so that the first i-I $(i = \overset{}{2,4})$ fifth and sixth groups contain, respectively, three, five, four and two keys, odd and even keys educated groups performed respectively closing and tripping, in each group, the output of the previous odd key connected to the output of the next key in each group except the sixth sign of the previous even-numbered key is connected to the input of the m subsequent key the inputs of the first, third and fifth keys j $(j = \overset{}{3,4})$ group are connected respectively to the outputs of the first, third and fifth switches (j-1)-th group, the outputs of the first, third and the inputs of the first, third, and fourth keys of the fifth group are connected respectively to the inputs of the first and second keys of the sixth group and the outputs of the first, third and fifth keys of the fourth group, and the inputs of the first and third and fifth keys of the second group are connected respectively to the bus reference potential and outputs the first, third keys of the first group, inputs connected respectively to the bus zero potential, the seventh input pulse selector, the k-th $(k = \overset{}{1,6})$ the input and output of which are connected respectively with the control input of all keys k-th group and the release of the first key of the sixth group connected through a resistor to the bus unit capacity.

Figure 1 presents the scheme of the proposed pulse selector. Figure 2 shows the timing chart explaining how it works.

Pulse selector contains a resistor 1 and wadati four key 2 ₁₁,...,2₆₂, which are grouped into six groups so that the first i-I $(i = \overset{}{2,4})$ fifth and sixth groups contain, respectively, three key 2₁₁, 2₁₂, 2₁₃five keys 2_i1, 2_i2, 2_i3, 2_i4, 2_i5four key 2₅₁, 2₅₂, 2₅₃, 2₅₄and two keys 2₆₁2₆₂and even and odd keys educated groups performed respectively closing and tripping, in each group, the output of the previous odd key connected to the output of the next key in each group except the sixth sign of the previous even-numbered key is connected to the input of the following key inputs key 2_j1, 2_j3, 2_j5, $(j = \overset{}{3,4})$ connected respectively to the outputs of keys 2_(j-1)1, 2_(j-1)3, 2_(j-1)5the outputs of keys 2₅₁, 2₅₃and the input keys 2₅₁, 2₅₃, 2₅₄connected respectively to the inputs of keys 2₆₁, 2₆₂and outputs key 2₄₁, 2₄₃, 2₄₅and the input keys 2₂₁and 2₂₃, 2₂₅connected respectively with the bus zero on the potential and outputs key 2 ₁₁, 2₁₃connected inputs respectively to the bus zero potential, the seventh input pulse selector, the k-th $(k = \overset{}{1,6})$ the input and output of which are connected respectively with the control input of all keys k-th group and the exit key 2₆₁connected through the resistor 1 to the bus unit capacity.

The work of the proposed pulse selector is as follows. On his first, ..., seventh inputs are given correspondingly synchronized on the leading edge of a positive pulse signals x₁...x₇∈{0,1}, with duration τ₁,...,τ₇respectively. If the control input of all the keys of an arbitrary group applies a logical "1" or a logical "0", then each even-numbered key of this group is respectively closed or open, and every odd key respectively open or closed. Thus, the pulse signal at the output of the proposed pulse selector is defined by the expression

$\begin{array}{l} Z = \overset{}{{\overset{}{x}}_{2} {\overset{}{x}}_{3} {\overset{}{x}}_{4} {\overset{}{x}}_{5} {\overset{}{x}}_{6} \lor {\overset{}{x}}_{1} x_{2} {\overset{}{x}}_{3} {\overset{}{x}}_{4} {\overset{}{x}}_{5} {\overset{}{x}}_{6} \lor {\overset{}{x}}_{1} {\overset{}{x}}_{2} x_{3} {\overset{}{x}}_{4} {\overset{}{x}}_{5} {\overset{}{x}}_{6} \lor {\overset{}{x}}_{1} {\overset{}{x}}_{2} {\overset{}{x}}_{3} x_{4} {\overset{}{x}}_{5} {\overset{}{x}}_{6} \lor {\overset{}{x}}_{1} {\overset{}{x}}_{2} {\overset{}{x}}_{3} {\overset{}{x}}_{4} x_{5} {\overset{}{x}}_{6} \lor} \\ \overset{}{\lor {\overset{}{x}}_{1} {\overset{}{x}}_{2} \overset{}{x} {\overset{}{x}}_{4} {\overset{}{x}}_{5} x_{6} \lor x_{1} x_{2} {\overset{}{x}}_{3} {\overset{}{x}}_{4} {\overset{}{x}}_{5} {\overset{}{x}}_{6} {\overset{}{x}}_{7} \lor x_{1} {\overset{}{x}}_{2} x_{3} {\overset{}{x}}_{4} {\overset{}{x}}_{5} {\overset{}{x}}_{6} {\overset{}{x}}_{7} \lor x_{1} {\overset{}{x}}_{2} {\overset{}{x}}_{3} x_{4} {\overset{}{x}}_{5} {\overset{}{x}}_{6} {\overset{}{x}}_{7} \lor} \\ \overset{}{\lor x_{1} {\overset{}{x}}_{2} {\overset{}{x}}_{3} {\overset{}{x}}_{4} x_{5} {\overset{}{x}}_{6} {\overset{}{x}}_{7} \lor x_{1} {\overset{}{x}}_{2} {\overset{}{x}}_{3} {\overset{}{x}}_{4} {\overset{}{x}}_{5} x_{6} {\overset{}{x}}_{7} \lor {\overset{}{x}}_{1} x_{2} {\overset{}{x}}_{3} {\overset{}{x}}_{4} {\overset{}{x}}_{5} {\overset{}{x}}_{6} {\overset{}{x}}_{7} \lor {\overset{}{x}}_{1} x_{2} {\overset{}{x}}_{3} x_{4} {\overset{}{x}}_{5} {\overset{}{x}}_{6} {\overset{}{x}}_{7} \lor} \\ \overset{}{\lor {\overset{}{x}}_{1} x_{2} {\overset{}{x}}_{3} {\overset{}{x}}_{4} x_{5} {\overset{}{x}}_{6} {\overset{}{x}}_{7} \lor {\overset{}{x}}_{1} x_{2} {\overset{}{x}}_{3} {\overset{}{}}_{4} {\overset{}{x}}_{5} x_{6} {\overset{}{x}}_{7} \lor {\overset{}{x}}_{1} {\overset{}{x}}_{2} x_{3} x_{4} {\overset{}{x}}_{5} {\overset{}{x}}_{6} {\overset{}{x}}_{7} \lor {\overset{}{x}}_{1} {\overset{}{x}}_{2} x_{3} {\overset{}{x}}_{4} x_{5} {\overset{}{x}}_{6} {\overset{}{x}}_{7} \lor} \\ \overset{}{\lor {\overset{}{x}}_{1} {\overset{}{x}}_{2} x_{3} {\overset{}{x}}_{4} {\overset{}{x}}_{5} x_{6} {\overset{}{x}}_{7} \lor {\overset{}{x}}_{1} {\overset{}{x}}_{2} {\overset{}{x}}_{3} x_{4} x_{5} {\overset{}{x}}_{6} {\overset{}{x}}_{7} \lor{\overset{}{x}}_{1}{\overset{}{x}}_{2}{\overset{}{x}}_{3}x_{4}{\overset{}{x}}_{5}{\overset{}{x}}_{6}{\overset{}{x}}_{7}\lor{\overset{}{x}}_{1}{\overset{}{x}}_{2}{\overset{}{x}}_{3}{\overset{}{x}}_{4}x_{5}x_{6}{\overset{}{x}}_{7}\lor} = \\ = (x_{2} \lor x_{3} \lor x_{4} \lor x_{5} \lor x_{6}) (x_{1} \lor {\overset{}{x}}_{2} \lor x_{3} \lor x_{4} \lor x_{5} \lor x_{6}) (x_{1} \lor x_{2} \lor {\overset{}{x}}_{3} \lor x_{4} \lor x_{5} \lor x_{6}) \cdot \\ \cdot (x_{1} \lor x 2 \lor x_{3} \lor {\overset{}{x}}_{4} \lor x_{5} \lor x_{6}) (x_{1} \lor x_{2} \lor x_{3} \lor {\overset{}{x}}_{4} \lor {\overset{}{x}}_{5} \lor x_{6}) (x_{1} \lor x_{2} \lor x_{3} \lor {\overset{}{x}}_{4} \lor x_{5} \lor {\overset{}{x}}_{6}) \cdot \\ \cdot ({\overset{}{x}}_{1} \lor {\overset{}{x}}_{2} \lor x_{3} \lor {\overset{}{x}}_{4} \lor x_{5} \lor x_{6} \lor x_{7}) ({\overset{}{x}}_{1} \lor x_{2} \lor {\overset{}{x}}_{3} \lor {\overset{}{x}}_{4} \lor x_{5} \lor x_{6} \lor x_{7}) \cdot \\ \cdot ({\overset{}{x}}_{1} \lor x_{2} \lor x_{3} \lor {\overset{}{x}}_{4} \lor x_{5} \lor x_{6} \lor x_{7}) ({\overset{}{x}}_{1} \lor x_{2} \lor x_{3} \lor {\overset{}{x}}_{4} \lor {\overset{}{x}}_{5} \lor x_{6} \lor x_{7}) \cdot \end{array}$

$\begin{array}{l} \cdot ({\overset{}{x}}_{1} \lor x_{2} \lor x_{3} \lor x_{4} \lor x_{5} \lor {\overset{}{x}}_{6} \lor x_{7}) (x_{1} \lor {\overset{}{x}}_{2} \lor {\overset{}{x}}_{3} \lor x_{4} \lor x_{5} \lor x_{6} \lor x_{7}) \cdot \\ \cdot (x_{1} \lor {\overset{}{x}}_{4} \lor x_{5} \lor x_{6} \lor x_{7}) (x_{1} \lor {\overset{}{x}}_{2} \lor x_{3} \lor x_{4} \lor {\overset{}{x}}_{5} \lor x_{6} \lor x_{7}) \cdot \\ \cdot (x_{1} \lor {\overset{}{x}}_{2} \lor x_{3} \lor x_{4} \lor x_{5} \lor {\overset{}{x}}_{6} \lor x_{7}) (x_{1} \lor x_{2} \lor {\overset{}{x}}_{3} \lor {\overset{}{x}}_{4} \lor x_{5} \lor x_{6} \lor x_{7}) \cdot \\ \cdot (x_{1} \lor x_{2} \lor {\overset{}{x}}_{3} \lor x_{4} \lor {\overset{}{x}}_{5} \lor x_{6/mn>} \lor x_{7}) (x_{1} \lor x_{2} \lor {\overset{}{x}}_{3} \lor x_{4} \lor x_{5} \lor {\overset{}{x}}_{6} \lor x_{7}) \cdot \\ \cdot (x_{1} \lor x_{2} \lor x_{3} \lor {\overset{}{x}}_{4} \lor {\overset{}{x}}_{5} \lor x_{6} \lor x_{7}) (x_{1} \lor x_{2} \lor x_{3} \lor {\overset{}{x}}_{4} \lor x_{5} \lor {\overset{}{x}}_{6} \lor x_{7}) \cdot \\ (x_{1} \lor x_{2} \lor x_{3} \lor x_{4} \lor {\overset{}{x}}_{5} \lor {\overset{}{x}}_{6} \lor x_{7}) = x_{1} x_{2} x_{3} \lor x_{1} x_{2} msub> x 4 \lor x_{1} x_{2} x_{5} \lor x_{1} x_{2} x_{6} \lor x_{1} x_{2} x_{7} \lor x_{1} x_{3} x_{4} \lor \\ \lor x_{1} x_{3} x_{5} \lor x_{1} x_{3} x_{6} \lor x_{1} x_{3} x_{7} \lor x_{1} x_{4} x_{5} \lor x_{1} x_{4} x_{6} \lor x_{1} x_{4} x_{7} \lor x_{1} x_{5} x_{6} \lor x_{1} x_{5} x_{7} \lor x_{1} x_{6} x_{7} \lor \\ \lor x_{2} x_{3} x_{4} \lor x_{2} x_{3} x_{5} \lor x_{2} x_{3} x_{6} \lor x_{2} x_{3} x_{7} \lor x_{2} \end{array}$ x 4 x 5 ∨ x 2 x 4 x 6 ∨ x 2 x 4 x 7 ∨ x 2 x 5 x 6 ∨ x 2 x 5 x 7 ∨ ∨ x 2 x 6 x 7 ∨ x 3 x 4 x 5 ∨ x 3 x 4 x 6 ∨ x 3 x 4 x 7 ∨ x 3 x 5 x 6 ∨ x 3 x 5 x 7 ∨ x 3 x 6 x 7 ∨ x 4 x 5 x 6 ∨ x 4 x 5 x 7 ∨ ∨ x 4 x 6 x 7 ∨ x 5 x 6 x 7 , ( 1 )

where ·, ∨, is a symbol of conjunction, disjunction,inversion. According to (1) have

$Z = {\begin{cases} 1 p p and \sum_{q = 1}^{7} x_{q} \geq 3 \\ 0 p p and \sum_{q = 1}^{7} x_{q} < 3 \end{cases} .$

Therefore, the selector (1) to reproduce the operation τ_Z=supramed (τ₁,...,τ₇(see figure 2).

The above data allow us to conclude that the proposed pulse selector has a wider compared to the prototype functionality, as it provides processing seven pulse signals.

The pulse selector containing a resistor, characterized in that it introduced the twenty-four keys, which are grouped into six groups so that the first i-I $(i = \overset{}{2,4})$ fifth and sixth groups contain, respectively, three, five, four and two keys, and even and odd keys educated groups you who Olney respectively closing and tripping, in each group, the output of the previous odd key connected to the output of the next key in each group except the sixth sign of the previous even-numbered key is connected to the input of the following key inputs of the first, third and fifth keys j $(j = \overset{}{3,4})$ group are connected respectively to the outputs of the first, third and fifth switches (j-1)-th group, the outputs of the first, third and the inputs of the first, third, and fourth keys of the fifth group are connected respectively to the inputs of the first and second keys of the sixth group and the outputs of the first, third and fifth keys of the fourth group, and the inputs of the first and third and fifth keys of the second group are connected respectively to the bus reference potential and outputs the first, third keys of the first group, inputs connected respectively to the bus zero potential, the seventh input pulse selector, the k-th $(k = \overset{}{1,6})$ the input and output of which are connected respectively with the control input of all keys k-th group and the release of the first key of the sixth group connected through a resistor to the bus unit potential is and.