Analogue-to-digital converter and zero offset calibration method

IPC classes for russian patent Analogue-to-digital converter and zero offset calibration method (RU 2520427):

H03M1/10 - CODING, DECODING OR CODE CONVERSION, IN GENERAL (using fluidic means F15C0004000000; optical analogue/digital converters G02F0007000000; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

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FIELD: radio engineering, communication.

SUBSTANCE: high-speed N-bit combined analogue-to-digital converter (ADC) includes an input parallel M-bit ADC1, an M-bit digital-to-analogue converter (DAC1), a sampling and storage device (SSD) and a pipelined (N-M+1)-bit ADC2. The M-bit ADC1 and DAC1 employ a common serial resistance divider. The SSD with double sampling, consisting of an amplifier and two samplers, generates a different signal of the input voltage of the ADC and the output voltage of the DAC. The entire analogue circuit of the ADC is differential. The ADC implements individual zero offset calibration for different samplers, for which are used two identical calibration DACs and a switch which transmits to the amplifier of the SSD a calibration signal corresponding to the sampler in storage mode, from one of the calibration DACs. During calibration, a zero differential signal with an in-phase level equal to or close to the in-phase level of the input signal is transmitted to the input of the SSD.

EFFECT: reduced conversion error of an ADC by eliminating separation of zero offset on samplers by performing zero offset calibration separately for each sampler.

3 cl, 4 dwg

The invention relates to electronics and can be used in systems for processing analog signals and convert the analog information to digital, in particular, in high-speed analog-to-digital converters (ADC).

The purpose of the invention is the reduction of error of the ADC conversion by reducing the influence of the error element parameters using calibration.

There are many schemes of high-speed ADC. For example, in U.S. patent 5,574,457 from 12.11.1996,, MKI NM "Switched capacitor gain stage" presents a cascade of pipelined ADC with dual sampling and ADC based on it. This cascade includes two sampler on switched capacitors with a common amplifier. Double sampling allows you to double the conversion rate compared to a single sample. The lack of ADC with dual sample is eidentical parameters of the samples caused by natural dispersion elements and leading to error of conversion and degradation of dynamic ADC parameters.

Methods of calibration of ADC and their effectiveness is largely determined by the architecture and features of the ADC. The object of the present invention is the implementation and the method of calibrating the zero offset in ADC with dual sample.

Closest to the claimed is ADC and the method of its calibration, presented in the patent of the Russian Federation No. 2442279, IPC NM/10 (2006.01), published on 10.02.2012, Bulletin No. 4. Significant features of the ADC circuit of the prototype is depicted in figure 1.

Known N-bit ADC includes:

M-bit parallel ACP 110, the inlet of which is connected to the input of the ADC 100, the M-bit digital-to-analog Converter (CAP) 120, the input of which is controlled by the output ACP, and ACP and CAP use a common serial resistive divider 130;

device sampling and storage (water economy Department) 140 that generates an output signal equal to or a multiple of the difference between the input signal of the ADC and the output signal TAP;

- to improve noise immunity all analog path ADC, including ACP, CAP and water economy Department, is differential;

The water economy Department (Figure 3) scheme with double sampling, which are two differential sampler And 310 and 320 on the switched capacitors with a common differential amplifier 360. At any time one sampler is in sampling mode (figure 3 - sampler), the other is in storage mode (figure 3 - sampler). At each stage switching of samplers;

- (N-M+1)-bit pipelined ACP 150 with the input connected to the output of the water economy Department;

block logic ADC 160, forming of the output codes ACP 162 and ASP 164 ADC output code 166;

- keys calibration 170 applying calibration to the input of the water economy Department of the zero differential signal;

- TAPU, Caleb ovci zero offset 180, forming a signal for the calibration of the operational amplifier, the water economy Department so that at zero signal at the ADC input at its output code is generated, exactly or closely corresponding to zero input signal;

the logic block calibration 190, the input of which is connected to the senior discharge outlet AZP, and outputs connected to the inputs CAP, TAPU and keys calibration 170.

Known for the prototype ADC is as follows.

ACP 110 produces a parallel analog-to-digital conversion of the input signal 100 and determines the M high-order bits of the output code of the ADC. The result of the conversion ACP is fed to the input M-bit CAP 120, which forms at its output a voltage equal to one of the 2^M+1 reference levels divider closest to the input signal. The water economy Department 140 generates at its output a signal equal to or a multiple of the difference between the input signal of the ADC 100 and the output voltage CAP.

The logic block ADC 160 forms of M-bit code ACP 162 and (N-M+1)-bit code ACP 164 N-bit output code of the ADC 166 using excessive discharge for digital error correction for a known schema.

When calibrating the keys calibration 170 serves to input the water economy Department of the zero differential signal. This is achieved by switching both shoulders differential input water economy Department 140 from the ADC input to a circuit with a known potential, for example, the average of the water resistive divider. Thus, at the entrance of the water economy Department formed a zero differential voltage. In CAP 120 load code 2^M-1also the corresponding differential zero at its output. In this state, both of the differential inputs of the water economy Department are zero signal, and the ADC converts its zero offset digital code. When this analog input of the ADC 100 is disconnected from the water economy Department. Then use the method of successive approximation to determine the code of the DAC 180, which switches the high order bit of the output code ACP. The code of the DAC corresponds to its output signal, which compensate the offset of zero, and is used during normal operation of the ADC after calibration.

The advantage of considering known ADC is the possibility to calibrate the zero offset of the ADC. This parameter is important in some applications.

The main disadvantage of the ADC and method of its calibration is different offset zero in the two samples, resulting in a residual error, not disposable described method of calibration. Zero offset caused by the mismatch of the capacitors and the keys of the samplers in the differential shoulders and water economy Department of the difference between the common mode level of the input signal of the ADC and output CAP. This leads to a conversion error and the degradation of dynamic performance of the ADC. In particular, in the spectrum of the output code of the ADC component appears at the frequency the Nyquist.

The aim of the present invention is to reduce the error of the ADC conversion by eliminating stratification offset by samplers by introducing calibration zero offset for each individual sampler.

This objective is achieved in that in an N-bit analog-to-digital Converter with calibration zero offset, including M-bit parallel ACP, whose input is connected to the ADC input, the M-bit digital-to-analog Converter CAP, the entrance of which is controlled by the output ACP, and ACP and CAP use a common serial resistive divider device for sampling and storing the water economy Department with double sampling, carried out alternately by the samplers a and b, forming an output signal equal to or a multiple of the difference between the input signal of the ADC and the output signal CAP, (N-M+1)-bit pipelined ACP, whose input is connected to the output of the water economy Department, and ACP, CAP, water economy Department and ACP are differential, the logic block ADC that generates output codes ACP and ACP output code ADC, DAC calibration, forming the signal calibration zero offset of the amplifier, the water economy Department, the keys of the calibration filing with the calibration in the water economy Department of the zero differential signal, the logic block calibration, the input of which is connected to the senior discharge outlet ACP, and the output controls CAP, TAPU and keys calibration, inputs of the DAC is calibrated and the switch, applying for water economy Department of amplifier signal calibration zero offset from the DAC or CAPV corresponding to the sampler, in the moment of time in storage.

This goal is achieved by a method of calibrating the ADC, wherein the keys of the calibration serves to input the water economy Department of the zero differential signal, to the input CAP code serves 2^M-1determine individually for each of the two samples a and b codes calibration zero offset corresponding to the switching of the senior discharge ACP, and load them into a DAC and ZAPU, and during normal operation through a switch on the amplifier the water economy Department of signal calibration from TAPU or CAPV corresponding to the sampler, in the moment of time in storage.

This goal is achieved also by a method of calibrating the ADC, wherein the keys of the calibration serves to input the water economy Department of the zero differential signal with a common mode level that is equal to or close to the common mode level of the input signal.

The invention is illustrated by drawings:

- figure 1 shows the scheme of the closest declare known ADC (prototype);

- figure 2 presents the diagram of the inventive ADC according to claims 1, 2 and 3 Formulas;

- figure 3 presents the scheme of differential water economy Department of the double sample;

- figure 4 presents the spectra of the output code of the ADC with individual calibration offset OLEDs each sampler and without it.

Below is a description of the structure and operation of the inventive ADC.

Figure 2 presents the diagram of the inventive ADC. The input signal 100 is supplied to the inputs ACP 110 and the water economy Department 140. ACP produces a parallel analog-to-digital conversion of the input signal and determines the M high-order bits of the output code of the ADC. The result of the conversion ACP is fed to the input M-bit CAP 120 that generates the output voltage equal to the voltage of one of the 2^M+1 reference levels divider closest to the input signal. The water economy Department 140 generates at its output a voltage equal to or a multiple of the difference between the input signal of the ADC and the output voltage CAP. The output signal of the water economy Department arrives on the input conveyor (N-M+1)-bit ACP 150. The logic block ADC 160 collects the M-bit code ACP 162 and (N-M+1)-bit code ACP 164 in the N-bit output code of the ADC 166. Redundancy codes used for error correction Comparators ACP.

The logic block calibration 190 controls the calibration process and calculates the calibration codes applied to the inputs of the DAC 182 and ZAPU 184. The outputs of the DAC and ZAPU signals are formed calibration kompensiruyushchie zero offset of each of his sampler. The switch 186 selects the signal calibration corresponding to the sampler, in the moment of time in storage mode, and supplies it to the differential amplifier, the water economy Department of 140.

It should be noted that to reduce errors of calibration, due to the processes established in the amplifier the water economy Department after switching signal calibration, it is advisable to perform a DAC and ZAPU with current outputs and to use as a switch circuit switching current signals calibration, control the zero offset of the amplifier, the water economy Department.

Figure 3 shows a diagram of the differential water economy Department of the double sample. Sampler 310 And includes two differential shoulder 312 and 314. Sampler 320 includes two differential shoulder 322 and 324. Figure 3 shows the details of only one positive shoulder a sampler 312 And 310. Other shoulders 314, 322 and 324 have the same structure. Signals Vip 330 and 332 Vin form a differential input signal of the water economy Department. Signals Vdp 340 and Vdn 342 form a second differential input signal, the water economy Department subtracted from the first. Signals Vop 350 and 352 Von form a differential output signal of the water economy Department. The water economy Department has two samplers differential amplifier 360.

Figure 3 keys 373, 374, 377 are in a conducting state, and the keys 375, 376, 378 in a non-conductive state. Sampler And is located in the state of selection, that is connected to the ADC input and monitors the change of the input voltage. The keys of the sampler are in the opposite state, and the sampler is in storage and connected to a differential amplifier 360 and the differential input of the water economy Department of Vdp/Vdn.

Let us introduce the notation di is ferentially signals:

$V i = V i p - V i n$

$V d = V d p - V d n$

$V o = V o p - V o n$

then for the perfect water economy Department

$V o = (V i - V d) * C 1 / C 2 (1)$

The ratio of the capacitances of the capacitors 141 and 142 SR/SR determines the transmission coefficient of the water economy Department. Thus, the ADC prototype SR/SR=2. Consider the case of a mismatch of the capacitors under ideal amplifier the water economy Department. Let C1p/C2p=2+mp, where mp is a little random for a specific ADC and a sampler value, standard deviation which depends on the size of the capacitors and the technological process of manufacturing. In the General case, the mismatch of the capacitors in different shoulders of one differential sampler can be varied. Then C1n/C2n=2+mn, and the expression (1) takes the form:

$V o = (V i - V d) * 2 + (V i p - V d n) * m p - (V i n - V d n) * m n (2)$

The quantity e=(Vip-Vdp)*mp-(Vin-Vdn)*mn represents a sampler error caused by the mismatch of the capacitors.

Now imagine voltage shoulders differential input signals with respect to their common-mode levels Vic, Vdc:

$V i p = V i c + V i / 2$	$V i n = V i c - V i / 2$
$V d p = V d c + V d / 2$	$V d n = V dc-Vd/2$

Substituting these stresses in the expression for the error of the sampler, get:

$\begin{array}{l} e = (V i c * m p + V i / 2 * m p) - (V d c * m p + V d / 2 * m p) \\ - (V i c * m n - V i / 2 * m n) + (V d c * m n - V d / 2 * m n) \\ = V i c * (m p - m n) - V d c * (m p - m n) + V i / 2 * (m p + m n) - V d / 2 * (m p + m n) \\ = (V i c - V d c) * (m p - m n) + (V i - V d) * (m p + m n) / 2 \end{array}$

Now the expression (2) takes the form:

$V o = (V i - V d) * (2 + (m p + m n) / 2) + (V i c - V d c) * (m p - m n) (3)$

Now let the power of the water economy Department has its own zero offset Vz. Then, accurate to small quantities of the second order, determined by the product of the small zero offset to a small mismatch of the capacitors, the expression (3) takes the form:

$V o = V z + (V i - V d) * (2 + (m p + m n) / 2) + (V i c - V d c) * (m p - m n) (4)$

During calibration Vi=Vd=0 and the expression (4) is reduced to:

$V o = V z + (V i c - V d c) * (m p - m n) (5)$

The first component Vz in the expression (5) represents a zero offset of the amplifier, the water economy Department and is calibrated by the method proposed in the prototype.

The second term (Vic-Vdc)*(mp-mn) in the expression (5) represents an additional zero offset caused by the mismatch of the capacitors. Additional zero offset in different samplers are determined by the mismatch of different and independent groups of capacitors and, therefore, have different values.

The second term in the expression (5) also depends on the difference (Vic-Vdc) common-mode level of the input signal and output CAP. It is important that the value of this difference was the same during calibration and normal operation of the ADC. Otherwise, part of the additional zero offset will remain Neot is alibrandi.

Different alternating time-offset of samplers cannot be reduced simply to the zero offset of the ADC. These errors degrade the dynamic performance and manifest as a component of the output spectrum of the ADC at the Nyquist frequency.

Figure 4 shows the spectrum of a 12 bit ADC with double sampling. The upper diagram the zero offset of the samples are equal, which may be in the hypothetical absence of the mismatch of the capacitors. On the bottom chart, the zero offset of the samplers differ by 1 least significant bit. You can see the appearance of the lower diagram of spectral components to the Nyquist frequency at the level of -73 dBFS and reducing the signal-to-noise + distortion (SNDR) at 1.6 dBFS.

To resolve the error zero offset of the ADC according to claim 1 of the Formula includes (Figure 2):

the logic block calibration 190 that controls the calibration process and calculates the calibration codes;

- TAPU 180 and ZAPU 184, forming signals calibration kompensiruyushchie zero offset of each of his sampler;

switch 186, which selects the signal calibration DAC or CAPV for a sampler, in the moment of time in storage mode, and feed it to the differential amplifier, the water economy Department of 140.

In accordance with paragraph 2 of the Formula calibration is carried out individually for each sampler. For this purpose (see Figure 2) keys calibration 170 under control of the logic block calibration 19 serves to input the water economy Department of differential zero signal. In the particular case of the keys of the calibration 170 connects the two shoulder differential input water economy Department of the middle tap of the divider 130. The logic block calibration 190 loads in CAP 120 code 2^M-1also the corresponding differential zero at its output. Thus, both of the differential inputs of the water economy Department set to zeros. Configured the ADC converts its zero offset in tsipouri code.

It should be noted that the water economy Department is not the only, albeit dominant, source of zero offset of the ADC. In addition, an additional source of bias in the water economy Department is the parasitic capacitance of the signal tyres inputs of the amplifier, and different in different samples. In any case, the calibrated total zero offset of the ADC. This method solves exactly this problem.

In accordance with section 3 of the calibration Formula is fed to the input of the water economy Department of the zero differential signal with a common mode potential level equal to or close to the common mode level of the input signal. In this case, the keys of the calibration 170 connect both shoulders differential input water economy Department to the circuit with the potential common-mode level of the input signal. Thus, the constancy of the difference (Vic-Vdc) during calibration and normal operation of the ADC, which provides the most accurate calibration zero offset of the samples caused by the mismatch of the capacitors.

<> Next, the logic block calibration 190 organizes the process of binary search code TAPU and ZAPU that minimizes the zero offset for the sampler. The criterion for this procedure is the main nikodoby transition or switching bit older ACP. Different schemes are possible procedures for the two samplers, including averaging to reduce the effects of random noise on the calibration results. With modern possibilities of synthesis of logic it is not difficult.

Upon completion of the procedures of the binary search logic block calibration 190 loads of TAPU and ZAPU calibration codes corresponding to samples a and b, and enters normal operation. In this mode, the switch 186 selects one of the output signals of the calibration DAC or CAPV corresponding to the sampler, which is currently in storage mode, and supplies it to the amplifier, the water economy Department.

Note that individual calibration zero offset of the samplers in the water economy Department with double sampling can be implemented and one DAC calibration without the switch. It is necessary continuously to overload calibration codes for each sampler, and the DAC should have high performance, unattainable when the sampling rate of the ADC. The use of two Caps calibration and the current switch as the switch obespechivayushchuyu switching speed signal calibration the water economy Department.

In the present description unit logic ADC 160 and the logic block calibration 190 are separated solely on function. In real ADC both logic block can be represented by a single behavioral description and synthesized into a single topological block.

1. N-bit analog-to-digital Converter (ADC) calibration zero offset, including M-bit parallel ACP, whose input is connected to the ADC input, the M-bit digital-to-analogue Converter (CAP), whose input is controlled by the output ACP, and ACP and CAP use a common serial resistive divider, the unit of sampling and storage (water economy Department) with double sampling, carried out alternately by the samplers a and b, forming an output signal equal to or a multiple of the difference between the input signal of the ADC and the output signal CAP, (N-M+1)-bit pipelined ACP, the inlet of which is connected to the output of the water economy Department, and ACP, CAP, water economy Department and ACP are differential, the logic block ADC that generates output codes ACP and ACP output code ADC, DAC calibration, forming the signal calibration zero offset of the amplifier, the water economy Department, the keys of the calibration filing with the calibration in the water economy Department of the zero differential signal, the logic block calibration, the input of which is connected to the senior discharge outlet ACP, and the output controls CAP, keys, and a DAC calibration, and wherein the CPU further includes CAPV calibration and switch, applying for water economy Department of amplifier signal calibration zero offset from the DAC or CAPV corresponding to the sampler, in the moment of time in storage.

2. A method of calibrating the ADC according to claim 1, wherein the input of CAP code serves 2^M-1determine and loaded into a DAC code calibration zero offset corresponding to the switching of the senior discharge ACP at zero differential signal at the input of the water economy Department and characterized in that the calibration zero offset is conducted individually for each of the two samples a and b, the resulting codes calibration load, respectively, in a DAC and ZAPU, and during normal operation of the amplifier the water economy Department of the switch signal calibration from TAPU or CAPV corresponding to the sampler, in the moment of time in storage.

3. A method of calibrating the ADC according to claim 2, characterized in that the calibration in the water economy Department serves a zero differential signal with a common mode level that is equal to or close to the common mode level of the input signal.