IPC classes for russian patent Complementary differential amplifier with expanded active operation range. RU patent 2519544. (RU 2519544):
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Selective amplifier / 2465718
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Selective amplifier / 2467469
Present invention relates to radio engineering and communication and can be used in devices for microwave filtration of radio signals of cellular communication systems, satellite television, radar etc. In some cases, the invention enables to reduce total power consumption and realise a high-quality selective microwave device with f0=1-5 GHz. To this end, the selective amplifier has a signal source (1) connected to the input (2) of the device, a first (3) input transistor, whose collector is connected through a first (4) current-stabilising two-terminal device to the first (5) power supply bus and the input of an additional current mirror (6), the current output of which is connected through a first (7) frequency-setting resistor to the first (5) power supply bus, a first (8) balancing capacitor, connected through alternating current in parallel to the first (7) frequency-setting resistor, a second (9) current-stabilising two-terminal device, connected between the emitter of the first (3) input transistor and the second (10) power supply bus, a second (11) input transistor. Between the emitter of the first (3) and second (11) input transistors, there are series-connected second (12) balancing capacitor and second (13) frequency-setting resistor, the base of the second (11) input transistor is connected to the input (2) of the device, the collector is connected to the first (5) power supply bus, and the emitter is connected to the second (10) power supply bus through a third (14) current-stabilising two-terminal device, wherein a voltage repeater is connected between the output of the device and the base of the first (3) input transistor.
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Selective amplifier / 2468498
Selective amplifier has a signal source (1), a first input transistor (2), a first current stabilising two-terminal device (3), a first power supply bus (4), a second power supply bus (5), a second input transistor (6), a first load resistor (7), a second current stabilising two-terminal device (8), a first balancing capacitor (9), a first frequency setting resistor (10), a second balancing capacitor (11), a third input transistor (12), a fourth input transistor (13), a third current stabilising two-terminal device (14), a fifth input transistor (15) base, a voltage source (16), a fourth current stabilising two-terminal device (17), a third balancing capacitor (18).
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FIELD: radio engineering, communication.
SUBSTANCE: complementary differential amplifier with an expanded active operation range comprises a first (1) and a second (2) input transistor, inputs (3), (4) of the device, a first (5) and a second (6) output transistor, a reference current source (7), a first (8) and a second (9) current-limiting resistor, first (10) and second (11) series-connected auxiliary resistors, an auxiliary forward-biased p-n junction (12), a common node (13), a first group of antiphase current outputs (14, 15), a second group of antiphase current outputs (16, 17), an emitter p-n junction of an additional transistor (18), a power supply bus (19).
EFFECT: wider active operation range of the input stage of the operational amplifier for a differential signal and obtaining limiting voltage values of the transfer characteristic thereof.
2 cl, 11 dwg
The invention relates to the field of radio engineering and communication and can be used as a device to gain analog signals with a wide dynamic range, in the structure of analog chips of different functional purposes (for example, high-speed operational amplifiers (op amps), multidifferential OS and RC-filters based on them).
Known schemes complementary input stages OS, made in the form of differential amplifiers (DU) on the n-p-n and p-n-p transistors with the so-called "architecture of input bandwidth operational amplifier a" [1-30]. On their modifications issued more than 50 patents for the leading microelectronic companies of the world. Differential amplifiers of this class, along with the model of parallel-balanced cascade [29-31], became the main amplification part of many analog interfaces. This is because in such remote control input capacitance is minimized due to the lack of effect Miller. The present invention relates to this subclass devices.
The closest prototype (1) the claimed device is complementary differential amplifier for patent US 4.429.284, fig.2, containing the first 1 and 2 second input transistors, databases which are relevant inputs 3, 4 devices, the first 5 and 6 second output transistors, the bases of which are connected with the reference current 7, the first 8 and 9 second current-limiting resistors connected between the relevant emitters 1 first input and to the first 5 output transistors, and the second 2-input and second 6 output transistors, the first 10 and 11 second serial connected auxiliary resistors connected between the emitters 1 first and second 2 input transistors, auxiliary pramosone p-p transition 12 included between bases of the first 5 and 6 second output transistors and common node of 13 consecutive first 10 and 11 second auxiliary resistors, the first group phase with current outputs (14, 15)associated with the collectors of the first 5 and 6 second input transistors, the second group phase with current outputs (16, 17)associated with collectors 1 first and second 6 output transistors.
A significant disadvantage remote control is that it has a relatively narrow dynamic range (U gr ) linear differential (U who <U g ≈100 to 150 mW). As shown in the monograph authors of this application [31], and this fact is the main cause of low performance of modern op amps, due to the nonlinear mode input stage of the shelter. However for the majority of the OS with high impedance node and one correction capacitor (C ) the maximum slew rate output voltage is determined by the formula [31] * in s x = 2 PI f with R U g g R , ( 1 )
where f cp is the unity gain frequency (cut-off frequency) adjusted OS;
U gr - voltage limits passing characteristics i o =f(u of I ) input stage (for the classical do U g =50% to 100 mW).
From (1) that there is increasing * o can be done in two different ways [31]:
1. The increase of the range of active work input DN (U, g ) without changing the slope of the conversion of the input voltage at output currents do;
2. The increase f cp by improving the frequency properties of transistors that is connected, first of all, using higher frequency and costly process (SG25VD, SG251, SG25R and others).
Declare input cascade OS solves the problem of increasing performance by increasing (without changing the steepness) of linear range of work in the input stage, the measured voltage limit U g =0.4% to 0,8 Century
In addition, we offer do quite effective in multidifferential shelter, where input stages requires a fairly wide range of line work, as well as in RC-filters, low harmonic distortion.
Thus, the main task of the invention consists in expanding the range of active work in the input stage of the shelter for differential signal - receiving boundary stresses his passing characteristics i o =f(u of I ) at the level of U gr =0.4% to 0,8 Century
The task is achieved that complementary differential amplifier with an extended range of active work containing the first 1 and 2 second input transistors, databases which are relevant inputs 3, 4 devices, the first 5 and 6 second output transistors, the bases of which are connected with the reference current 7, the first 8 and 9 second current-limiting resistors connected between the relevant emitters 1 first input and to the first 5 output transistors, and the second 2-input and second 6 output transistors, the first 10 and 11 second consistently connected auxiliary resistors connected between the emitters 1 first and second 2 input transistors, auxiliary pramosone p-n junction 12, included in the bases of the first 5 and 6 second output transistors and common node of 13 consecutive first 10 and 11 second auxiliary resistors, the first group phase with current outputs (14, 15)associated with the collectors of the first 1 and 2 second input transistors, the second group phase with current outputs (16, 17)associated with the collectors of the first 5 and 6 second output transistors, provided new elements and communication - as a subsidiary promomaster p-n junction 12 is used emitter junction of the additional transistor 18, collector which is connected with the bus 19 to the power source.
The amplifier circuit prototype presented on the drawing figure 1. On the drawing figure 2 shows the proposed device in accordance with the formula of the invention.
Drawing 3 shows the typical architecture for high-speed operational amplifier.
On the drawing figure 4 shows the scheme do prototype in the environment of computer modeling PSpise on models of integrated transistors FGUP NPP "pulsar".
The drawing is 5 - 6 the dependences of the output currents do figure 4 from the input voltage for various values of the resistance of the resistor R i R i =R 8 =R 9 =R 10 =20 MD - 5 and R i =200 Ohm - 6.
On the drawing 7 shows the scheme of the claimed Doo 2 in the environment of computer modeling PSpise on models of integrated transistors FGUP NPP "pulsar".
The drawings Fig - Fig.9 shows the dependence of the output current from the input voltage DN 7 for different values of the resistors R 0 termination 20 included in the emitter transistor 18.
The drawings figure 10 - 11 shows the dependence of the difference of output currents do to the input voltage u I do Fig.7 for different values of the resistors R 0 termination 20.
Complementary differential amplifier with an extended range of active work 2 1 contains the first and second 2 input transistors, databases which are relevant inputs 3, 4 devices, the first 5 and 6 second output transistors, the bases of which are connected with the reference current 7, the first 8 and 9 second current-limiting resistors connected between the relevant emitters first 1 input and the first 5 output transistors, and the second 2-input and second 6 output transistors, the first 10 and 11 second serial connected auxiliary resistors connected between the emitters 1 first and second 2 input transistors, auxiliary pramosone p-n junction 12, included in the bases of the first 5 and 6 second output transistors and common node of 13 consecutive first 10 and 11 second auxiliary resistors, the first group phase with current outputs (14, 15)associated with the collectors of the first 1 and 2 second input transistors, the second group counter-current outputs (16, 17)associated with the collectors of the first 5 and 6 second output transistors. As a subsidiary promomaster p-n junction 12 is used emitter junction of the additional transistor 18, collector which is connected with the bus 19 to the power source.
On the drawing figure 3 declare differential amplifier figure 2 (21) included in the classical structure of a fast OS with high-impedance node 22, which contains additional current mirrors 23, 24, output buffer 25 and correction capacitor (C ) 26. This OS is covered 100% negative feedback. Its power supply is provided by the sources, on 27 and 28.
The drawing of figure 2, in accordance with claim 2, consistently with the emitter of the p-n junction of the additional transistor 18 included the termination resistor 20.
Let us first consider the work of the known device figure 1.
Static current all transistor circuit are determined by the current I 7 ecostability of two-terminal 7. However, for a fairly low-Ohm resistors 8, 10, 11, 9 (R 8 =R 10 =R 11 =R 9 =R=1015 Ohm) due to increase of the areas emitter transitions transistors 5, 6 may at zero input voltage DN (U BX =0) to ensure the equality of all the emitter circuit currents: I E. 1 = I E. 2 = I E. 5 = I E. 6 ≈ I 0 , ( 2 )
where 2I 0 =I 7 - some reference current, for example 1 mA.
On the basis of the Kirchhoff equations with U I =0 can write the following equation U E. b .5 + I E. 5 R 8 = I 0 R 10 + U d , ( 3 ) U E. b .6 + I E. 6 R 9 = I 0 R 11 + U d , ( 4 )
U d =U AB =B 0,7 - voltage dvuhyarusnaya 12 (auxiliary promosnastka p-n junction),
i E. 5 ≈ u C B R 8 = R 10 R 8 u in x R 10 + R 11 , ( 12 ) i E. 5 ( t ) = I 0 U 10 R 8 + R 10 R 8 u in x R 10 + R 11 . ( 13 )
Similarly for emitter current output transistor 6 i E. 6 ( t ) = I 0 R 11 R 9 - R 11 R 9 u in x R 10 + R 11 . ( 14 )
Transistor 6 fully closed, if i a (t)were 0, i.e. when U in x = U in x . g R = ( R 10 + R 11 ) I 0 = 2 R 10 I 0 = 2 R 11 I 0 = 2 R 8 I 0 = 2 R 9 I 0 . ( 15 )
Given that the R8 and R9, significantly influence the steepness S I pass characteristics do i, o =f(u I ), can not get large, from (15) that at a fixed slope S I considered scheme 1 cannot ensure proportionality output currents from the u of I in a wide range of changes, u of I , and the steepness S in x ≈ R 8 - 1 + [ h 11.1 b + h 11.5 b ] - 1 , ( 16 ) where h 11.1 b , h 11.5 b
- h-parameters of transistors 1 and 5 in the diagram with a common base. Maximum output currents do not exceed the value
I KMF =I KMF =0 2I , I KMF =I KMF =4I 0 . Therefore, DN 1 operates in the mode of "a"class for which output currents are rigidly connected with the total static shock, do consumed from the power source. This is one of the major drawbacks do prototype.
Let us further consider the scheme of the claimed Doo 2.
Static mode transistor circuit in figure 2 R 10 =R 11 ≤1 K U I =0, are described by the following system of equations of Kirchhoff U E. b .5 + I E. 5 R 8 = U E. b .18 + I 0 R 0 , ( 17 ) U E. b .6 + I E. 6 R 9 = U E. b .18 + I 0 R 0 , ( 18 )
where R 0 - resistor 20.
Considering that U AB ≈0.7 V, you can find static (U BX =0) emitter current all major (1, 2, 5, 6) transistor circuits I E. 5 = I 0 R 0 R 8 = I E. 1 , ( 19 ) I E. 6 = I 0 R 0 R 9 I E. 2 . ( 20 )
In future we shall assume, for example, that R 0 =R 8 =R 9 =10% to 20 Ohm. If the input VH served positive voltage u of I , the current through the resistor 10% to 11 incremented i R , which generates a resistor 10 "unlocking" transistor 5 and resistor 11 "locking" transistor 6 stresses that cause corresponding changes collector currents of these transistors. So for the left part of the scheme Doo 2 i to 1 ≈ i to 5 = R 10 u in x R 8 ( R 10 + R 11 ) ≈ u in x R 8 ( 1 + R 11 R 10 ) ≈ u in x 2 R 8 . ( 21 )
This transistors 6 and 2 "podupirati"as their collector currents are reduced by the amount i to 2 ≈ i to 6 ≈ u in x 2 R 9 . ( 22 )
Full locking transistors 2, 6 (I K3 =0, I K6 =0) will occur when the input threshold voltage u in x = U g R = 0,7 ( 1 + R 10 R 11 ) ≈ 1,4 B . ( 23 )
So when u I =U g maximum output currents do reached values i to 1. max = i to 5. max = 0,35 R 8 ( 1 + R 10 R 11 ) ≈ 0,7 R 8 B . ( 24 )
if R 8 =R 9 =10 OHM, then i KMF =i CMO ≈70 mA.
Practical value of i KMF =i kmh (Fig.9) differ from the calculated according to the formula (24) due to the influence of resistance 10, 11 and gain current base β 18 transistor 18 to work scheme. In addition, when more accurate calculations should take into account that the actual locking transistors 5 (6) occurs not when U DL =0, and when U DL ≈0,5 C. As a result, R10=R11=1 ohms maximum currents i CMO , i CMO somewhat less calculated by the formula (24).
Thus, Doo 2 works as a cascade of class "b" - its maximum output currents significantly exceed the static current transistors, which, along with higher value U gr is its significant advantage.
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1. Complementary differential amplifier with an extended range of active work containing the first (1) and second (2) of the input transistors, databases which are relevant inputs (3), (4) devices, the first (5) and the second (6) the output transistors, the bases of which are connected with the reference current (7), first (8) and second (9) current-limiting resistors connected between the relevant emitters first (1) of the input first and (5) of the output transistors, and the second (2) of the input, and the second (6) the output transistors, the first (10) and the second (11) consistently United auxiliary resistors connected between the emitters of the first (1) and second (2) of the input transistors, auxiliary pramosone p-n junction (12)included in the bases of the first (5) and the second (6) output transistors and shared host (13) connected in series the first (10) and the second (11) the subsidiary resistors, the first group phase with current outputs (14, 15)associated with the collectors of the first (1) and second (2) input transistors, the second group phase with current outputs (16, 17), associated with the collectors of the first (5) and the second (6) output transistor, notable as a subsidiary promomaster p-n junction (12) used by the emitter junction of the additional transistor (18), the collector which is connected with the bus (19) power supply.
2. Complementary differential amplifier with an extended range of active work according to claim 1, characterized in that series with the emitter of the p-n junction of the additional transistor (18) included the termination resistor (20).
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