Differential operational amplifier with passive parallel channel

FIELD: radio engineering, communication.

SUBSTANCE: differential operational amplifier with a passive parallel channel comprises two input transistors, two output transistors which are junction gate field-effect transistors, a non-inverting stage and a controlled current source.

EFFECT: reducing the magnitude of the systematic component of the zero bias voltage and temperature and radiation drift thereof.

2 cl, 9 dwg

The invention relates to the field of radio engineering and communication and can be used as a device for the amplification of analog signals, in the structure of the analog circuits of various functional purposes (e.g., photodetector devices, computing amplifiers with small values of the input conductivity).

In modern electronic equipment find application of differential operational amplifiers (op-amp) with a significant variety of settings. A special place is occupied by complementary chastnye OS [1-11]. These OS have a very simple structure and are characterized by low energy consumption.

The present invention relates to this class of devices.

The closest entity to the claimed technical solution is the classical scheme of differential shelter 1 is presented in U.S. patent No. 4.714.894, fig. 1, which is also present in a large number of other patents and monographs, for example, [12-18]. It contains the first 1 input transistor, the collector of which is connected with the first 2 bus power source, and a base connected to the first 3 not inverting input device, the first 4 output transistor, the emitter of which is connected with the emitter of the first 1 of the input transistor, and the collector is connected to reinvestiruet entrance 5 of the first 6 einverseremove cascade, consistent with the WTO is Oh 7 bus power source, the output of the device 8 connected to a current output 9 of the first 6 einverseremove cascade and is associated with the first 2 bus power source through a current source 10, 11 second input transistor, the base of which is connected with the first 12 inverting input device, and an emitter connected to the emitter 13 second output transistor.

A significant disadvantage of the known OS figure 1 is that he has increased the importance of the systematic component of the bias voltage of zero (U_cm), which is associated with the asymmetry of its architecture. In addition, known OS is characterized by only two inputs, so you cannot relate it to the subclass multidifferential OS.

The main objective of the present invention is to reduce the absolute value of U_cmand its temperature and radiation drift.

An additional goal is to increase the number of differential inputs of the shelter.

This object is achieved in that the operational amplifier 1, 1 containing the first input transistor, the collector of which is connected with the first 2 bus power source, and a base connected to the first 3 not inverting input device, the first 4 output transistor, the emitter of which is connected with the emitter of the first 1 of the input transistor, and the collector is connected to reinvestiruet entrance 5 of the first 6 einverseremove cascade is, consistent with the second 7 bus power supply, the output device 8 connected to a current output 9 of the first 6 einverseremove cascade and is associated with the first 2 bus power source through a current source 10, 11 second input transistor, the base of which is connected with the first 12 inverting input device, and an emitter connected to the emitter 13 second output transistor, there are new elements and relationships - as the first 4 and 13 second output transistors are field-effect transistors with a control p-n junction, the gates which correspond to the bases, the origins of the emitters and sinks to the collectors of transistors, gate the second 13 output transistor connected to the second 14 reinvestiruet input device, and a drain connected to the second 7 bus power supply, the gate of the first 4 output transistor connected to the second 15 inverting input device, and the current source 10 is controlled current source, a non-inverting control input 16 which is connected to the collector of the second 11 of the input transistor.

The amplifier circuit of the prototype shown in the drawing figure 1. In the drawing figure 2 presents the diagram of the inventive device in accordance with claim 1 and claim 2.

In the drawing figure 3 shows the diagram of figure 2 with the specific implementation of the first 6 einverseremove cascade and manageable what about the power source 10.

In the drawing figure 4 shows the diagram of figure 2 with another variant of execution of the first 6 einverseremove cascade and the controlled current source 10.

In the drawing figure 5 presents the amplifier circuit 3 in the environment PSpice models of integrated transistors ABMC.

Drawing 6 shows the temperature dependence of the voltage offset of the operational amplifier 5.

In the drawing 7 shows the amplifier circuit 3 in the environment PSpice models of bipolar transistors FGUP NPP pulsar and field-effect transistors ABMC with a specific implementation of the buffer amplifier 24.

In the drawing Fig presents the temperature dependence of the voltage zero offset OS Fig.7 and Fig.9 drawing - logarithmic amplitude-frequency characteristic of the open OS 7.

Differential operational amplifier with passive parallel channel 2 1 contains the first input transistor, the collector of which is connected with the first 2 bus power source, and a base connected to the first 3 not inverting input device, the first 4 output transistor, the emitter of which is connected with the emitter of the first 1 of the input transistor, and the collector is connected to reinvestiruet entrance 5 of the first 6 einverseremove cascade, consistent with the second 7 bus power supply, the output device 8 connected to a current output 9 of the first 6 reinverting the th cascade and is associated with the first 2 bus power source through a current source 10, the second 11 input transistor, the base of which is connected with the first 12 inverting input device, and an emitter connected to the emitter 13 second output transistor. As the first 4 and 13 second output transistors are field-effect transistors with a control p-n junction, the gates which correspond to the bases, the origins of the emitters and sinks to the collectors of transistors, the gate 13 second output transistor connected to the second 14 reinvestiruet input device, and a drain connected to the second 7 bus power supply, the gate of the first 4 output transistor connected to the second 15 inverting input device, and the current source 10 is controlled current source, a non-inverting control input 16 which is connected to the collector of the second 11 of the input transistor.

In the drawing figure 3, in accordance with claim 2, the base 1 of the input transistor and the gate of the first 4 output transistor connected to a common bus power supply 17. This controlled current source 10 is implemented on the basis of dvukhpolosnykh 18, the transistor 19 and the circuit bias potentials 20, and the first 6 non-inverting stage is executed on the transistor 21, the circuit bias potential 22 and dvukhpolosnykh 23.

In the drawing figure 4 controlled current source 10 is implemented on the basis of the p-n junction 26, the transistors 27 and 28, and the first is th 6 non-inverting stage is executed on the transistor 29, the p-n junction 30 and the transistor 31 and the resistor 32. The circuit also includes a buffer amplifier 33, the output of which 34 is the output device.

Consider the factors that determine the systematic component of the bias voltage of zero U_CMin the scheme of figure 2, i.e. depending on the circuitry of the shelter.

The currents of the source and drain of field-effect transistors 4 and 13 (I_And=I_With=I₀depend on the steepness of their statesattorney characteristics when U_si=U_si≈0,7 Century Under identical p-n junctions of the first 1 and 11 second input transistors, and an identical field-effect transistors 13 and 4, the collector current of the transistor 11 and the current source transistor 4 will be equal to the value of I₀. Therefore, when zero differential current at the output node 8, the bias voltage of zero U_cmconsider shelter close to zero

$$U\mathrm{with\; a}m=U_{eb.11}-U_{C\mathrm{and}.13}\approx \mathrm{0,}\text{(1)}$$

as

$$\begin{array}{l}{U}_{eb.4}=U_{eb.1},\\ U_{\mathrm{the}b.11}=U_{eb.1},\text{(2)}\\ U_{e\mathrm{and}.4}=U_{C\mathrm{and}.13}\text{.}\end{array}$$

Thus, in the present scheme provides a small bias voltage of zero.

The differential gain voltage declare Doo 2:

$$K_y=\frac{u_{\mathrm{in}sx.8}}{u_{\mathrm{in}x.1}-u_{\mathrm{in}x.2}}=\frac{u_{\mathrm{in}sx.8}}{u_{\mathrm{in}x\mathrm{.1.2}}}\approx \frac{R_{n.eK\mathrm{in}}}{r_{e11}+S_{13}^{-1}},\text{(3)}$$

where $$r_{e11}\approx \frac{{\phi }_t}{I_0}$$- resistance emiterio transfer transistor 11;

S₁₃- slope statesattorney characteristics of field-effect transistor 13;

φ_T=26 mV - temperature capacity;

R_naquequivalent load resistance of the shelter connected to the output 8.

When the temperature (or radiation) changes the drain current of the transistor 13. However, just as well (due to the symmetry of the emitter circuits of transistors 11 and 1) changes the current source transistor 4 and the collector current of the transistor 11, which is transmitted to the output node 8 and compensate each other. In the U_cmscheme 2 changes slightly.

Thus, in the inventive device, in connection with the symmetry of the circuit decreases the systematic component of the bias voltage of zero U_CMand his drift.

In accordance with claim 2, inputs 3 and 15 can sometimes not be used. In this case, the transistors 1 and 4 form the passive channel, which is not involved in the transmission of the input signal (U_I=U_WH-U_WH) and serves only to compensate for the voltage offset of the shelter. However, compensation U_cmeven if the use of the Finance inputs 3 and 15 for connection to other input to the voltage control which becomes multidifferential amplifier.

Thus, the proposed device can have 4 inputs, has significant advantages in comparison with the prototype largest static error amplification signal DC and can be used as IP modules of modern systems-on-chip implemented, for example, technology analog base matrix crystals ABMC.

BIBLIOGRAPHIC LIST

1. U.S. patent No. 4.415.868 fig.3

2. the Federal Republic of Germany patent No. 2928841 fig.3

3. The Japan patent JP 54-34589, CL 98(5) a014 select the active portion

4. The Japan patent JP 154-10221, CL H03F 3/45

5. The Japan patent JP 54-102949, CL 98(5)A21

6. U.S. patent No. 4.366.442 fig. 2

7. U.S. patent No. 6.426.678

8. The patent application U.S. 2007/0152753 fig. 5

9. U.S. patent No. 6.531.920, fig.

And U.S. No. 4.262.261

11. Eskow Y.A. Reference circuitry of the amplifiers. - 2nd ed., Rev. - M: FE the Radiosoftware, 2002. - 272 S. - RIS (p.235).

12. Patent US 4.714.894 fig. 1

13. Patent US 6.492.871 fig. 3b, fig. 5

14. Patent US 4.749.958 fig. 2

15. Patent US 4.749.831

16. Patent US 6.249.153 fig. 9

17. Patent application US 2009/0033423

18. Patent SU 1283946.

1. Differential operational amplifier with passive parallel channel containing the first (1) of the input transistor, the collector of which is connected to the first (2) bus power source, and a base connected to the first (3) not inverting input device, the first (4) o the ne transistor, the emitter of which is connected with the emitter of the first (1) of the input transistor, and the collector is connected to reinvestiruet input (5) of the first (6) einverseremove cascade, consistent with the second (7) bus power supply, the output device (8)connected with a current output (9) of the first (6) einverseremove cascade and is associated with the first (2) bus power supply through a current source (10), second (11) of the input transistor, the base of which is connected with the first (12) inverting input device, and an emitter connected to the emitter of the second (13) of the output transistor, characterized in that the first (4) and second (13) output transistors are field-effect transistors with a control p-n junction, the gates which correspond to the bases, the origins of the emitters and sinks to the collectors of transistors, the second shutter (13) of the output transistor is connected with the second (14) reinvestiruet input device, and a drain connected to a second (7) bus power supply, the gate of the first (4) of the output transistor is connected with the second (15) inverting input device, and as a current source (10) used a controlled current source, a non-inverting control input (16) which is connected to the collector of the second (11) of the input transistor.

2. Differential operational amplifier with passive parallel channel according to claim 1, characterized in that the base PE the first (1) of the input transistor and the gate of the first (4) of the output transistor connected to a common bus power supply (17).