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IPC classes for russian patent Code frame synchronisation method (RU 2450436):
   
 Device of code cycle synchronisation with soft decisions / 2428801
Device comprises an information accumulator, circuits of unit borders detection, every of which comprises circuits of word borders and their numbers detection, every of which includes a unit of error detection, a unit of decoders and a unit of binary stage summators, the output of the error detection unit is connected to the input of the decoders unit, one of outputs in which is connected with the distributor input, and the other output of the decoders unit is connected to the input of binary stage summators unit, the summators unit output, being the output of the circuit for detection of word borders and their numbers, is connected to a circuit of numbers filtration, outputs of which are connected to inputs of a counters unit, other inputs of the counters unit are connected to outputs of distributors, the output of the counters unit is connected to the input of a threshold element, the outputs of the threshold elements are the outputs of the circuits for detection of unit borders and are connected to inputs of an assembly, the output of which is the output of the device for generation of signals on the end of each information unit. At the same time the information accumulator output is the information output of the device. The device includes a circuit that generates most probable error vectors, a unit of summators, a circuit of numbers filtration and an assembly circuit.
 Transmitter, receiver, mobile communication system and synchronisation channel transmission method / 2414073
Transmitter has a frame generating unit having OFDM symbols and a unit for transmitting the generated frame, wherein the generation unit deploys the main synchronisation channel for detecting the symbol synchronisation signal in the last OFDM symbol in the frame and an auxiliary synchronisation channel for frame detection during reception in an OFDM symbol preceding the last OFDM symbol.
Method of code cyclic synchronisation / 2401512
Proposed method consists in that accepted input sequence made up of several words coming one after another, each representing modulus digit-by-digit sum, of two noise-resistant cyclic codes, synchronising sequence and numbering sequence are multiplied by verification polynomial of noise-resistant cyclic code and by verification polynomial of numbering sequence to obtain the sum of syndrome of noise-resistant cyclic code and synchronising sequence. Then numbering sequence of accepted noise-resistant cyclic code is extracted and compared with numbering sequences of noise-resistant cyclic codes accepted earlier. The number of agreements of numbering sequences with those accepted earlier in one of F agreement counters. If numbering sequence agrees with numbering sequences accepted earlier, the number in appropriate agreement counter is increase by 1, and, if the number of agreements exceeds that written in appropriate counter of threshold value agreements, code cyclic synchronisation of input sequence is taken to result.
 Method for generation of digital broadcasting transport flow pack for improved efficiency of reception, digital broadcasting transmitting device and method of signals processing in it / 2391779
Method is proposed for generation of digital broadcasting transport flow pack, including formation of transport flow pack comprising filling area for insertion of available data of subsidiary reference sequence (SRS), randomisation of pack, which includes filling area, and SRS-data is inserted into filling area of randomised packet, addition of parity for correction of errors in pack, where SRS-data is inserted, pack, in which parity has been added, is alternating, and its trellis coding is carried out. Signal of segment synchronisation and signal of field synchronisation are inserted into pack produced by trellis coding, and modulation is carried out with vestigial sideband (VSB) and RF-transformation of pack for transfer of VSB-modulated and RF-transformed pack.
 Code cycle phasing device / 2383104
Code cycle phasing device relates to systems for transmitting discrete information and can be used for cycle phasing in noise-immune information security systems which use correcting codes, particularly factorable codes. The code cycle phasing device includes a decoder for confirmed words, a number multiplexer, a distributor and a counter unit. Signals on the end of each information unit are generated at the output of a threshold unit.
 Method for code cyclic synchronisation / 2359414
Invention is related to electric communication and is applicable for synchronisation of message sent by sequence of words of block turbo-code, in which component codes are binary cyclic codes of primitive lengths with generator polynomials having common divisor and expanded due to addition of verification for parity, under conditions of parametric uncertainty expressed in absence of any data on coder structure, excluding length of code word. Substance of code cyclic synchronisation method consists in the fact that discrete sequence of code word symbols is accepted with application of discrete information receiver. From received discrete sequence fragment is separated with length that is less than length of code word by one symbol, discrete Fourier Galois transform (DFGT) is carried out for this fragment, and synchronous condition of discrete information receiver is defined by availability of synchronous condition criterion. Criterion of synchronous condition of discrete information receiver is equality to zero of at least one spectral component in spectrum of separated fragment. In case of synchronisation absence prior to its establishment, synchronous condition is searched by means of serial shift by received sequence by one symbol into one and the same side with further separation of new fragment, its DFGT and determination of receiver synchronous condition availability by criterion of synchronous condition. After synchronous condition criterion has been detected, additionally synchronous condition establishment verity is confirmed by availability of phasing verity criterion. For this purpose at least four fragments of the same length are separated, which are serially installed downstream fragment selected at the stage of synchronous condition definition, at that beginning of another fragment is separated from the end of preceding fragment by one symbol of sequence, DFGT of additionally separated fragments is carried out, and phasing verity criterion availability is defined. Criterion for verity of phasing is nonempty crossing of multiple numbers of zero components in received spectra. In case phasing verity criterion is not available, searching of synchronous condition is restored from the moment of synchronous condition criterion detection.
 Device for cyclic synchronisation / 2348117
Invention is related to telecommunications and may be used in receiving devices of synchronisation by cycles of discrete messages transmission system. Device comprises identifier of sync pulse, adder, unit of shift registers, resolver, shaper of sync pulses, counter of cycles, comparator, finder of synchronism loss threshold, unit of undistorted sync pulses permissible number selection, counter of distorted sync pulses, counter of total number of sync pulses, trigger, counter of clock pulses, element AND, unit of threshold selection, signal input, clock input and device output. Identifier of sync signal comprises shift register, detector of errors in sync group, shaper of response weight for sync signal. Resolver comprises the first comparator, memory unit, subtraction unit, the second comparator, counter of comparison, the second element AND, the third element AND, element OR. At that exit from synchronism condition is determined, when number of accumulated responses at position of true sync signal in another test cycle will be less than threshold of synchronism loss. At that in case of true distortion of synchronism in cells that correspond to position of true sync signal, there is drastic reduction of sync signal identifier responses accumulation density observed, which makes it possible to faster determine condition of system exit from synchronism, which in its turn makes it possible to reduce time required for synchronism restoration.
 Method of code cyclic sync / 2342796
Method of code cyclic sync concerns field of telecommunication and can be used for cyclic sync of conferrings in systems of transmission of the discrete information in which are used correcting, in particular cascade codes. The essence of the invention consists that the accepted input sequence representing the total on the module two checkout parts of an unjammable code, numbering and synchronising sequences, multiply by a checkout multinominal of a code. As a result calculate the total of a syndrome of an unjammable code and numbering and synchronising sequences. Then on the total of a syndrome of an unjammable code and synchronising sequence spot a vector of errors and correct errors in numbering sequence. After that compare numbering and synchronising sequences with earlier accepted and gain certain number of coincidence of numbering and synchronising sequences with corresponding numbering and synchronising sequences before the accepted code words. Thus, if this number of coincidence exceeds some in advance given threshold value, make the solution on presence of cyclic sync. And input sequence break into groups on f figures (f>1) in each group and calculate the total of a syndrome of the unjammable code, numbering and synchronising sequences, and also spot a vector of errors and correct errors in numbering sequence in a series-parallel code by means of in advance calculated functional connections set in a tabular view.
Method of cyclic sync of blocks of information for range of fixed velocities of operation in communication channel / 2342795
Invention concerns communication technics, namely to expedients of cyclic sync of blocks of the information at synchronous expedients of transmission in a gamut of the fixed velocities of operation and self-acting operation of the receiver of telecode equipment without prestress installation of value of velocity of operation in a communication channel. At use of the receiver of the telecode information without prestress installation of velocity carry out parallel processing of signals of the code information sequences arriving from a communication channel with any velocity from a working range of the fixed velocities, N of devices of phase correction and recording (DPCR); after processing signals from everyone DPCR submit on inlets N of corresponding devices of cyclic sync (DCS) which parallelly carry out the analysis of input sequence with the subsequent record of signals of code information sequences in N operative storage devices (RAM). Thus on a signal of the cyclic sync, generated DCS, corresponding to velocity of signalling in a communication channel, information code sequence of signals at reading from corresponding to it DCS the RAM and a signal "an information Sign" from the corresponding block of guidance are switched by a mode "Record-reading" to an inlet of the decoder of the receiver of telecode equipment.
 Cyclic code synchronization method / 2319308
Cyclic code synchronization method includes receiving discrete series of code word symbols using a receiver of discrete information, a fragment of discrete series is extracted which has length equal to length of code word, discrete Fourier-Galois transform is performed over the fragment and presence of synchronous state of discrete information receiver is determined using synchronous state criterion. Synchronous state criterion for the discrete information receiver is the equality to zero of at least one spectral component in the spectrum of the extracted fragment. In case when synchronization is absent before it is established, synchronous state is found by means of successive shifting of received series for one symbol towards one and the same side with following extraction of a new fragment, its discrete Fourier-Galois transform and detection of receiver synchronous state presence based on the synchronous state criterion. After detection of synchronous state criterion, validity check of synchronous state establishment is additionally performed according to presence of phasing validity indication. For that purpose, at least four fragments of the same length are extracted, which are positioned serially after the fragment, extracted at the stage of synchronous state detection, discrete Fourier-Galois transform is performed over additionally selected fragments and presence of phasing validity indication is determined. As phasing validity indication, non-empty intersection of sets of zero component numbers in resulting spectrums is considered. In case when phasing validity indication is absent, the search for synchronous state is continued starting at the moment when synchronous state criterion is fulfilled.
 Code frame synchronisation method / 2450436
Code frame synchronisation method involves multiplication of a received input sequence consisting of several successive words by a noise-immune cyclic code verification polynomial and by a numerating sequence verification polynomial. Each word is a bitwise modulo 2 sum of the noise-immune cyclic code, a synchronising sequence and the numerating sequence. As a result, a synchronising sequence and noise-immune cyclic code syndrome sum is obtained, from which possible error vectors of the noise-immune cyclic code are determined beyond its error-correcting capability. The number of the numerating sequence is then determined, from which the possible end of the message block is determined for a threshold number of numbers. Each signal on the end of the message block is further checked for conformity with the true signal on the end of the message block through a message block decoding procedure and if the decoding result is positive, a final decision is made on code frame synchronisation of the message block.
 Device for group cycle synchronization / 2248677
Device has random access memory, adjusting device, synchronous combination decoder, phasing device, generator equipment, three commutators, signals distributor, time analyzer and signals remover.
 Device for cylce synchronization of data blocks / 2249920
Device has control circuit, first input of which is connected to output of phase sign decoder, second input is connected to first clock input of device, third input is connected to second clock input of device, circuit OR, connected by its inputs to outputs of controlled system, and output of OR circuit is connected to third block for forming cyclic phasing signal, while the latter is made on basis of same circuit of logic numbers processing and consists of two numbers signals switchboard, arithmetic adder of two numbers, memory device, meant for recording K numbers, on basis of K data words, required for forming of cycle synchronization signal, AND match circuit, decoder, pulse counter, performing function of threshold element.
 Frame synchronization device / 2256295
Proposed device is used for frame synchronization of digital time-division multiplex data transmission systems and incorporates provision for synchronizing data transmission class at dispersed sync combination of group signal and for implementing parallel search for synchronism. Device has first, second, and third random-access memories, storage register, decoder, distributor, generator equipment, phasing unit, flip-flop, first and second inverters, adjusting unit, first, second, and third inverters, first, second, third, fourth, and fifth AND gates, first and second OR gates.
 Adaptive code frame synchronization device / 2259638
Proposed device for adaptive code frame synchronization has delay register 1, error detection assembly 2, decoder unit 10, counter 11, threshold unit 21, synchronizing-sequence generator 18, modulo two output adder 12, random-access memory 15, modulo two adder unit 16, number comparison unit 13, full adder 19, synchronization counter 17, error counter 14, and code converter 20. Error detection assembly is set up of two series-connected Huffman filters 3, 4 and syndrome register; each Huffman filter has register 6/7 and modulo two adder 8/9.
 Device for synchronization by cycles / 2280956
Device contains synchronization signal recognition device, forbidding element, first AND element, adder, shift registers block, generator of clock pulses, OR element, cycles counter, counter of distorted synchronization signals, block for selecting allowed number of distorted synchronization signals, block for selecting threshold, block for selecting counting coefficient, counter by exit from synchronization status, and also solving assembly, containing first comparison block, memory block, subtraction block, second comparison block, comparison counter, second AND element, third AND element, second OR element.
 Device for cyclic synchronization / 2284665
Device contains synchronization signal recognition device, adder, block of shift registers, solving block, generator of cyclic impulses, counter of cycles, comparison block, counter of distorted synchronization impulses, counter of total number of synchronization impulses, AND element, counter of clock impulses, trigger, block for selecting maximal weight of response, threshold selection block, second threshold selection block, block for selection of counting coefficient, signal input, clock input and output of device. Synchronization signal recognition device contains shift register, detector of errors in synchronization group, generator of weight of response to synchronization signal. Solving block contains comparison block, memory block, subtraction block, comparison block, comparison counter, second AND element, third AND element, OR element. By means of second element AND, third element AND, and also element OR in synchronous mode, and also in case of synchronism failure, generation of synchronization signal is performed at output of solving block. Restoration of synchronism after failure and phasing of device for new position of cyclic synchronism is performed in case of occurrence of two events simultaneously: determining of new position of cyclic synchronization signal by solving block and detection of failure of cyclic synchronism by means of cycles counter, comparison block, threshold selection block and count coefficient selection block, because during regular repeating at certain information position of cycle of false synchronization group and random distortion of true synchronization group phase of cyclic impulse generator does not alter, thus causing no false synchronism failure.
 Device for cyclic synchronization / 2286020
Known device contains random-access memory device, adjustment and diagnostics device, phasing device and generator equipment. Cyclic evenness determining device is introduced to known device. Therefore, cyclic synchronization device provides cyclic synchronization of different digital transmissions, wherein synchronous combination is absent, while on positions at the end of cycle signals are transferred, filling sum of signals of appropriate digital transmission up to evenness.
 Code cyclic synchronization method / 2295198
In accordance to method, at transferring side one synchronization series is selected for N code words following one another, check section of code words is added with modulus two to appropriate section of aforementioned synchronization series. At receiving side received input series, consisting of several code words following each other, is divided onto original interference-resistant cyclic codes polynomial, producing a total of interference-resistant cyclic codes syndrome and synchronization series. By subtracting synchronization series from produced total, interference-resistant cyclic codes syndrome is selected. On basis of interference-resistant cyclic codes syndrome combination of errors in interference-resistant cyclic codes is computed and its weight is evaluated. On basis of error combination weight, trustworthiness degrees of code words following each other are computed. If total trustworthiness degree exceeds threshold value, decision about performing code cyclic synchronization of input series is taken.
 Method and device for accelerated search of broadband signal / 2297722
Proposed method intended for use where reception of extended-spectrum data signals keyed by simulation-resistant pseudorandom nonlinear derivative sequences is always preceded by synchronization includes concurrent accumulation of periodic mutually correlated function values of signal segments arriving from output of dynamically matched adjustable filters with two standard sampling lines affording generation of random derivative, as well as determination of time step numbers of their mutual shift corresponding to delay synchronism. Then current delay of entire signal being received is found from combination of these time step numbers. Used as dynamically matched adjustable filters in search channels are acousto-electronic convolvers.
 Frame synchronization method / 2298879
Proposed method includes sequential search at single-bit shift, identification of concentrated sync groups in group digital stream, and formation of responses when identifying concentration sync groups on tested clock intervals, and measurement of time intervals between sequential moments of responses across concentrated sync group identifier in terms of clock intervals. Primary sample of N ≥ 3 time intervals is accumulated. Secondary samples of time intervals between moments of first, second, through (N + 1)th reference responses, respectively, and arrival moments of all other primary-sample responses are calculated. Maximal common dividers of probable combinations of two or more time intervals are calculated and particular lines (spectrums) of distribution of maximal common dividers whose values exceed lower boundary of region of probable group signal cycle lengths are formed in the framework of secondary time interval samples. Integrated spectrum of maximal common divider values is formed by summing up all particular maximal common divider spectrums. Regular sequence of true integrated sync group responses is detected by fact of coincidence of maximal common dividers in integrated spectrum whose quantity exceeds desired threshold, and coincidence point abscissa of maximal common dividers is assumed as cycle length. True concentrated sync group responses are identified in primary implementation of stream by serial numbers of particular maximal common divider spectrums wherein we see multiple coincidences of maximal common dividers with found cycle length. Clock interval of group-signal next cycles commencement is predicted. Concentrated sync group responses appearing at predicted clock intervals are assumed as frame synchronization pulses. Decision on input in and output from frame synchronization mode is taken by composite "k/m-r" criterion.
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FIELD: information technology. SUBSTANCE: code frame synchronisation method involves multiplication of a received input sequence consisting of several successive words by a noise-immune cyclic code verification polynomial and by a numerating sequence verification polynomial. Each word is a bitwise modulo 2 sum of the noise-immune cyclic code, a synchronising sequence and the numerating sequence. As a result, a synchronising sequence and noise-immune cyclic code syndrome sum is obtained, from which possible error vectors of the noise-immune cyclic code are determined beyond its error-correcting capability. The number of the numerating sequence is then determined, from which the possible end of the message block is determined for a threshold number of numbers. Each signal on the end of the message block is further checked for conformity with the true signal on the end of the message block through a message block decoding procedure and if the decoding result is positive, a final decision is made on code frame synchronisation of the message block. EFFECT: high reliability of received information in high-noise level channels. 3 cl
The invention relates to systems for the transmission of discrete data and can be used for frame synchronization in systems robust data protection that apply corrective, in particular, concatenated codes. In the device code frame synchronization clock characteristics are passed on words of error-correcting code. For synchronization are testing the code symbols and the transmission of additional synchronization symbols is not required. After receiving information signs synchronization are removed from the error-correcting code, and correcting ability of the code is not reduced. The most effective use of the code frame synchronization in the cascade codes. In this case, synchronization is provided by multiple repetition of signs synchronization in different words internal code cascade code. When developing methods code frame synchronization urgent task is to increase the reliability of the received information in the communication channels with high noise level. The proposed method code frame synchronization provides increased reliability of the received information in the communication channels with high noise level. The known method code frame synchronization, namely, that the accepted input sequence is alnost, consisting of several consecutive words, each of which represents a bitwise sum modulo two error-correcting cyclic code, synchronizing sequence and numbering sequence, first multiply by the check polynomial of error-correcting cyclic code. In the result of the multiplication is get the sum of the syndrome of error-correcting cyclic code, synchronizing sequence and numbering sequence. Then, the resulting amount is multiplied by the check polynomial numbering sequence and get the sum of the syndrome of error-correcting cyclic code and a synchronization sequence. Of this amount, subtract the synchronization sequence and receive the syndrome of error-correcting cyclic code. Further, if the syndrome of error-correcting cyclic code corresponds to a valid combination of errors, allocate numbering sequence of the received error-correcting cyclic code and compare it with the numbering sequence of the previously received error-correcting cyclic codes. In case of exceeding the threshold number of matches numbering sequence shall decide on the code frame synchronization input sequence [RF Patent №2210870 IPC 7 H04L 7/08. Semigin D.A., Kvashennikov CENTURIES, lepuhin F. W. Method of adaptive coded frame synchronization, prior. 09.08.2001, publ. 20.08.2003]. This way the code frame synchronization is not designed for operation in channels with a high level of noise, as when synchronizing in this manner, the permissible number of errors in words is limited to correcting ability of the code. Closest to the proposed method is a method code frame synchronization (prototype), namely, that the accepted input sequence consisting of several consecutive words, each of which represents a bitwise sum modulo two error-correcting cyclic code, synchronizing sequence and numbering sequence, first multiply by the check polynomial of error-correcting cyclic code. In the result of the multiplication is get the sum of the syndrome of error-correcting cyclic code, synchronizing sequence and numbering sequence. Then, the resulting amount is multiplied by the check polynomial numbering sequence and get the sum of the syndrome of error-correcting cyclic code and a synchronization sequence. Next, the sum of the syndrome of error-correcting cyclic code and a synchronization sequence and determine the possible error noise immune cyclic the ski code and beyond its remedial abilities. Then possible for the error vector by the sum of the syndrome of error-correcting cyclic code, synchronizing sequence and numbering sequence of the numbers numbering sequence. If these numbers correspond predetermined threshold length chains of numbers numbering sequence, you can determine the end of the message block. To determine the boundary of block messages are typically used counters block counters. The block counter consists of a set of series-connected counters of two types. Factor account of the first counter corresponds to the length of the BCH code word and the second counter counts the number of these words until the end of the message block. The ratio of the accounts of these two counters corresponds to the length of the message block. To the clock input of block counter is the frequency corresponding to the speed of receiving information from a channel. The outputs of the block counter, when the counter has reached the end, signals are formed about the end of the message block, which is fed to the input of the threshold unit. For a given threshold length chains of numbers numbering sequence at the output of the threshold block is the signal for the end of the message block [Yourmachine, Sairusi. Cycle timing for transmission of the messages in channels of low quality. Scientific and technical journal. Systems and means of communication, television and radio. Issue 1, 2, 2008, str-160]. The disadvantage of this method code frame synchronization is the lack of reliability of the received information in the communication channels with high noise level due to the lack of opportunities to simultaneously reduce both the likelihood of rasinhronizatsiey message blocks, and the probability of false synchronization message blocks. The purpose of the invention is to increase the reliability of the received information for the method code frame synchronization and, as a consequence, the possibility of its operation in channels with high noise level. To achieve the goal proposed method code frame synchronization, namely, that the accepted input sequence consisting of several consecutive words, each of which represents a bitwise sum modulo two error-correcting cyclic code, synchronizing sequence and numbering sequence, first multiply by the check polynomial of error-correcting cyclic code. In the result of the multiplication is get the sum of the syndrome of error-correcting cyclic code, synchronizing sequence and numbering sequence. Then, the resulting sum of the syndrome is multiplied by a test is Olya numbering sequence and get the sum of the syndrome of error-correcting cyclic code and a synchronization sequence. On this syndrome and determine the possible vector error error correcting cyclic code, and beyond its remedial abilities. Further for a possible vector of errors and known syndrome synchronizing sequence define the number numbering sequence and to determine the boundaries of the block messages trigger the corresponding counter unit counter. The block counter consists of a set of series-connected counters of two types. Factor account of the first counter corresponds to the length of the code word and the second counter counts the number of these words until the end of the message block. The ratio of the accounts of these two counters corresponds to the length of the message block. To the clock input of block counter is the frequency corresponding to the speed of receiving information from a channel. In block counters at the end of each counter at its outputs signals are formed about the end of the message block, which is fed to the input of the threshold unit. At the output of the threshold block is the signal for the end of the message block. Characteristics the majority of the schema element threshold block are selected in such a way as to ensure a high probability of correct frame synchronization for a specific channel. What's new is that each signal the end of a message block additionally check what is the procedure of decoding according to the true signal the end of a message block. For the identified false signals about the end of the message block further procedure of information processing is not carried out, and the whole procedure of data processing is carried out only for the true signal about the end of the message block. The functioning of the proposed method code frame synchronization consider the example of a frame synchronization error correcting cascade code. On the transmission side as the output information is formed by a sequence of c1⊕c2i⊕c3nrepresenting the bitwise sum modulo two of the three sequences: sequence internal binary cascade code c1, numbering binary sequence c2i=c21c22c23...c2nand synchronizing sequence c3n=C3with3with3...with3violating the cyclical properties of the source and consisting of repeating cyclic sequences, where n is the number of code words of Bose-Roy-Chaudhury-Hocquenghem (BCH). To obtain the sequence c1on the transmitting side of the original information amount k m-ary (m>1) characters encoded m-ary error-correcting code, such as m-ary error-correcting code is a reed-Solomon (PC). Code PC is the external code or code first stage of error-correcting ka is odnogo code. As a result of such encoding the original information is a block of code words PC (n, k), the information length k is equal to the word PC and block - n characters. The next block of information consisting of code words PC, encoded binary code, such as binary BCH code with the check polynomial h1(x). Code BCH is an internal code or code of the second stage of error-correcting cascade code. The word BCH code has the following parameters: n1- block code length, k1information code length. A coding block of code words PC code BCH receive a block of n binary words BCH code (n1, k1), which is a sequence of c1. Then the BCH code word are summed modulo two numbering sequence c2i. As the numbering sequence select binary code with block length n1and information length of k2for example, the code of the reed-Muller (RM) first order (sequence maximum period) with the check polynomial h2(x). Information length of k2code RM corresponds to the binary representation of numbers, words BCH. Between the numbers of code words in concatenated BCH code and an information part numbering sequence is set one-to-one correspondence. The first word of the BCH code added by mod the Liu two sequence, the resulting encoding binary representation of the first number of the code word BCH code of the Republic of Moldova, the second BCH code word is added modulo two and a sequence obtained by encoding a binary write of the second code word BCH code of the Republic of Moldova and so on. This operation is the summation runs over all words BCH code. If the check polynomial h1(x) and h2(x) is summable BCH codes and the Republic of Moldova and are coprime divisors of binomial xn1+1, the resulting sum will be obtained n words cyclic BCH code with length n1and an information length of k1+k2. This code will correct errors, including e≤r/log2(n1+1), where r=n1-k1-k2- the number of check symbols of the code. The third sequence with3which summarizes the BCH code word will be a constant sequence of length n1bits for all words. Such a sequence may be any sequence that is not a code word BCH code, for example, a sequence of 10000...000. In real channels and interference, which can be viewed as a sequence of c4the presence of units which corresponds to the location of errors in words. For correct word sequence c4contains only zeros. Information which I as a sequence of c 1⊕c2i⊕c3n⊕c4formed of four sequences, is supplied to the information input of the receiver. This sequence is recorded in the drive information and simultaneously fed to the input node of the error detection, consisting of two series-connected first filter and the second filter Huffman and register syndrome. In the drive information sequence is recorded in one of the two RAM until the threshold block is not determined to be the end of the block of words BCH, after which the control circuit of the drive will start recording in the other RAM further information, and from the previous RAM will start reading data for further operations processing and decoding. The use of storage media that contains two RAM allows you to apply a strip method of processing data, providing simultaneous recording and reading information from an information storage that improves performance of the device. In filters Huffman is the multiplication of the sequence of test polynomials BCH codes and RM h1(x) and h2(x). Thus, in the first filter Huffman calculates the syndrome of the BCH code word sequence with1and the second filter is a syndrome code RM sequence c2i. For correct word syndrome code is zero and is egistra syndrome is written to the combination of the d 0corresponding converted into filters Huffman sequences with3. For misspelled words, correcting where possible within the correcting ability of the code in the syndrome register is written, the combination of a set {di}corresponding to the converted in filters Huffman sequences with3and c4and uniquely identifying a combination of errors. The proposed method synchronizes not only according to the BCH code, accepted with errors that can be corrected within the correction ability of the total sequence c1⊕c2i⊕c3ni.e. the number of errors in each code word BCH should be no more than e≤(n1-k1-k2)/log2(n1+1), which uniquely corresponds to a specific syndrome of the code, but according to the code, the number of errors that is equal to e≤(n1-k1)/log2(n1+1) and exceeds the correction capability of the code corresponding to the total sequence c1⊕c2i⊕c3n. In case of exceeding the correcting ability of the code to one syndrome may correspond to several different combinations of errors. We denote the set of such syndromes {ri}. The block decoders finds in the syndrome register combinations of door who is inali of sets {d i} or {ri} and outputs to the input unit adders modulo two appropriate combination of error correction. Another output of block decoders receives signals to the input of the decoder confirmed with detection of misspelled words from the set {di}. At this point in the case of the second filter Huffman is a binary combination of numbers that uniquely corresponding to the sequence c2ibecause the sequence c1becomes zero after multiplication by the polynomial h1(x) in the first filter Huffman, and the sequence with3is constant. This binary combination of numbers from the output of the register is fed to another input of the adders modulo two. In block adders modulo two is the correction bits of the considered combinations of numbers so that its output was binary combination corresponding to the number of words BCH code. For this purpose, the block decoders recognize combinations of the syndrome in the syndrome register, determines the combination of errors and issues appropriate correction signals to the input unit adders modulo two. Combination syndrome, which are recognized by the block decoders receive by calculating a syndrome for each of the possible combinations of errors. Example of construction of the block decoders presented in the East is cnice Clark, J., ml, Kane, J. Encoding with error correction in digital communication systems: Lane. from English. - M.: Radio and communication, 1987, p.96-101. Adjusted non BCH code word from the output of the unit adders modulo two is fed to the input of the register unit and simultaneously to the input of the comparison circuit of the rooms and to the input of the switch rooms. The register unit made in the form of parallel shift registers, each of which is equal to the number of words BCH code with unit output adders modulo two. The number of parallel registers equal to the number of options adjustment combinations for each number of the code word BCH syndrome which corresponds to the set {ri}. For words BCH code, syndromes which correspond to the combination of d0or the set {d1}in each of the parallel registers is written to the same numbers. The length of each of the shift registers of the register unit equal to the length of the BCH code word. To the clock input of register unit is constantly supplied clock speed that matches the speed of delivery of information to the input device. Thus, recorded in the register unit numbers appear at its output when new numbers next word BCH code appear at the input of the register unit. At the same time the number of words BCH code with unit output registers is fed to the input of the full adder of rooms, is where all rooms are words BCH code is added to the unit. As numbers of consecutive words BCH code differ by one, the number of words BCH code on the output of the full adder of rooms and the number of words BCH code with unit output adders modulo two must match. In the comparison circuit of rooms each option adjusted numbers coming from the output of the unit adders modulo two, compared with all the numbers present at the output of the full adder of the rooms. The output of the comparison circuit of the rooms, which are all variants of the comparisons of the input and output numbers of the register unit is connected to the input of the selection plan. Another input of the comparison circuit connected to the output of the full adder, which receives increased per unit calculated values of the length of each sequence numbers. Sampling scheme locates the value of the account in the longest sequences and generates at its output the signal resolution. The output of the circuit selection is connected with the control input of switch accounts. On another information input switch accounts from the output of the full adder receives the invoice values, which are then fed to the output switch accounts and further to the input circuit registers account for signal resolution with the output of the circuit selection. The number of shift registers in the scheme account registers equal to the number of shift registers in the register of the century The length of each of the shift registers schema registers accounts, as well as the length of each of registers a block of rooms equal to the length of the BCH code word and the number of digits of the word register circuit registers the account matches an entry of the maximum number of counted numbers in the sequence of consecutive words BCH code. For room recording, for example, up to eight, in the scheme of the case with just three digits in the word register (23=8). Each register block registers contain the next number of the sequence numbers corresponds to a shift register in the scheme account sequence number written to it by the numbers, counting the length of this sequence. To the inputs of shift registers schema account sequence number is written to the original values for the respective rooms, in which there is no comparison or who has reached the given maximum length sequence. Also the initial values for the initial installation are recorded in the shift register circuit invoice sequence number. The calculation sequence number counts the number of coincidences of rooms in the schema comparison numbers for consecutive words BCH code. In case of equal number of matches specified threshold value in the output schema definitions posledovatelno and a given length schema counting sequence numbers generated signal transfer which indicates a high reliability of a received combination of rooms. Variant structural schema that defines the specified sequence number for fixing the true numbers, see "Device error-correcting coding of digital information for the channel with probability of error of up to 10-1", Proceedings of the Russian scientific-technical conference "New information technologies in communication and control systems", 15-16 may 2007, Kaluga, SCR-296. The signal transfer from the output of the circuit invoice sequence number switch rooms connects the appropriate combination of options non BCH code word from the output of the unit adders modulo two to the input of block counter. The switch may connect one or more values of the numbers associated with short sequences. Switch on the signal output from the decoder confirmed words also connects the corresponding unique combination of numbers, words BCH code with unit output adders modulo two to the input of block counter. It is assumed that the decoder confirmed words allows the entry of numbers only for the true words BCH code, unique rooms which was confirmed by the numbers of the previous words BCH code having the syndromes for error no more than correcting ability summary the th sequence 1⊕c2i⊕c3n. The signals from the outputs of the scheme account sequence number and decoder confirmed words are received at the inputs of the distributor. For the maximum number of combinations of multivariate non scheme dispenser shall contain an appropriate number of podrazdeleniya. The scheme of each of pokespecial can be constructed, for example, on the basis of the D-flip-flop. In the initial state, all the Q-outputs of serially connected D-flip-flops pokespecial are in a state of logical "0". Upon receipt of the clock signal pokespecial on the Q-output of the first D-flip-flop is formed by a logic level "1", which is a two-input circuit OR supplied to the D-input of the second D-flip-flop and the input of two-input circuit And a second input which is connected to the output of the following scheme OR, one input of which is connected to the Q output of the second D-flip-flop. On the second inputs of each OR can receive signals of logic "1", prohibiting the entry of new values of the numbers in the corresponding synchronized counters block counters and restart. The output of the circuit And is connected to D-input of the next D-flip-flop and the input of the following two schemes And. After a two-input circuits OR the first and last D-flip-flops circuit pokespecial input schema And missing. With each clock signal is crimson of pokespecial is the promotion of logical level "1" to the Q output of the last D-flip-flop. When all of the Q outputs of the D flip-flops are set to a logical "1", there is a General reset of all the Q-outputs of the D flip-flops in state logical "0". The second input of each input schema OR is intended to feed him the logical level "1" to prevent the formation of the circuit output OR differential signal of logic "0" logic "1", enabling the account numbers in the relevant counters in block counters and run these counters. The output of the distributor is connected to the input of block counter, another input connected to the output switch rooms. The block counter works as follows. The output signal of the distributor there is a record from the output of the switch room on the second count of the number of this word BCH code and the simultaneous launch of the first counter. When the first counter dositive to the end that corresponds to the length of the BCH code word is formed of the clock signal for the second counter, and its value is incremented. The moment when the second counter dositive to the end, must comply with the finding end-of-block code words BCH. However, there is a chance of receiving false words BCH code, that is, transformations, especially in channels with high noise level. When running counters transformations the end of the account will not correspond to the true end of the block of words BCH code. is therefore the number of counters in block counters should be calculated by taking into account the possible reception of the transformation. The maximum number of counters may be equal to the number of words in the block of code words BCH or even more with regard to possible changes in the boundaries of the two words BCH code and ambiguous definitions of combinations of numbers for words BCH code in channels with high noise level. To reduce the number of counters while maintaining the reliability of the reception block counters provided by pairwise comparison of all numbers of counters in each pokespecial, as well as their comparison with the numbers of the counters of all the other podrazdeleniya. During synchronization is sequential record numbers in the counters until the end of the length of podrazdeleniya. For subsequent entries of rooms verifying synchronous operation of the counters, and the entry of new rooms is only in the synchronized counters, and the counters have to synchronize with each other, the entry of new non-Smoking or until the end of their account or to reset all counters at the end of the block or signal initial setup. The outputs of the block counter signals are formed about the end of the block of words BCH code, which is fed to the input of the threshold unit. At the output of the threshold block is the true signal the end of a block of words BCH code. The length of the sequence schema account sequence number, word count decoder is confirmed words and the characteristics of the majority of the schema element threshold block are selected so that to ensure a high probability of correct frame synchronization for a specific channel. For example, cascading code, external code which is the code PC (32, 16)and the inner code BCH (31, 16), the number of rooms equals thirty-two, the volume of the syndrome register, equal to the difference between the number of check bits and the number of bits in the number, the equivalent of ten bits, it is possible to correct one error in each code word BCH (31, 21). Each of the remaining 988 syndromes correspond to five words BCH code, containing two or three errors, so the number of registers in the register unit is five. The table below shows the quantity of room options for words code BCH (31, 21) to the number of their syndromes depending on the length of the sequence schema account sequences of numbers.
The table shows that the choice of a sequence of five words should be connected to the block counter non-multiple, dual, triple path and chetyrehkantnye combination of rooms. Therefore, the dispenser combinations of numbers contains four pokespecial. The most likely is the explicit determination of the rooms, so pokespecial for such rooms should run the greatest number of counters, for example, six, as in 32-bit words can be no more than six non-overlapping sequences of the five words. For dual, triple path and chetyrehkantnyj rooms pokespecial run on three meter, the AK for actuation threshold of the unit minimum number of synchronized counters on the results of the simulation are defined as three. Therefore, the dispenser can run fifteen meters. The threshold block contains the majority element that generates a signal of the end of the block of information provided synchronizing three or more counters of fifteen. The number of counters should consider the effect of erasing, that is, their number should be sufficient to erase the true signs synchronization false signs synchronization. In the process of transmission information sequence may be distorted as evenly as a single bit-error and uneven - in the form of errors in several bits, consecutive, so it is possible grouping errors. Therefore, when receiving the information sequence along with the words with a great number of errors may contain infallible words or words with a small number of errors even for channels with high noise level. The decoder confirmed words generates at its output a permission signal for connecting rooms only for correct words and words with one error, which is confirmed by the presence of the previous word, which can contain no more than three errors. Modeling and experimentally determined that in channels with a high level of noise between words and words with a large number of errors are generated sequence, the syndromes to which x can match even the infallible words and words with the same error. Thanks to the operation confirm the number of such transformations is reduced, so there is no need to increase the number of counters in block counters, which leads to simplification of the circuit solutions. The definition of non-words, at least two criteria increases the probability of synchronization, since P=P1+P2-P1P2>P1, where P1- the probability of a synchronization sequence numbers, registered scheme account sequence number, P2- the probability of synchronization in proven infallible words and words syndromes which correspond to the set {di}. Cycle synchronization is performed according to code with errors within the correcting ability of the code, and short sequences of code words with errors beyond the correction ability of the code and leads to multiple solutions. To block messages, the probability of correct synchronization, the probability of synchronization and the probability of false synchronization form a complete group, which corresponds to the equation PPS+Pdrug+Pna=1 Therefore, the probability of correct synchronization block of the message is defined as PPS=1-(Rdrug+Pna)≅1-Rna, since typically Rna>>Rdrug. <> The probability of rasinhronizatsiey can be defined as
where P(≤t) is the probability of synchronized code words with correct errors
where p is the average probability of error per bit, t - the maximum number of errors that can be corrected when the synchronization L - the threshold number of code words for synchronization block of the message. From the above formulas it follows that to reduce the likelihood of rasinhronizatsiey block messages need to fix the maximum number of errors t in synchronized code words and to reduce the length L of a synchronizing string of code words. To increase the probability of correct synchronization message block must simultaneously reduce the likelihood of rasinhronizatsiey and the probability of false synchronization block of the message. To reduce the probability of false synchronization block messages tend to increase the threshold, that is, increase the length of the timing chain, which leads to a contradiction, since the probability of rasinhronizatsiey block messages. To reduce the likelihood of rasinhronizatsiey block messages, we must reduce the length of the timing chain, which leads to a greater probability of false synchronization block messages and to reduce the time the fun is testing the device without failure. The proposed method frame synchronization allows to overcome this contradiction, i.e. allows to simultaneously reduce the likelihood of rasinhronizatsiey and the probability of false synchronization block of the message. To implement this way to the entrance of the main device code frame synchronization, the operation of which is described above, after the delay in parallel connect multiple cyclic code synchronization devices, and to output the decoding device. In order not to lose the true sign of synchronization, the delay should be more time procedures decoding BCH code and sort code words PC for a set number of code words PC decoding device of the main device code frame synchronization required for further decoding. The delay should be minimal, because her time is included in the total processing time information, which determines the maximum speed of the received data unit. At refusal of decoding the decoding device of the main device code frame synchronization in the other parallel device code frame synchronization signal resolution, according to which the following device code frame synchronization skips the first sign of boundary synchronization, dedicated to superior quality products is obtained for the primary device code frame synchronization and responds only to the second characteristic boundary synchronization. The following device code frame synchronization skips respectively two characteristic boundaries synchronization and reacts only to the third characteristic boundary synchronization, etc. of the permission Signal from the main device code frame synchronization is removed in the case of the set of code words PC to decode and reset to its original state. If the enable signal goes true mark of a boundary synchronization and provides a set of code words PC, the code decoder PC corresponding device code frame synchronization takes the right message. In contrast to the methods code frame synchronization using a sliding window, which is typically less than the length of the message block in the proposed method, the code frame synchronization decoding is conducted on the entire length of the message block that maximizes the probability of correct synchronization block of the message. In the main device code frame synchronization at the first sign of a border sync block counter is reset, and starts recording the incoming data into the second RAM drive. In other devices, the code frame synchronization this function is performed only for the corresponding signs of the borders synchronization, and for intermediate characteristics borders of synchronization is then in block counters in the initial state are reset only those counters, which counted to its end, and write data is still in RAM drives. We denote the T - transformed probability of words and the number of rooms in the numbering sequence in the message block. The probability of a sequence of three transformed words in the message block can be defined as For a more accurate test of determining the end of the message block can be used for complete decoding procedure code, including the decoding of the outer code cascade code. For code words PC, you can enter a checksum that ensures the correctness of the results of decoding. The proposed method code frame synchronization, unlike the prototype, allows to reduce the length of the synchronization chain to reduce the likelihood of rasinhronizatsiey, and also to reduce the probability of false synchronization block of the message by increasing the number of devices code frame synchronization to determine the true end of the message block, which increases the probability of correct synchronization block of the message. Achievable technical result of the proposed method device code frame synchronization is to increase the reliability of received data in channels with high noise level. 1. The way the code frame synchronization, namely, that the accepted input sequence consisting of several consecutive words, each of which represents a bitwise sum modulo two error-correcting cyclic code, synchronizing sequence and numbering sequence, first multiply by the check polynomial of error-correcting cyclic code and the result of the multiplication is get the sum of the syndrome of error-correcting cyclic code, synchronizing sequence and numbering sequence, then the resulting sum is multiplied by the check polynomial numbering sequence and get the sum of the syndrome of error-correcting cyclic code and a synchronization sequence, the sum of the syndrome of error-correcting cyclic code and synchronizerproxyuserdeclineauth define the error vector error-correcting cyclic code, including and beyond its remedial abilities, then for a given vector of error by the sum of the syndrome of error-correcting cyclic code, synchronizing sequence and numbering sequence of the numbers numbering sequence, which in case of exceeding the number of rooms numbering sequence of threshold values determine the end of the message block and make a decision about code frame synchronization block messages, characterized in that the accepted input sequence recorded in parallel in multiple storage devices, the first order signal the end of the block of the message is checked for the correct signal the end of a message block using the procedure of decoding block messages that are recorded in the first storage device, the second order signal the end of the block of the message is checked for the correct signal the end of a message block using the procedure of decoding the message block stored in the second storage device, and so forth, when the set threshold number of words required for decoding error-correcting cyclic code in one of the storage devices, decide on a code frame synchronization of blackbooty. 2. The method according to claim 1, characterized in that a message block consists of words robust cascade code, internal code which is a block of binary error-correcting code and the outer code is a reed-Solomon code and the decoding procedure of the message block is the decoding of the inner code cascade code. 3. The method according to claim 1, characterized in that the decoding procedure of the block of the message is to decode the outer code cascade code.
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