Device for synchronization by cycles

FIELD: electric communications, possible use in receiving devices for synchronization by cycles of system for transferring discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, forbidding element, first AND element, adder, shift registers block, generator of clock pulses, OR element, cycles counter, counter of distorted synchronization signals, block for selecting allowed number of distorted synchronization signals, block for selecting threshold, block for selecting counting coefficient, counter by exit from synchronization status, and also solving assembly, containing first comparison block, memory block, subtraction block, second comparison block, comparison counter, second AND element, third AND element, second OR element.

EFFECT: increased reliability of operation of device for synchronization by cycles due to excluded possibility of overflow of shift registers block in synchronous operation mode.

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The invention relates to telecommunication and can be used in the receiving device sync cycles of transmission of discrete messages.

A device for synchronizing the cycles of A.S. USSR 436393 class G 11 19/00, publ. 15.07.1974, bull. No. 46, containing, as the proposed device, the detector of the synchronization signal, the adder, the unit shift registers, a crucial node, and the output of the detector clock connected to the first input of the adder, the output of which is connected to the signal input of the shift registers, the main output of which is connected to the second input of the adder. In addition, in the known device, the main output of the unit shift registers is connected with the signal input of the decision making node. This adder is made in the form of n-bit reversible counter which performs a counting function response of the detector clock on each of the pulse positions of cycles of the observation interval, and n shift registers of unit shift registers perform the saving of the results account for the duration of the cycle. In clock intervals defined by clock pulses from a clock pulse is cheating values of bits of the n-bit counter in the first cell of the corresponding shift registers and write to the same counter values of the last cells of the shift registers. If the clock in the interval is the response of the detector clock in the n-bit counter is added to the unit, and thus the value of the binary number corresponding to the number of responses accumulated previously in this position the loop is incremented. If the position loop is no response of the detector, the number recorded in parallel binary code into an n-bit counter with the last cell of register is decreased by one. After a cycle in cells of registers in a parallel binary code are recorded the results of the response of the detector for all N pulse positions. Based on the analysis of these results, a crucial node determines the position number, which corresponds to the largest binary number of responses of the detector clock, and thus decides the position of synchronism. The output of the decision making node is an output device. A disadvantage of the known device is the low reliability due to the possibility of overflow of the unit shift registers, leading to malfunction of the decision making node and the whole device. This is due to the fact that the synchronization signal from the output of the decision making node does not reset the unit shift registers. The block shift registers continues to accumulate the responses of the detector clock. Therefore, after a certain number of cycles, search in many cell block region is TRS shift (not only on the position of the true clock) will be setting the maximal possible values of accumulation, that will lead to malfunction of the decision making node and the whole device as a crucial node after overflow cannot determine the position of the clock.

Closest to the present invention is a device for synchronizing the cycles of the RF patent № 2231228 class H 04 L 7/08, publ. 20.06.2004, bull. No. 17, prototype, containing, as the proposed device, the detector clock element of the ban, the first element And the adder, the unit shift registers, a crucial node, the driver of such pulses, the element OR the cycle counter, the counter distorted signals, the block select a valid number undistorted signals, the block selection threshold, the block selection coefficient accounts, the counter out of synchronism. Moreover, a crucial node contains the first block of comparison, a memory unit, a subtraction unit, a second unit of comparison, the counter comparison and the second element And. the Output of the detector clock jointly connected with the second input element of the ban, the second input of the first element And to the first input of the adder, the output of which is connected to the signal input of the shift registers. The main output of the unit shift registers connected to the second input of the adder, and an additional output to the signal input of the decision making node. The signal input of the decision making node is the first input of the first unit of comparison. P and the output of the first unit of comparison is connected to the control input of the memory block, the output of which is connected to the second input of the first unit of comparison and the first input of the subtraction unit. The second input of the subtraction unit is combined with data input of the memory block, the first input of the first unit of comparison is the signal input of the decision making node. The output of the subtraction unit is connected to the second input of the second block of comparison, the output of which is connected to the reset input of the counter comparison, the output of which is connected to a second input of the second element And. While managing and clock inputs of the decision making node are, respectively, the first input of the second block comparison and the clock input of the counter comparison. Additional managing input decisive node is the first input of the second element Acting out a casting site jointly connected to the reset inputs of the former (cyclic pulses of unit shift registers, and also to the second input of the OR element. The output of shaper cyclic pulses jointly connected to the first input of the first element And the first input element of the ban and the entrance to the loop counter. The output of cycle counter connected to the control input of the counter distorted signals. The output of the counter distorted signals jointly connected to the address inputs of the block select a valid number undistorted singlesymbol, block selection threshold and the block selection coefficient accounts. The output unit in the boron valid number undistorted singlesymbol connected to the control input of the detector clock. The output element of the ban jointly connected to the counting input of the counter out of synchronism and counter the distorted signals. The output of the first element And connected to the first input member OR the output of which is connected to the reset input of the counter out of synchronism. To the input of counter data output from the synchronism is connected to the output of the block selection coefficient accounts. The clock input of the shaper cyclic pulses combined with a clock input of the Recognizer clock, the unit shift registers of the decision making node. The control input of the decision making node coupled to the output of the block selection threshold, and additional control input of the decision making node is connected with the output of the counter out of synchronism. When this signal input to the detector of the clock, the clock input of the shaper cyclic pulses and the output of the shaper cyclic pulses are respectively the signal input, a clock input and output devices. In addition, in the known device the output of the decision making node is the output of the second element And which is connected to the reset input of the memory block. The disadvantage of the prototype is the low reliability due to the possibility of overflow of the unit shift registers in synchronous mode, leading to malfunction of the decision making node and the whole device. This obukov is provided, however, the sync signal deciding node Abdoulaye unit shift registers can be formed only if the detection counter is out of synchronism failure of synchronism and the detection of a critical node clock. In synchronous mode, the counter output from the synchronism zeroed. Therefore, even when the detection decisive true node clock at its output the synchronization signal is not generated. The block shift registers are not reset, but continues to accumulate responses. Therefore, after a certain number of cycles, search in many cells of the unit shift registers (not only on the position of the true clock) will be setting the maximal possible values of accumulation that will lead to malfunction of the decision making node and the whole device as a crucial node after overflow cannot determine the position of the true clock in synchronous mode, and after the failure of synchronism.

Transmission feature of deterministic sequential clock is the frequency of its repetition on the same positions of the transmission cycle of the group signal. This Recognizer clock can recognize in the received multicast signal is not only true singlegroup, but false, randomly generated information on the positions of the cycle. Reformirovanie at the output of the Recognizer trigger responses in the form of units (identified on singlegroup) and zeros (the unidentified singlegroup) the required accuracy of decision-making decisive node is achieved by accumulation of responses in the unit shift registers. Recognition by the Recognizer clock code groups at the position of the synchronization signal leads to the accumulation of responses in cell block shift registers corresponding to the true singlegroup. This recognition by the Recognizer clock code group information on the positions of the cycle leads to the accumulation of responses in cells of the unit shift registers corresponding to a false synchrogram. A crucial node specifies the cell with the maximum accumulation of responses. This cell corresponds to the position in the cycle, which is considered a crucial site for the position of the synchronization signal with the highest probability. A crucial node can determine the position of the true cyclical clock only when the condition of excess accumulation by a certain amount in one of the cells of the unit shift registers savings over all other cells. For proper operation of the decision making node requires that when determining the true clock unit shift registers were reset (reset to zero), and the process of accumulation response of the detector began anew. When the failure of synchronism reset of the unit shift registers can occur only after detection of the output of the synchronism. It should be noted that for reliable operation of the device the reset unit shift registers in synchronous d is the ima works should be carried out. Failure to follow this procedure may result in overflow of the cell block shift registers, which will lead to malfunction of the decision making node and the whole device. These factors make high demands for reliable operation of the unit shift registers and to prevent its overflow in the synchronous mode, so that, ultimately, contributes to the reliable operation of the entire device to synchronize the cycles.

Device for synchronizing the cycles contains Recognizer clock element of the ban, the first element And the adder, the unit shift registers, a crucial node, the driver of such pulses, the element OR the cycle counter, the counter distorted signals, the block select a valid number undistorted singlesymbol, the block selection threshold, the block selection coefficient accounts, the counter out of synchronism. Moreover, a crucial node contains the first block of comparison, a memory unit, a subtraction unit, a second unit of comparison, the counter comparison and the second element And. the Output of the detector clock jointly connected with the second input element of the ban, the second input of the first element And to the first input of the adder, the output of which is connected to the signal input of the shift registers. The main output of the unit shift registers connected to the second input of the adder, and the additional is hydrated output - to the signal input of the decision making node. The signal input of the decision making node is the first input of the first unit of comparison. Thus the output of the first unit of comparison is connected to the control input of the memory block, the output of which is connected to the second input of the first unit of comparison and the first input of the subtraction unit. The second input of the subtraction unit is combined with data input of the memory block, the first input of the first unit of comparison is the signal input of the decision making node. The output of the subtraction unit is connected to the second input of the second block of comparison, the output of which is connected to the reset input of the counter comparison, the output of which is connected to a second input of the second element And. While managing and clock inputs of the decision making node are, respectively, the first input of the second block comparison and the clock input of the counter comparison. Additional managing input decisive node is the first input of the second element Acting out a casting site jointly connected to the reset inputs of the former (cyclic pulses of unit shift registers, and also to the second input of the OR element. The output of shaper cyclic pulses jointly connected to the first input of the first element And the first input element of the ban, and the entrance to the loop counter. The output of cycle counter connected to the control input of the counter distorted signals. Output scetchy is and distorted signals jointly connected to the address inputs of the block select a valid number undistorted singlesymbol, block selection threshold and the block selection coefficient accounts. The output unit selecting a valid number undistorted singlesymbol connected to the control input of the detector clock. The output element of the ban jointly connected to the counting input of the counter out of synchronism and counter the distorted signals. The output of the first element And connected to the first input member OR the output of which is connected to the reset input of the counter out of synchronism. To the input of counter data output from the synchronism is connected to the output of the block selection coefficient accounts. The clock input of the shaper cyclic pulses combined with a clock input of the Recognizer clock, the unit shift registers of the decision making node. The control input of the decision making node coupled to the output of the block selection threshold, and an additional control input of the decision making node is connected with the output of the counter out of synchronism. When this signal input to the detector of the clock, the clock input of the shaper cyclic pulses and the output of the shaper cyclic pulses are respectively the signal input, a clock input and output devices.

The technical result in the implementation of the invention is to enhance reliability of the device to synchronize the cycles is achieved by introducing into a crucial node of the third element And, as well as storageelement OR. Thus the output of the counter comparison is also connected to the first input of the third element And the second input of the third element And is connected to the output device. The output of the third element And is connected to the second input of the second element OR to the first input of which is connected to the output of the second element And. the Output of the second element OR connected to the reset input of the memory block. The output of the second element OR an output of the decision making node. Thanks to the introduction of a crucial node of the third element And the second element OR increases reliability of the device to synchronize the cycles, as in the synchronous mode of operation upon detection of the true clock does not overflow block shift registers. Reset the unit shift registers is performed by the synchronization signal generated on the output of the second element OR. The discovery of a critical node in the mode matching exactly true clock is determined using the third element Acting Upon simultaneous receipt of signals from the output of the counter comparison and output devices sync cycles to the inputs of the third element And outputs the synchronization signal. While using the second item OR the operation of priklucheniya to the output of the decision making node synchronization signal, generated or in crash mode matching (the output of the second element), or in synchronous mode (the third element).

Conducted by the applicant's analysis of the prior art, including searching by the patent and scientific and technical information sources, and identify sources that contain information about the equivalents of the claimed invention, has allowed to establish that the applicant had not discovered similar, characterized by signs, identical with all the essential features of the claimed invention. Select from a list of identified unique prototype, as the most similar in essential features analogue, has identified a set of essential towards perceived by the applicant to the technical result of the distinctive features in the claimed device, set forth in the claims. Therefore, the claimed invention meets the criterion of "novelty".

To check the compliance of the claimed invention, the criterion of "inventive step", the applicant conducted an additional search of the known solutions to identify signs that match the distinctive features of the prototype of the characteristics of the claimed device. The search results showed that the claimed invention not apparent to the expert in the obvious way from the prior art, as defined by the applicant. Not identified the impact of the reforms envisaged essential features of the claimed invention, to achieve a technical result. In particular, the claimed invention does not provide the following transformations: addition of known means of any known part attached to it according to certain rules, to achieve a technical result, in respect of which it is the effect of such additions; the replacement of any part of the other known means known part to achieve a technical result, in respect of which it is the effect of such a change; the exclusion of any part of the funds while the exclusion of its functions and the achievement of a result of such exclusion; an increase of similar elements to enhance the technical result due to the presence in the vehicle is such elements; the execution of a known drug or part of a known material to achieve a technical result due to the known properties of the material; the creation of tools, consisting of well-known parts, the choice of which and the relationship between them is carried out on the basis of known rules, recommendations and achievable technical result is due only to the known properties of the parts of this object and the relationships between them; change quantitative attributes or relations to recognize the s, if you know the fact of the influence of each on the technical result and the new values of the signs or their relationship could be obtained from the known dependencies. Therefore, the claimed invention meets the criterion of "inventive step".

The invention is illustrated by the drawing, which shows a structural diagram of the device for synchronization cycles. Information confirming the ability of the invention to provide the above technical result are as follows.

Device for synchronizing the cycles contains Recognizer 1 clock, item 2 of the prohibition element 3 And the adder 4, block 5 shift registers, a crucial node 6, the imaging unit 7 cyclic pulses, item 8, OR, the counter 9 cycles, the counter 10 distorted signals, block 11 select a valid number undistorted singlesymbol, block 12 of the choice of the threshold, the block 13 ratio selection account, the counter 14 out of synchronism, the input signal 15, the clock input 16, output device 17. A crucial node 6 contains the block 18 comparison unit 19 of the memory block 20 subtraction unit 21 comparison, the counter 22 comparison, item 23 item 24 And item 25 OR. The output of detector 1 clock jointly connected with the second input element 2 of the ban, the second input element 3 And to the first input of the adder 4, o is d which is connected to the signal input unit 5 shift registers. The main output unit 5 shift registers connected to the second input of the adder 4, and the additional output to the signal input of the decision making node 6. The signal input of the decision making node 6 is the first input unit 18 of the comparison. Thus the output of block 18 comparison is connected to the input of the control unit 19 of the memory, the output of which is connected to the second input unit 18 of the comparison and the first input unit 20 subtraction. The second input unit 20 subtraction combined with data input block 19 of the memory, the first input unit 18 of the comparison signal is input decisive node 6. The output of block 20 of the subtractor is connected to the second input unit 21 of the comparison, the output of which is connected to the reset input of the counter 22 comparison. The output of counter 22 comparison jointly connected to the second input of the element 23 and to the first input element 24 And. the Output element 23 And connected to the first input element 25, OR, to the second input of which is connected to the output element 24 And. the Output element 25 OR connected to the reset input of block 19 of the memory. While managing and clock inputs of the decision making node 6 are, respectively, the first input unit 21 comparison and the clock input of the counter 22 comparison. The first additional control input of the decision making node 6 is the first input element 23 And. a Second additional control input of the decision making node 6 is the second input element 24 And. Outlet decide what its node 6 is the output element OR which is connected to the reset inputs of the former (7 cyclic pulses, block 5 shift registers, and the second input element 8 OR. The output of the shaper 7 cyclic pulses jointly connected to the first input element 3 And the first input element 2 of the ban, the input of the counter 9 cycles, and the second additional control input of the decision making node 6. The output of the counter 9 cycles connected to the control input of the counter 10 distorted signals. The output of the counter 10 distorted signals jointly connected to the address inputs of the block 11 select a valid number undistorted singlesymbol, block 12 of the choice of the threshold and the block 13 ratio selection account. The output of block 11 select a valid number undistorted singlesymbol connected to the control input of the detector 1 clock. The output element 2 of the prohibition jointly connected to the counting input of the counter 14 out of synchronism and the counter 10 distorted signals. The output element 3 And connected to the first input element 8 OR the output of which is connected to the reset input of the counter 14 out of synchronism. To the data input of the counter 14 and the output from the synchronism is connected to the output unit 13 ratio selection account. The clock input of the shaper 7 cyclic pulses combined with a clock input detector 1 clock, unit 5 shift registers and decisive node 6. Opravlyaushi the input of the decision making node 6 is connected to the output unit 12 of the choice of the threshold, and the first additional control input of the decision making node 6 is connected to the output of the counter 14 out of synchronism. When this signal input of the detector 1 clock, the clock input of the shaper 7 cyclic pulses and the output of the shaper 7 cyclic pulses are respectively the signal input 15, a clock input 16 and output 17 of the device.

Device sync cycles is as follows. At the signal input of the detector 1 clock group enters the digital signal containing the deterministic group of the synchronization signal that is repeated with a repetition rate of the cycles. Information items group code signal group information symbols, is identical to singlegroup, are formed randomly. When the input detector 1 clock combination with the structure of singlegroup on outputs its response in the form of a single pulse, arriving next to the first input of the adder 4, the second input element 2 of the ban and the second input element 3 I. the control input of the detector 1 clock output unit 11 is supplied a valid number k undistorted singlesymbol. The detector 1 clock consists of a shift register, decoder clock, the encoder and the comparator. The shift register performs a conversion operation group cifrovoj the signal, coming to the information input of the shift register of the sequence in the parallel code. During each clock interval in the shift register is written to one symbol of the received signal, and with the arrival of the next character previous moves to the next cell in the shift register. Thus, for m clock intervals in the register is written m-character code combination (where m is the number of characters in singlegroup). From the output of the shift register group signal in parallel code is input to the decoder clock. The decoder is configured to recognize the clock. The output of the decoder is connected encoder. The encoder is designed to generate binary numbers accurately detected singlesymbol. Comparing the device performs the operation of comparing the numbers accurately detected singlesymbol in singlegroup with a valid number k undistorted singlesymbol. If the number is accurately detected singlesymbol greater than or equal to the allowable number k undistorted singlesymbol, the output of detector 1 clock generated single signal (response). Otherwise, the output of detector 1 is "zero" signal. The detector 1 clock can be implemented, for example, as described in the description of the invention to the patent of Russian Federation № 2231228 class H 04L 7/08, publ. 20.06.2004, bull. No. 17 figure 2.

The adder 4 is a parallel combinational adder, whose younger bit input of the first term (low-order bits of n-bit input and n-bit inputs of the second term are respectively the first and the second input of the adder, while the other (n-1)-bit inputs of the first summand is connected to the source of the "zero" level.

Unit 5 shift registers includes n-bit (n=[log2N]+1, N is the number of positions in one cycle) shift registers. United clock inputs and the United inputs reset shift registers are respectively a clock input and a reset input block 5 shift registers, and the signal inputs, the outputs of the last bits and outputs the first digits of all shift registers are respectively the signal input, main output and an additional output side 5 shift registers. Thus, the response of the detector 1 clock in the i-th clock interval, formed in the adder 4 with the previous account of the responses to the i-th position of the loop coming from the main output unit 5 shift registers. A new result of counting responses, larger one still written in the form n-bit binary number in the corresponding first cell (bits) shift registers block 5 shift registers. P and this binary number, recorded before in the first cell block 5 shift registers, and all other numbers are stored in subsequent similar cells, in parallel shifted by one digit, and the main output unit 5 shift registers to the second input of the adder 4 receives the result of counting responses (i+1)-th clock interval. If the response of the detector 1 clock (i+1)-th clock interval is not present, then the previous result account of the responses to (i+1)-th position of the cycle corresponds to the first cell block 5 shift registers, and other numbers that are stored in the same cell block 5 shift registers are shifted by one digit, etc. Block 5 shift registers provides storage of account results of the responses to each position of the loop within the loop duration. The value of n determines the memory capacity of account results. At the same time the account of the responses to each of the positions of the cycle with an additional output unit 5 shift registers sequentially arrive at the signal input of the decision making node 6. In the final node 6, for example in the i-th clock interval, the input binary number in parallel code representing the current account responses to the i-th position of the cycle, is simultaneously supplied to the first input unit 18 of the comparison, the data input block 19 memory and the second input unit 20 subtraction. In block 18 the comparison of the input number cf universe with a binary number, stored in block 19 of the memory, and if it exceeds the number of block 19 of the memory, the output unit 18 comparison is formed impulse, which, when the input control unit 19 memory provides the Erasure of the old and the new record (input) number. The input unit 18 of the comparison are equal to a binary number. If the input number is equal to or less than the number stored in the block 19 to the memory, the content of the latter is not changed. Thus, in block 19 of the memory is overwritten greatest the current account responses to any of the position loop, which is then compared to the results account for the subsequent positions of the cycle. The resulting difference between the number of block 19 of the memory and the input number) at the output of block 20 subtraction in the form of binary numbers in parallel code is compared in block 21 comparison with a threshold number d received at its first input (which is the controlling input of the decision making node 6) from the output unit 12 of the choice of the threshold. If the number from the output of block 20 of the subtraction is less than the threshold number d, the output of the second block 21 comparison to the reset input of the counter 22 comparison is "single" (prohibiting) the potential that sets and keeps it in the "zero" state. When the i-th clock interval number from the output of block 20 of the subtraction is equal to or greater than the number d, the output of the second block 21 comparison will occupait "zero" (enabling) the potential and the counter 22 comparison produces a single clock pulse received at its clock input, which is the clock input of the decision making node 6. If the largest binary number written in block 19 of the memory that will exceed each of the N-1 subsequent numbers coming one after another with an additional output unit 5 shift registers, an amount equal to or greater than the threshold number d, the counter 22 comparison will produce the following N consecutive clock pulses. Then its output is formed by the single pulse signal, which is supplied to the second input element 23 and to the first input element 24 I. thus, if the counter 14 out of synchronism has done the math α times "neopoznannyi" true singlegroup, at its output, a signal is generated logical unit, which receives at the first input element 23 And permitting the passage of a single pulse signal output from the counter comparison output element 23 And. the Passage of a single pulse signal output from the counter comparison the output element 24 And is carried out upon receipt from the output of the shaper 7 cyclic pulse signal frame synchronization. The element 25 OR performs Poluchenie single pulse signal at the output of the decision making node 6 or the output element 23 or the output element 24 And. the output Signal R is superior to node 6 is an output synchronization signal. In the first case, the synchronization signal at the output of the decision making node 6 is formed with the loss of state matching (loss condition of synchronism is determined by the counter 14 out of synchronism). In the second case, the output synchronization signal is generated in synchronous mode. The sync signal from the output of the decision making node 6 is supplied to the reset inputs of block 19 of the memory unit 5 shift registers of the imaging unit 7 cyclic pulses, and also to the second input element 8 OR. As a result, the block 19 of the memory block 5 shift registers and the counter 14 out of synchronism are reset to "zero". Then from the output of block 21 comparison begins to act prohibiting "single" potential and the counter 22 comparison is also reset to "zero". The output signal synchronized final node 6 is the phase shaper 7 cyclic pulses so that the output 17 of the device start coming regularly following cycle pulses, a time coinciding with the response of the detector 1 clock on the true singlegroup. The process of finding a temporary position of a cyclical clock in binary stream group signal begins again. When the next synchronization signal of the decision making node 6 will be formed under the condition detection timing after the loss of the condition of synchronism ("ed the border" pulse at the output of the element 23) or in the synchronous condition (single pulse at the output of the element 24). In the first case, the synchronization signals of the decision making node 6 will change the phase of the initial installation of the driver 7 cyclic pulses. In the second case, the initial setup phase shaper 7 cyclic pulses will not be changed. The failure condition of synchronism may occur if the temporary position of a cyclical clock is changed, or the synchronization signal α times distorted (more than k singlesymbol). Thus, the counter 14 out of synchronism counts the number of consecutive pulses of the failure of the synchronization signal generated by the element 2 of the ban. Upon reaching the account status α at the output of the counter 14 and the output of the synchronism signal appears permits the formation of a critical node 6 of the synchronization signal. When the detection of the true clock or the formation of the output of the decision making node 6 of the synchronization signal counter 14 out of synchronism is reset to "zero". Blocks 18 and 21 comparison can be performed, for example, in the form of n-bit binary Comparators forming the sign "more", "less" with the appropriate sign of the difference values of the input operands, and a sign of their equality supplied to first and second inputs of the blocks. Block 19 of the memory may be in the form of n-bit register with parallel input. When this data inputs, a control input, the Odom reset and the output unit 19 memory is respectively input data, clock input, a reset input and output data n-bit register. Block 20 subtraction can be performed in a full n-bit parallel adder. The bit width of the adder is provided a serial output connection of the transfer of the adder least significant bits with a carry-in input of adder senior ranks. To perform a full adder operation of subtracting a number from the memory block 20, arriving at the first input of the subtraction unit, subject inversion, and the number coming from the additional output unit 3 shift registers to the second input of the subtraction, inversion is not exposed. Shaper 7 cyclic pulses and the counter 22 comparison and can be made in the form of serially connected binary-synchronous decimal counter and decoder (see, for example, as described in the description of the invention to the patent of Russian Federation № 2231228 class H 04 L 7/08, publ. 20.06.2004, bull. No. 17, figure 3).

The counter 14 out of synchronism is a BCD synchronous pulse counter, the output of which is connected to the first comparator input binary numbers. The counter is designed to count consecutive pulses of a failure of the synchronization signal, which are received from the output element 2 of the ban on the clock input of the counter. The comparator is designed to recognize the achievements of the counter state maximum account equal ratios the NTU account α that block 13 ratio selection account is served in binary code to the second input of the comparator. To the reset input of the counter with the output element 8 OR receives pulses identify the true clock or synchronizing pulse. For storing a status signal of maximum accumulation counter 14 out of synchronism to the comparator output setup input must be connected to the trigger. The counter is reset and the trigger in the "zero" state is received at a reset input of the counter 14 and the output of the synchronism signal "reset". The trigger output is the output of the counter 14 out of synchronism. The counter 14 out of synchronism can be implemented, for example, as described in the description of the invention to the patent of Russian Federation № 2231228 class H 04 L 7/08, publ. 20.06.2004, bull. No. 17 figure 4.

The process of forming the threshold numbers d for the final node 6, the allowable number k undistorted singlesymbol for detector 1 clock ratio and the account α for counter 14 out of synchronism as follows. At the first input element 3 of the prohibition act, the pulse shaper 7 cyclic pulses, and the second input pulses (feedback) of detector 1 clock. As a result, the output element 2 of the ban will only pulse shaper 7 cyclic impulses that sootvetstvujusceje the signals received binary information sequence. Counting the number of R distorted singlesymbol during the time the account is quite a large number of such pulses, it is possible with some degree of accuracy periodically to determine the probability (castest) erroneous reception of the synchronization signal according to the formula Poc≈R/Q, i.e. to produce a current assessment of the degree of distortion of the received signal. While the counter 10 distorted signals counts distorted signals, and the counter 9 cycles - the total number Q of signals transmitted over a given period of time. The capacity of the counter 9 cycles is equal to the value of Q. After counting each Q cycle pulses at its outputs a single pulse, which is supplied to the control input of the counter 10 distorted signals. The counter 10 distorted signals, is designed to count erroneously received signals. The counter 10 distorted signals consists of a counting device and a storage device. At the counting input of the counter 10 distorted signals from the output element 2 of the prohibition of the signals of logical "unit" or "zero". When this signal is logical "unit" corresponds to the detection of a failure (distortion) of the synchronization signal, and a signal of logical "zero" - detection undistorted clock. Therefore, the counter 10 distorted signals provides the treatment tip can the em only distorted signals, the corresponding true synchrogram. These signals are counted using a counting device. The storage device is designed to record and store the result (the number of distorted signals R) during the observation period (the number of cycles Q). The counter 10 distorted signals can be implemented, for example, as described in the description of the invention to the patent of Russian Federation № 2231228 class H 04 L 7/08, publ. 20.06.2004, bull. No. 17 figure 5. Element 2 of the prohibition may be made of serially connected elements of the EXCLUSIVE OR element And. at the first input of EXCLUSIVE OR serves cycle pulses. It is connected with the first input element I. the second input of the EXCLUSIVE OR pulses (feedback) from the detector 1 clock. The output of EXCLUSIVE OR connected to the second input of the element I. the Output element And an output element 2 of the ban.

The counter 9 cycles consists of a counting device and decoder. The counting device is intended for calculation of Q cycles. The decoder is designed to recognize the achievements of the counting device account status equal to Q, and generate the reset signal of the counting device, the reset which is done synchronously (on the positive edge of a cyclical pulse on the clock input of the counting device). The signal reaching the end of the observation period, the Q output MF is tcheka 9 cycles is supplied to the control input of the counter 10 distorted signals. The counter 9 cycles can be implemented, for example, as described in the description of the invention to the patent of Russian Federation № 2231228 class H 04 L 7/08, publ. 20.06.2004, bull. No. 17, 6.

Unit 11 select a valid number undistorted signals, block 12 of the choice of the threshold and the block 13 ratio selection account depending on the value of the number R, is recorded in the counter 10 distorted signals, make the selection accordingly a certain number k undistorted signals, the threshold number of d and s α counter out of synchronism. The selected number k, d and α with outputs of blocks 11, 12 and 13 in parallel code are given correspondingly to the control input of the detector 1 clock to the control input of the decision making node 6 and the input of the counter 14 out of synchronism. Unit 11 select a valid number undistorted signals, block 12 of the choice of the threshold and the block 13 ratio selection accounts can be made in the form of permanent storage devices (for example, on the chip CRF), memory elements which are recorded the results of the calculations are valid numbers undistorted singlesymbol k, threshold numbers d and s α counter out of synchronism, depending on the probability of erroneous reception of the synchronization signal (see Kalinnikov CENTURIES, tashlinskii A.G. Technique for finding the internal parameters of cyclic systems is the synchronization, parallel and recircularii search. - Ulyanovsk: UFWOC, 2002. 35 S. - Dept. in ZUNI the defense Ministry 23.09.02. No. b, publ. STR, Serb, VIP, 2002). The value of the measured probability of erroneous reception of the synchronization signal ROSfrom the output of the counter 10 distorted signals is fed to the address inputs of permanent storage devices units 11, 12 and 13, the outputs of which are the output numbers k, d and α. Thus, during the time of account Q in the detector 1 clock served a certain acceptable number of undistorted singlesymbol, at the crucial site 6 - threshold number d, and the counter 14 and the output from the synchronism factor accounts αthat can take in each case one of the h discrete values (gradation) depending on signal quality. The required number of gradations h numbers k, d and α is selected from the calculation of maintaining the probability of false detection of the synchronization signal within the required limits with various changes in the size of ROS. Under the laws of the formation of specific values of the numbers krundistorted singlesymbol unit 11, the threshold numbers drthe block 12 and coefficient αrthe counter output of the matching unit 13 can be written in the form:

kr=F1(Ar≤Poc<Br),

dr=F2(Ar≤Poc<Br),

αr=F3(A r≤POS<r),

where F1F2F3- pre-selected rules, respectively, for block 11 select a valid number undistorted singlesymbol, block 12 of the choice of the threshold and the block 13 selection factor accounts for which value of POS=R/Q, takes the value within the r-th period (r varies from 1 to h) dimensions, given in compliance with the valid values of krundistorted singlesymbol, the threshold number of drand coefficient αrcounter out of synchronism; Andrand Inrrespectively the lower and upper bound values of ROSfor the r-th interval.

The required noise immunity of the device, which is determined by the probability of false detection of the synchronization signal, is ensured by the choice of the law of formation of the numbers krfor block 11 select a valid number undistorted singlesymbol, numbers, drfor block 12 of the choice of the threshold, and numbers αrfor block 13 selection coefficient accounts for the respective measured values of ROSwithin any r-th interval with boundaries Andrand Inraccording to the principle: the higher the value of POS, the greater must be the number of krdrand αr.

The time interval of observation of the response of the detector 1 clock in the rates in which to decide the phase of the clock cycle, adaptive changes depending on the magnitude of ROSand in each specific case (at a certain value of POSis approaching the minimum possible, which will ensure the required immunity. The Q-value, which determines the ratio of the account of the counter 9 cycles, must be chosen, on the one hand, large enough to provide the desired precision of the estimate of the error probability POSa single character, on the other hand is sufficiently low to ensure that the measurement of POSbetween two failures of synchronism in cycles and tracking of changes to the conditions of communication. If we assume that failures of synchronism in cycles occur relatively infrequently, i.e. intervals that are much longer than the time of account Q cyclic signals, in practice, the value of Q can be chosen as:

where B1- the upper boundary value of POSwithin the first measurement interval, which corresponds to the lowest values of the numbers k1d1and α1; [ ] means rounding to the nearest integer.

The above data confirm that the implementation of the use of the claimed device the following cumulative conditions:

the tool embodying the claimed device in its implementation, is rednaznachena for use in the receiving device sync cycles of transmission of discrete messages;

for the claimed device, as it is characterized in the claims, confirmed the possibility of its implementation using the steps described in the application or known before the priority date tools and methods;

the tool embodying the claimed invention in its implementation, is able to achieve perceived by the applicant of the technical result.

Thus, the claimed invention meets the criterion of "industrial applicability".

Device for synchronizing the cycles containing Recognizer clock element of the ban, the first element And the adder, the unit shift registers, a crucial node, the driver of such pulses, the first element OR the cycle counter, the counter distorted signals, the block select a valid number undistorted singlesymbol, the block selection threshold, the block selection coefficient accounts, the counter out of synchronism, and the output of the detector clock jointly connected to the second input element of the ban, the second input of the first element And the first input of the adder, the output of which is connected to the signal input of the shift registers, the main output of which connected to the second input of the adder, and an additional output unit shift registers connected to the signal input of the decision making unit, which consists of first the th block of the comparison, memory block, block subtraction, the second unit of comparison, counter comparison and the second element And the output of the first unit of comparison is connected to the control input of the memory block, the output of which is jointly connected to the second input of the first unit of comparison and the first input of the subtraction unit, the second input is combined with the first input of the first unit of comparison, and also to the input of the data memory block and is the signal input of the decision making node, clock and control inputs of which are respectively the clock input of the counter comparison and the first input of the second block of comparison, a second input connected to the output of the subtraction unit, and the output the second unit of comparison is connected to the reset input of the counter comparison, the output of which is connected to the second input of the second element And the first input of which is the first additional control input of the decision making node, and the output of the decision making node connected to the second input of the first element OR, as well as to the reset inputs of the former (cyclic pulses and block shift registers, a clock input which is combined with the clock inputs of the detector clock, a casting site and shaper of such pulses, the output of which is jointly connected to the first input of the first element And the first input element of the ban and the input of the cycle counter, the output of which is under the offline to the control input of the counter distorted signals, and the output element of the ban jointly connected to the counting input of the counter distorted signals and counter out of synchronism, the output of which is connected to the first additional control input of the decision making node, and the output of the counter distorted signals jointly connected to the address inputs of the block select a valid number undistorted singlesymbol, block selection coefficient accounts and block selection threshold, the output of which is connected with the control input of the decision making node, and the output unit selecting a valid number undistorted singlesymbol connected to the control input of the Recognizer clock, and the output of the first element And connected to the first input member OR the output of which is connected to the reset input of the counter out of synchronism, to the data input of which is connected to the output of the block selection coefficient accounts, and the signal input of the detector of the clock, the clock input of the shaper cyclic pulses and the output of the shaper cyclic pulses are respectively the signal input, a clock input and output device, characterized in that it introduced the second element OR the third element And the output of the counter compare also connected to the first input of the third element And a second input which is the second additional control input becausepeople, which is connected to the output of the device, and the output of the third element And is connected with the second input of the second OR element, with the first input connected to the output of the second element And the second element OR is connected to the reset input of the memory block, and the output of the second element OR an output of the decision making node.



 

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