Device for group cycle synchronization

FIELD: digital communications.

SUBSTANCE: device has random access memory, adjusting device, synchronous combination decoder, phasing device, generator equipment, three commutators, signals distributor, time analyzer and signals remover.

EFFECT: higher reliability, higher effectiveness, higher interference resistance.

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The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal.

The known device for frame synchronization [1-3], comprising: a Recognizer of synchronously, units retention and retrieval of synchronism, power generating equipment, elements, AND, OR, the inputs and outputs of the devices that are connected in a certain way.

The main disadvantage of these devices is the inability of the same device to synchronize the various digital transmission of information with a temporary seal.

The closest to the technical nature of the claimed invention is selected as a prototype device for frame synchronization [4], containing random access memory device, the device configuration and diagnostics, the decoder synchronously, environment unit, generating equipment, storage devices criteria for entry and exit of synchronism, the inputs and outputs of the devices that are connected accordingly.

Shows the device allows the same device to synchronize a variety of digital transmission of information with a temporary seal. However, it does not provide cyclic synchronization group is identical in structure to the transmission with one from whom trojstva.

An object of the invention is the extension of functionality that allows one device cyclic synchronization band digital transmission of identical structure while reducing hardware costs, power consumption and increase reliability and noise immunity.

This task is solved in that in the device group for frame synchronization, containing random access memory (RAM)device settings (UN), the decoder synchronously (DS), environment unit (FU), generating equipment (TH), and the selection input of RAM is connected to the earth bus and the inputs of the write and read from the corresponding outputs of the UNIVERSITY, the input mode selection, new address, set to zero, write, read, set the RAM or register storing information 0,... ,N inputs and outputs which are relevant inputs device for group frame synchronization (GDS), input-output values synchronously, the position of synchronously, the end of synchronously RAM connected to respective inputs and outputs of the UNIVERSITY and to the corresponding inputs DC output response which is connected with the respective input FU, the input end of synchronously which is connected with the corresponding output of RAM, input-output loop end of which is connected to line the existing entrance-exit UNIVERSITY, the second 02,... ,N2specifies the outputs of which are connected respectively with the sets 0,... ,N inputs, the input set to zero which is connected with the corresponding output of the UNIVERSITY, the outputs of all cycles TH are the corresponding outputs of the device for GDS, according to the invention is introduced first, second and third switches, directional signals (PC), time analyzer (VA) and the remover of signals (CA), and clock inputs and an information input device for GDS connected to respective inputs of the first switch, the clock output of which is connected to the corresponding inputs DS, US, and the third switch, the information output of the first switch is connected with the respective input DC output signal the end of the cycle the RAM is connected with the respective input VA, 0,... ,N specifies the inputs of which are connected with 02,... ,N2specifies the outputs of the UNIVERSITY, the first 01,... ,N1specifies the outputs of which are connected with 0... N specifies the inputs of the PC clock output VA is connected with the respective input PC, 1,... ,M allow the outputs of which are connected to the corresponding inputs of the first, second and third switches and inputs MOUSTACHE, 0,... ,N address outputs of the second switch is connected to the corresponding inputs of RAM, the output of the availability of synchronization FU is connected to the corresponding inputs of the third switch and VA, o the d control which is connected with the corresponding input CONDITION, the clock outputs of which are connected to the corresponding inputs, selects the PC mode and the CONDITION connected with the respective input device for GDS, input the new address which is connected with the corresponding input CONDITION, the input end of synchronously which is connected with the corresponding output of RAM, the output of the zero state FU connected with the respective input CONDITION, the clock input of which is connected to respective inputs of the device for GDS, the address outputs connected to respective FIRST inputs of the second switch, the outputs of the presence of synchronization of the third switch are the corresponding outputs of the device for GDS.

Time analyzer includes first, second and third counters, the first and second triggers, the first and second inverters, the first, second and third elements OR first, second, third and fourth elements And the entrance to the availability of synchronization, the input end of the cycle that specifies the inputs, a control output and a clock output, and input availability synchronization is connected to a second input of the second element OR the second inputs of the first and second elements And the input end of the loop connected to the clock inputs of the first, second and third counters, and the second trigger, and also to the input of the first inverter, the third the input of the first element And the second input of the third element And the output of the first counter is connected with the quantum is the first input of the first trigger, an information input connected to the power bus, the inputs installed in the null of the first counter and the first flip-flop connected to the output of the first element OR the first input and the third input of the second element OR is connected to the output of the fourth element And the output of the first trigger is a control output time analyzer, and is connected to the input of the second inverter and to the first inputs of the first and second elements And the output of the second inverter is connected to the first input of the second element OR the output of which is connected to the inputs setup to zero second, the third counter and the second trigger that sets the inputs of the second counter are specifying inputs time analyzer, the output of the second counter is connected with the allow input of the second trigger, the output of which is connected with the allow input of the third counter, the output of the third counter connected to the first inputs of the third and fourth elements And the output of the first inverter is connected to a second input of the fourth element And the third input of the second element And whose output is connected to the second input of the first element OR the outputs of the first and third elements And are connected with the inputs of the third element OR whose output is clocked out time analyzer, the information input of the second trigger is connected to the power bus.

The novelty of the technical the definition of the solution is present in the inventive device of new circuit elements: first, the second and third switches, the distributor of the signal, time analyzer and remover signals.

Thus, the invention conforms to the criterion “Novelty”.

Analysis of the known technical solutions in the study and related fields allows us to conclude that the introduced functional units known. However, their introduction into a device group for frame synchronization with the above links gives it new properties. Introduced functional units interact in such a way that allow you to extend its functionality, providing one device synchronization band digital transmission with the same structure, reduced hardware costs and the associated energy consumption, improve the reliability and robustness of the device associated with the fact that the use of one storage device when you synchronize a group of digital streams allows to drastically reduce the amount of printed conductors, increase their width, thereby to reduce the resistivity and the chance of breaking the connection between the elements of the device.

Thus, the invention meets the criterion of “Inventive step”, as it is for the expert is not obvious from the prior art.

The invention can be used in digital transmission systems info is the information in Association with asynchronous digital stream.

Thus, the invention meets the criterion of “Industrial applicability”.

Figure 1 presents the structural electrical diagram of the device for group frame synchronization, figure 2 - structural electrical circuit time analyzer figure 3 is an electrical schematic diagram of the remover signals.

The device group for frame synchronization (figure 1) contains the random access memory 1 (RAM)device settings 2 (UN), the decoder synchronously 3 (DS), environment unit 4 (FU), generating equipment 5 (TH), the first switch 6, the dispenser signals 7 (PC), time analyzer 8 (VA), the second switch 9, the remover of signals 10 (US), the third switch 11, and input selection (input CE) RAM is connected to the earth bus, and recording inputs (input WE) and read (input OE) - with the corresponding outputs of SCIENCES 2, the selection input mode (input MODE), new address (input), set to zero (input RES), write (log CE), read (input OE), set the RAM or register recall (input RAM/RG) and information 0,... ,N inputs and outputs which are the corresponding inputs of the device group for frame synchronization (GDS), input-output values synchronously (input-output Zn), the position of synchronously (input-output P), the end of synchronously (input-output CSC) RAM 1 soedinenii corresponding inputs-outputs UN 2 and to the corresponding inputs DC 3, the output response (output IC) which is connected with the respective input FU 4, the inlet end of synchronously (input CSC) which is connected with the corresponding output of RAM 1, the input-output end of the cycle (input-output CC) which is connected with the corresponding input-output UN 2, the second 02,... ,N2specifies the outputs of which are connected respectively with the sets 0,... ,N inputs TH 5, the input set to zero (input RES) which is connected with the corresponding output of SCIENCES 2, the outputs of all cycles (outputs CC1,... ,CCM) are the corresponding outputs of the device for GDS, clock inputs (inputs T1,... ,TMand informational inputs (inputs And1... , AndMdevice for GDS connected to respective inputs of the first switch 6, a clock output (output T) which is connected to the corresponding inputs DC 3, US 10 and the third switch 11, an information output (exit) of the first switch 6 is connected with the respective input DC 3, the output signal of the end of the cycle (output CC) RAM 1 is connected with the respective input VA 8, 0,... ,N specifies the inputs of which are connected with the second 02,... ,N2the outputs of SCIENCES 2, the first 01,... ,N1specifies the outputs of which are connected with 0,... ,N specifies the inputs of the PC 7, the clock output (output T-R) VA 8 is connected with the respective input 7 PC, allowing the outputs of which are connected with the corresponding who moves first 6, the second 9, 11 third switches, and inputs the CA 10, 0,... ,N address outputs of the second switch 9 is connected to the corresponding inputs of the RAM 1, the output of the availability of synchronization (exit f) FU 4 is connected to the corresponding inputs of the third switch 11 and VA 8, the control output (output) which is connected with the corresponding input CONDITION 10, the clock outputs (outputs T1,... ,TM) which is connected to the corresponding inputs TH 5, the selection input mode (input MODE) PC 7 and CONDITION 10 is connected to a respective input device for GDS, input the new address (input) which is connected with the corresponding input CONDITION 10, the inlet end of synchronously (input CSC) which is connected with the corresponding output of RAM 1, the zero output state (output DC“0”) FU 4 is connected with the corresponding input CONDITION 10, the clock input (T1,... ,TM) which is connected to the corresponding inputs of the device for GDS, address outputs (outputs 01,... ,N1- 0M,... ,NM) TH 5 are connected to the corresponding inputs of the second switch 9, the outputs of the presence of synchronization outputs f1,... ,FM) the third switch 11 are the corresponding outputs of the device for GDS.

Time analyzer (figure 2) contains the first 12 and second 13 and third 14 counters, the first 15 and second 16 triggers, the first 17 and second 18 inverters, the first 19, the second 20 and third 21 ELEH the coefficients OR, the first 22 and second 23, 24 third and fourth 25 members, And the entrance to the availability of synchronization (input f), the input end of the cycle (log CS)specifying the inputs (inputs 0,... ,N), control output (output) and a clock output (output T-R), and the entrance to the availability of synchronization is connected to a second input of the second OR element 20 and the second inputs of the first 22 and second 23 elements And the input end of the loop connected to the clock inputs (inputs To the first 12, second 13, 14 third counters and the second trigger 16, and also to the input of the first inverter 17, the third input of the first element And 22 and a second input of the third element And 24, the output of the first counter 12 is connected with a clock input (entrance) of the first trigger 15, data input (D input) which is connected to the power bus, the inputs setup to zero (inputs R) of the first counter 12 and the first flip-flop 15 is connected to the output of the first element OR 19, the first input and the third input of the second OR element 20 is connected to the output of the fourth element And 25, the output of the first flip-flop 15 is the control output time analyzer, and is connected to the input of the second inverter 18 and to the first inputs of the first 22 and second 23 elements And the output of the second inverter 18 is connected to the first input of the second element OR 20, the output of which is connected to the inputs setup to zero (inputs R) 13 second, third 14 counters and the second trigger 16 that specifies the inputs (inputs 0,.. ,N) of the second counter 13 are specifying the input time analyzer, the output of the second counter 13 is connected with the allow logon (logon EC) of the second trigger 16, the output of which is connected with the allow logon (logon EU) third counter 14, the output of the third counter 14 is connected with the first inputs of the third 24 and fourth 25 elements And the output of the first inverter 17 is connected to a second input of the fourth element And 25 and with the third input of the second element And 23, the output of which is connected to the second input of the first element OR 19, the outputs of the first 22 and third 24 elements And is connected to the inputs of the third element OR 21, the output of which is a clock output (output T-R) time analyzer, data input (D input) of the second trigger 16 is connected to the power bus.

Remover signals (figure 3) contains the triggers 26, 27, 28, 29, inverters 30, 31, 321,... ,32Mthe elements 33, 34, 35, 361,... ,36M, 371,... ,37Mthe element OR 38, and input the new address (input ON) remover signals (CA) connected to the first input element And 34, a second input connected to the output of the inverter 31, an input and the first input element And 35 are a selection input mode (input MODE) CONDITION, clock inputs (inputs T1,... ,TM) US connected respectively to the first inputs of elements And 371,... ,37Msecond inputs of which are connected to the outputs of the respective inverters 321,... ,32Mthe inputs of the latter are connected respectively to the outputs of the respective elements 36 1,... ,36Mthe first inputs of which are connected respectively with a resolution inputs (inputs 1,... ,M) CONDITION, the control input (gate) of the CA connected to the first input element And 33, the output of which is connected with the second inputs of the And elements 361,... ,36Mthe zero input condition (input DC“0”) OUTP is connected with the second input element And 33, a third input connected to the output of the trigger 27, the inlet end of synchronously (input KCK), the CA is connected with a clock input (entrance) of the trigger 26, the information input (D input) which is connected to the power bus, and the input set to zero (log R) - with the release of the trigger 29, the output of the trigger 26 is connected with the information input (input D) flip-flop 27 and the input of the inverter 30, the output of which is connected to the inputs of the installation to zero (inputs R) flip-flops 27, 28, 29, the output of the trigger 27 is connected with the information input (D input) trigger 28, the output of the trigger 28 is connected with the information input (D input) trigger 29, the clock input (input T) OUTP is connected to clock inputs (inputs To) flip-flops 27, 28, 29, the output element 371connected with the second input element And 35, the output of which is connected to the second input of the OR element 38, the first input of the latter is connected with the output element And 34, the output element OR 38, and the outputs of the elements And 372,... ,37Mare clock outputs (outputs T1,... ,TM) MUSTACHE.

Device for GDS works with edusim way. Device for GDS has two modes of operation. The first mode of operation and diagnosis, the second mode of operation.

In the first mode to the inputs of the device for GDS and further inputs UN 2 with a controller that works in conjunction with personal electronic computing machine (the PC), do the following signals: mode selection (input MODE)set to “Log.0”, new address (input), set to zero (input RES), write (log CE), read (input OE), set the RAM or register (input RAM/RG), information (inputs-outputs 0,... ,N). Signal mode selection is also fed to corresponding inputs of a PC 7 and US 10. The new address signal is also supplied to the corresponding input CONDITION 10.

When setting the RAM to the input RAM/RG UN 2 signal “Log.1”.

Used in the device for GDS RAM has a 0,... ,N address inputs, a selection input (CE input), input recording (input WE, input read (input OE) and information inputs and outputs. Allow the RAM is carried out in the presence of low-level signal on its CE input. In the device for GDS input CE RAM is connected to the earth bus. Recording information on the information inputs and outputs of RAM, occurs to him WE signal is “Log.0”, and the SECOND input signal “Log.1”. Reading the information stored in RAM is carried out in the presence of his SECOND input signal “Log.0”, and WE input signal “Log.1”.

In About What We remembered the following parameters digital transmission:

- the value of synchronously (input-output Mn);

- position synchronously (input-output P);

- end of synchronously (input-output CSC);

- end loop (input-output CC).

Before you configure the RAM to the input RES UNIVERSITY 2 signal installation at zero. When this signal installation at zero, received from the output of SCIENCES 2 (output RES) to the appropriate input of the FIRST 5 meters of the positions are in the zero state. The number of counter positions in TH 5 is determined by the number of synchronized digital streams. 0,... ,N output bits 1,... ,M item counters TH 5 are connected, respectively, with 01,... ,N1,... ,0M,... ,NMthe address outputs TH 5.

In setup mode signal “DIR”, received at the corresponding input of the PC 7, the latter is held in the first state. When this signal is first sent from the output 1 PC 7 to the corresponding input of the second switch 9 is switched signals with 01,... ,N1outputs bits RD 5 through the respective inputs of the second switch 9 to the outputs of the last and next to the address inputs of the RAM 1. Thus, in configuration mode, the address inputs of RAM 1 receives signals from the address outputs of the first counter positions TH 5.

Also the signal “DIR”, received at the corresponding input of the remover signals 10, the last comma is range signals new address (input) CONDITION 10 on T 1the yield of the latter. Signals from T1exit CONDITION 10 arrive at T1entrance TH 5 as a clock signal of the first counter positions of the latter.

When configuring RAM 1 information 0,... ,N inputs and outputs of the UNIVERSITY 2 receives information signals settings. The signals Zn, P, CSC, CP with input-output UN 2 are received at the respective inputs and outputs of the RAM 1. Further according to the recording signal, WE arrived at the entrance of RAM 1, the last address corresponding to the zero state of the first counter positions TH 5, memorize the information received on the inputs-outputs of the RAM 1. After that, the new address signal received at the input to the device for GDS and forth through US 10 on T1entrance TH 5, the first counter positions of the latter changes its state by one. Then write data to RAM 1 is performed as described above.

To verify the configuration RAM 1 signal installation at zero received from RES output to the appropriate input TH 5, the first counter positions last set to the zero state. After that, the signal “Log.1”received on the input record (log CE) UN 2 and then WE exit UNIVERSITY 2 to the appropriate input of the RAM 1, the latter is transferred into the read mode. Then the signal “Log.0”received on the input read (input OE) UN 2 and further with the SECOND output of the University of 2 to the corresponding input of the RAM 1 is ativana information from the RAM 1 at address zero of the latter. The signals Zn, P, CSC, CP with input-output RAM 1 go to the appropriate inputs and outputs of the University of 2 and then to the controller PC to compare them with the original. Then the new address signal includes changing the RAM address 1 and read data at the new address in the same way as described earlier.

After you configure and verify the configuration RAM 1 is set up registers memory located in the UNIVERSITY 2. Configuration registers memory allowed signal “Log.0”at the input of RAM/RG UNIVERSITY 2.

In the case of storing in binary code stores the following parameters:

- the number of synchronized transmissions;

- the length of the cycle (in positions).

When this setting and checking its correctness is the same as for the RAM. With output register memorizing UNIVERSITY 2 signals specifying the number of synchronized transmission and the length of the cycle, proceed accordingly on the first 01,... ,N1and the second 02,... ,N2sets the outputs of the UNIVERSITY 2.

Transfer device for GDS in the operation mode signal is “Log.1”, input DIR of the University of 2. This signals “Log.1” and “Log.0”, coming respectively from the output WE write and exit SECOND reading UNIVERSITY 2 to corresponding inputs of the RAM 1, the latter is switched to the read data.

The operation of the device for GDS is the next way. Signals with a clock T1,... ,TMand information And1... , AndMinput device for GDS arrive at the corresponding inputs of the first switch 6. Signals with a clock Ti,... ,TMinput device for GDS go to the corresponding inputs of the CA 10. The clock signal with T1,... ,TMoutputs CONDITION 10 are received at the respective inputs of the FIRST 5 and then to the clock inputs of counters positions of the latter. The number of clock and data inputs of the device for GDS is determined by the number of synchronized digital transmission, set in binary code signals with 01,... ,N1specifies the output state UNIVERSITY 2. These signals are sent to corresponding inputs of a PC 7. The clock signal on T-R input PC 7 come from the corresponding output VA 8. The signal on one of the permissive 1,... ,M outputs PC 7 received at the respective inputs of the first 6, 9 second, third, 11 switches, and CONDITION 10, shall be allowed:

- switching information and clock signals corresponding to digital transmission from the respective inputs of the first switch 6 on its data and clock outputs;

- switching signals to the address outputs of the corresponding item counter TH 5 received at the appropriate address outputs TH 5 and further to the corresponding address inputs of the second switch 9, the address o the last years;

- switching signal having a synchronization received from the f outlet FU 4 to the appropriate input of the third switch 11, to the output of the existence of a synchronization device for GDS for the corresponding digital data;

- using US 10 to carry out the destruction of the clock signal of the corresponding digital data received from a specific input device for GDS to the appropriate input CONDITION 10, in the search mode of synchronism of the transmission.

The address outputs of the second switch 9 is connected to the address inputs of the RAM 1. Thus the address inputs of RAM 1 receives address signals from the outputs of the bits corresponding counter positions TH 5. Clock and data signals of a particular digital data information and clock outputs of the first switch 6 is coming to corresponding inputs of a DC 3. The clock signal from the output of the first switch 6 also enter the corresponding clock input CONDITION 10 and the clock input of the third switch 11.

In the initial state signal to enable output 1 PC 10 address inputs of the RAM 1 through the second switch 9 and the address 01,... ,N1outputs TH 5 connected to the first counter positions TH 5. Signal having a synchronization coming from the f outlet FU 4 to the appropriate input of the third switch 11, communicated by the latter to the output of the availability of synchronization is erway digital transfer (exit F 1device for GDS). Remover signal 10 is in the mode of removal of the clock signals from the T1sign in with appropriate input device for GDS. The clock signal of the first digital data switched by the first switch 6 log T1device for GDS on the clock" inputs (inputs T) US 10, DS 3, and the third switch 11. Information signals of the first digital data switched by the first switch 6 input And1device for GDS on the information input (entrance) DS 3.

The operation of the device for GDS starts with checking synchronization connected digital transmission. The maximum period of checking synchronization equals the length of the transmission cycle and the doubled value of the criterion output from the synchronism. If during the inspection device for GDS came out of synchronism, VA 8 is formed by a clock signal with T-R release of the latest fed to the corresponding input of the PC 7 by changing its status. Then, it verifies whether the synchronization of the next digital transmission. If during the period of checking synchronization was recorded output from the synchronism, the device for GDS goes into search mode synchronism connected digital transmission. The maximum period of search matching is equal to the sum of two values:

1) d is in loop digital transmission, squared;

2) the product of the length of the cycle at twice the value of the criterion exit synchronism.

If during the search for matching synchronization is not found, VA 8 is formed by a clock signal, which, as described earlier, the PC 7 is set to the next state, connecting for analysis the following digital transfer. In the second position 7 PC signal with its enabling output 2 address inputs of the RAM 1 is connected to the address outputs of the second counter positions TH 5, the signal having synchronization is connected to the output f2device for GDS, US 10 is set in the delete mode of the clock signals from the T2the input information and the clock signal of the second digital data (inputs And2and T2device for GDS switched on information and clock outputs of the first switch 6. In a further device for GDS works in the same way as described above. After analyzing the latest digital transmission PC 7 is again installed in the first state and the cycle of checking and searching for synchronization of digital transmission is carried out as described earlier.

The operation of the device for GDS when searching for synchronization of digital transmission is carried out as follows. The signals from the outputs values of synchronously (output Zn), the position of synchronously (output P) and the end C is recombinatio (exit CSC) RAM 1, as well as clock and information signals to corresponding inputs of a DC 3. DS 3 performs elementwise comparison information signals on the positions of synchronously with its values set in the RAM 1, and the formation of a result of comparison of the output response (output IC). In case of coincidence of signals values synchronously its positions defined in the RAM 1, the input information sequence at the output of the response (output IC) DS 3, a signal is generated “Log.1”, and when the mismatch signal “Log.0”. The output signal of the response DS 3 and the output end of synchronously (exit CSC) RAM 1 go to corresponding inputs of FU 4.

Environment the device operates as follows. In the absence of the input of the response signal “Log.1”, i.e. a positive response to the presence of synchronously, reversible counter FU 4 is in the zero state. The output signal from the zero state (output DC“0”) FU 4 may be permitted US 10. When entering the FU inputs 4 positive response and end synchronously with the respective DC outputs 3 and OSU reversible counter FU 4 is installed in the positive mode account and increases its state unit. Thus the output signal from the zero state FU 4 prohibited work MOUSTACHE 10. Thus, when the presence of a signal decode synchronously, reversible accounts the chick FU increases its state unit, in the absence reduces your status on the unit. When the difference signal of the presence and absence of synchronously reaches the value input in synchronism, and a reversible counter FU 4 is set to the maximum state. Thus, the device for GDS switches synchronism, as evidenced by the signal “Log.1” at the output of the availability of synchronization (exit f) FU 4. In this mode, the device for GDS is as long as the difference signal absence and presence of synchronously not reach the criteria value is out of synchronism. When this FU 4 set to the zero state and device for GDS goes into search mode matching, as described above.

The experiments showed that for devices frame synchronization optimal value of the criterion input in synchronism equal to 4, and the criterion value output from the synchronism is 8.

Generating equipment 5 contains counters positions and decoders all cycles. The number of counter positions and decoders all cycles equal to the number of synchronized digital transmission. The length of the cycle is set by the signals in binary code received from the second 02,... ,N2specifying outputs UN 2 0,... ,N specifies the inputs TH 5.

Time analyzer (figure 2) works as follows. Initially checked nalitch the e synchronization of the corresponding digital transmission. When this signal the end of the cycle input of CC time analyzer is supplied to the clock input (entrance) of the first counter 12. After admission to the clock input of the first counter 12 number of signals equal to twice the criterion output from the synchronism, the output of the first counter 12, a signal is generated which, when the clock input (input To the first flip-flop 15, installs it in one state. Thus, the outputs of the first flip-flop 15 is supplied to the control output (output) VA, to the input of the first inverter 18 and the enabling inputs of the first 22 and second 23 elements And. the Signal “Log.0” with the output of the second inverter 18 is supplied to the first input of the second element OR 20. If you are checking the synchronization of the corresponding digital transmission device for GDS came out of synchronism, the entrance to the availability of synchronism (log f) VA and then on the second enabling inputs of the first 22 and second 23 elements And to the second input of the second element OR 20 receives the signal “Log.1”. In this case, the output signal of the second element OR 20, arriving at the inputs setup to zero (inputs R) 13 second, third 14 counters and the second trigger 16, the latter are set in the zero state. Signal the end of the cycle through the open first element And 22 and the third element 21 is supplied to a clock output (output T-R) VA. After that, the signal received is from the output of the inverter 17 through the open by the first and second input of second And gate 23 and the first element OR 19, the inputs setup to zero (inputs R) of the first counter 12 and the first flip-flop 15, the latter are set in the zero state. The clock signal do output VA to the input of the distributor signal changes its state, thereby connecting to validate synchronization the following digital transfer. If when checking the synchronization of the corresponding digital transmission device for GDS came out of synchronism, it goes into search mode matching. On the first and second inputs of the second element OR 20 receives signals “Log.0” respectively with the output of the second inverter 18 and f log VA.

The output signal “Log.0”coming from the output of the second element OR 20 to the inputs of installation in zero second 13, 14 third counter and the second trigger 16 will be allowed to work.

The second counter 13 counts the number of signals the end of the cycle, received at its clock input (input To) CC input VA. Upon reaching the second counter 13 is equal to the number of positions in the loop digital transmission, given in binary code signals with 0,... ,N sets of inputs VA to the corresponding inputs of the second counter 13, the output of the last signal is formed, which is fed to an enable input (input EC) trigger 16. Further signal the end of the cycle received on the clock input (input To) the trigger 16,the latter is set in the one state, and its output signal received at the enable input (input EC) of the third counter 14, allows his work. After receipt of the clock input (entrance) of the third counter 14 signals the end of cycles equal to twice the value of input in synchronism, the output of the third counter 14, a signal is generated which indicates that synchronization is not found. When the output signal of the third counter 14 is fed to the first inputs of the third 24 and fourth 25 items And allowing their work. Signal the end of the cycle through the open third element 24 And the third element 21 is supplied to a clock output VA and next to the appropriate input PC by changing its status, thereby allowing checking for synchronization and search for matching in the next digital transmission. After that, the signal received from the output of the inverter 17, through the open fourth element And 25 and the second element OR 20 to the inputs of installation in zero second 13 and third 14 meters, and the second trigger 16, the latter are set in the zero state. The same signal received through the element OR 19 to the inputs setup to zero first counter 12 and the first flip-flop 15, the latter also set to the zero state.

If in the process of finding matching on f input VA appeared to signal the presence of synchronism, as described wound is, the first 12 and second 13 and third 14 counters, the first 15 and second 16 triggers are set in the zero state, and the output of the third element 21 is formed by a clock signal with T-R output VA is supplied to the corresponding input of the PC, installing it in the next state, allowing checking for synchronization and search for matching in the next digital transmission.

Remover signals (figure 3) works as follows. If the test digital transmission in the presence of synchronization has not been confirmed, the device for GDS goes into search mode matching of the corresponding digital transmission. Search matching is carried out as follows. On each cycle of the digital transmission is the recording of information signals on the positions of synchronously and comparing them with predetermined RAM. The position of synchronously specific digital transmission are determined by the state of the corresponding item counter, the address outputs of which are connected to the address inputs of RAM. If during the cycle digital transfer singlecompany not found, using remover signals are missing any of the clock signal of the corresponding clock input of counter positions, and the specified counter changes its phase in relation to the phase of the digital transmission. The decree is hydrated operating procedure is as long until it finds the first singlecompany. After which prohibits the destruction of clock signals and checking the availability of synchronously on the respective positions of digital transmission. In case of fulfillment of criterion input in synchronism device for GDS switches synchronism, which indicates compliance with the phase of the counter positions TH phase a particular digital transmission.

When searching for a synchronism to the input control (input) CONDITION from the corresponding output VA signal “Log.1”, and the input initial state (input DC“0”) CONDITION from the corresponding output of the FU also receives the signal “Log.1”. The signals from the inputs and DC“0” remover of signals respectively to first and second inputs of the element I, allowing his work. One of the permissive inputs (inputs 1,... ,M) CONDITION from the corresponding output of the PC signal “Log.1”. This signal, when the first input of one of the elements 361... , And 36Mallows his work. On clock inputs (inputs T1,... ,TM) The CA receives signals from the respective inputs of the device for GDS. On the input end of synchronously (input KCK), the CA signal from the corresponding output of RAM. This signal is doing with the KSK sign CONDITION on the clock input (input To) the trigger 26, installs it in one state. The single signal level output from the rigger 26 is supplied to the information input (D input) trigger 27 and through an inverter 30 - the inputs setup to zero (inputs R) flip-flops 27, 28, 29, allowing their work. On clock inputs (inputs To) flip-flops 27, 28, 29 receives signals from clock input (input T) US connected with the corresponding output of the first switch. Triggers 27, 28 negative front of the clock signals are set sequentially in one state, and then, the positive front of the clock signal in one state sets the trigger 29. Then the output signal of the trigger 29 is set in the zero state of the trigger 26, which output signal through an inverter 30 sets the initial state of the trigger 27, 28, 29. After you install the trigger 27 in one state to the third input element 33 receives the signal “Log.1”, which with the release of the latest fed to the second inputs of the And elements 361... , And 36m. Output is enabled by the first input of the corresponding element 361...And 36mthe signal of the logic unit is fed to the input of the corresponding inverter 321,... ,32m, the output of which a signal is generated “Log.0”prohibiting the second input operation corresponding element 371... , And 37mthereby preventing the passage through the element clock signal corresponding digital data from one clock T1,... ,TMinputs MUSTACHE to fit the existing its output. When the signal “Log.1” input DIR MUSTACHE permitted work item And 35, thereby allowed the passage of the clock signal, the first digital data from the output element And 371through the element And 35 and the element OR 38 on the clock T1the output of the AC. When configuring the signal “Log.0” input DIR US through the inverter 31 may be permitted element And 34, thereby allowed the passage of the signal from input a new address (input) CONDITION through the element And element 34 and 38 on the clock T1exit CONDITION.

For the technical realization of the device for GDS used static random access memory device imported type KM68257CJ-15 firms and the SEC programmable logic integrated circuit XC4020XLA by XILINX.

The present invention allows one device cyclic synchronization band digital transmission of identical structure while reducing hardware costs, power consumption and improve the reliability and noise immunity, because for frame synchronization band digital transmission uses a single RAM instead of N similar RAM. Use one RAM also allows to reduce the number of printed conductors and to increase their effective area, thereby reducing the resistivity and the disruption of connections between the elements of the device.

p> Sources of information

1. RF patent №2019046, H 04 L 7/08.

2. RF patent №2136111, H 04 L 7/08.

3. Levin PS, Plotkin M.A. Digital transmission systems. M.: Radio and communication. P.101-102, RES.

4. RF patent №2187210, H 04 L 7/08.

1. The device group for frame synchronization, containing random access memory (RAM)device settings (UN), the decoder synchronously (DS), environment unit (FU), generating equipment (TH), and the selection input of RAM is connected to the earth bus and the inputs of the write and read from the corresponding outputs of the UNIVERSITY, the input mode selection, new address, set to zero, write, read, set the RAM or register storing information 0,...,N inputs and outputs which are the corresponding inputs of the device group for frame synchronization (GDS), input-output values synchronously, the position of synchronously, the end of synchronously RAM connected to respective inputs and outputs of the UNIVERSITY and to the corresponding inputs DC output response which is connected with the respective input FU, the input end of synchronously which is connected with the corresponding output of RAM, input-output loop end of which is connected with the respective input-output state UNIVERSITY, the second 02,...,N2specifies the outputs of which are connected respectively with the sets 0,...,N inputs, the input set is Cai to zero which is connected with the corresponding output of the UNIVERSITY, the outputs of all cycles TH are the corresponding outputs of the device for GDS, characterized in that the input of the first, second and third switches, directional signals (PC), time analyzer (VA) and the remover of signals (CA), and clock inputs and an information input device for GDS connected to respective inputs of the first switch, the clock output of which is connected to the corresponding inputs DS, US, and the third switch, the information output of the first switch is connected with the respective input DC output signal the end of the cycle the RAM is connected with the respective input VA, 0,...,N specifies the inputs of which connected with 02,...,N2specifies the outputs of the UNIVERSITY, the first 01,...,N1specifies the outputs of which are connected with 0,...,N specifies the inputs of the PC clock output VA is connected with the respective input PC, 1,...,M allow the outputs of which are connected to the corresponding inputs of the first, second and third switches and inputs MOUSTACHE, 0,...,N address outputs of the second switch is connected to the corresponding inputs of RAM, the output of the availability of synchronization FU is connected to the corresponding inputs of the third switch and the VA, the control output of which is connected with the respective input CONDITION, the clock outputs of which are connected to the corresponding inputs, selects the PC mode and the CONDITION connected with match the named input device for GDS, input the new address which is connected with the corresponding input CONDITION, the input end of synchronously which is connected with the corresponding output of RAM, the output of the zero state FU connected with the respective input CONDITION, the clock input of which is connected to respective inputs of the device for GDS, the address outputs of the FIRST is connected with the corresponding inputs of the second switch, the outputs of the presence of synchronization of the third switch are the corresponding outputs of the device for GDS.

2. The device according to claim 1, characterized in that the timing analyzer includes first, second and third counters, the first and second triggers, the first and second inverters, the first, second and third elements OR first, second, third and fourth elements And the entrance to the availability of synchronization, the input end of the cycle that specifies the inputs, a control output and a clock output, and input availability synchronization is connected to a second input of the second element OR the second inputs of the first and second elements And the input end of the loop connected to the clock inputs of the first, second and third counters, and the second trigger, and also to the input of the first inverter, the third input of the first element And the second input of the third element And the output of the first counter connected to a clock input of the first trigger information whose input is connected to the power bus, the inputs installed in Nol the first counter and the first flip-flop connected to the output of the first element OR the first input and the third input of the second element OR is connected to the output of the fourth element And the output of the first trigger is a control output time analyzer, and is connected to the input of the second inverter and to the first inputs of the first and second elements And the output of the second inverter is connected to the first input of the second element OR the output of which is connected to the inputs setup to zero second, the third counter and the second trigger that sets the inputs of the second counter are specifying the input time analyzer, the output of the second counter is connected with the allow input of the second trigger, the output of which is connected with the allow input of the third counter, the output of the third the counter is connected with the first inputs of the third and fourth elements And the output of the first inverter is connected to a second input of the fourth element And the third input of the second element And whose output is connected to the second input of the first element OR the outputs of the first and third elements And are connected with the inputs of the third element OR whose output is clocked out time analyzer, the information input of the second trigger is connected to the power bus.



 

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