Frame synchronization device

FIELD: digital communications;

SUBSTANCE: proposed device is used for frame synchronization of digital time-division multiplex data transmission systems and incorporates provision for synchronizing data transmission class at dispersed sync combination of group signal and for implementing parallel search for synchronism. Device has first, second, and third random-access memories, storage register, decoder, distributor, generator equipment, phasing unit, flip-flop, first and second inverters, adjusting unit, first, second, and third inverters, first, second, third, fourth, and fifth AND gates, first and second OR gates.

EFFECT: enlarged functional capabilities.

1 cl, 2 dwg

 

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal.

A device for frame synchronization [1], comprising a memory device, the device configuration and diagnostics, the storage device criteria input in synchronism, the storage device criteria exit synchronism, the decoder synchronously, environment unit, generating equipment, inputs and outputs of the device.

This device allows you to sync one device of a large number of digital transmission of information.

However, this device has the following disadvantage. Realization of the sequential search synchronization increases the time of entering into synchronism.

The main time when searching for synchronization is determined by the time of the first synchronously.

The closest to the technical nature of the claimed invention is selected as a prototype device for frame synchronization [2], containing the decoder, generating equipment, environment unit, random access memory, a distributor, a trigger inverters, register memory, in addition, the device contains elements OR, AND, and to set the device.

the shown device implements a parallel search of synchronism when distributed synchronously.

The disadvantage of this device is that it is impossible for one and the same device to synchronize the various transmission information with asynchronous merging of digital streams in a distributed synchronously and implementation of parallel search of synchronism.

The aim of the invention is the extension of functionality by providing one device group is synchronized transmission with asynchronous merging of digital streams when the dispersed synchronously group signal, and implementation of parallel search of synchronism.

This goal is achieved by the fact that in the device for frame synchronization, containing the first random access memory (RAM), a register memory (RA), the decoder, generating equipment (TH), environment unit (FU), the distributor, the trigger, the first and second inverters, and a clock input devices for frame synchronization (CA) is connected to the corresponding inputs of the distributor and TH, address outputs 1, ..., m and 1, ..., n which are relevant address outputs of the device for the CA, the address outputs 1, ..., m TH is also connected with the corresponding address inputs of the first RAM, I/o 1, ..., N which are connected to the corresponding inputs/outputs RA, the information input of which is the information input device for CA and outputs connected to respective inputs of the decoder, the output of which is connected to the corresponding inputs of the FIRST and FU, the zero output state of which is connected with the corresponding input, and the output of the availability of synchronization is output having a synchronization device for a CA, the output of pulse generator TH is connected to the corresponding input of the distributor, the first and third outputs of which are connected respectively with a clock input and the input set to zero trigger, and the second output to the clock input of RH, input read/write which is connected to the output of the first inverter, the information input trigger is connected to the power bus, the outputs of the first and second inverters connected respectively to the inputs of the reading and writing of the first RAM, according to the invention introduced the second and third RAM device configuration and diagnostics (UND), with third, fourth and fifth inverters, the first and fifth elements And the first and second elements OR, and address inputs 1, ..., m of the second RAM connected to respective outputs, the address outputs 1, ..., n which are connected to the corresponding inputs of the third RAM inputs select the first, second and third RAM connected to respective outputs of UND, outputs, 3.0, ..., ZM, PO, ..., PN which are connected to the corresponding inputs of the decoder, the input read second and third RAM connected between the Wallpaper and the output of the fourth inverter, recording inputs of the second and third RAM connected with each other and with the output of the fifth inverter, the input/output position of the end of the cycle and the position of synchronously in the cycle of the second RAM connected to respective inputs/outputs of the UND, the input/output end positions of the super-frame, which is connected with the corresponding input/output of the third RAM, input/output position of the end of the cycle of the second RAM is connected with the corresponding input and output devices for CA entrance/exit position synchronously in the cycle of the second RAM is connected also to the first input of the fifth element And the input/output position of the end of the third multiframe RAM connected with the appropriate output device for the CA, the input and the second input of the fifth element, And a third input connected to the third output of the distributor, the fourth output of which is connected to a second input of the fourth element And the input of the mode selection device for the CA is connected to the corresponding inputs UND and the CS input of the third inverter and the first input of the second and fourth elements And the output of the read-UND connected to the input of the fourth inverter and the second input of the first element And the first input and the first input of the third element And is connected to the output of the third inverter, the output records UND connected to the input of the fifth inverter and a second input of the third element And whose output is connected to the first input of the m second element OR their second input connected to the output of the fourth element, And the output to the input of the second inverter, the output of the trigger is connected with the second input of the second element And whose output is connected to the second input of the first element OR the first its input connected to the output of the first element, And the output to the input of the first inverter, the outputs of clock cycles settings and options are in zero UND connected to respective inputs, the output of the fifth element And is connected to the input end of synchronously FU, input the new address, set in the zero state, write, read, configuration, RAM or registers, selection custom RAM, the information input/output device settings for the CA is connected to the corresponding inputs UND.

The novelty of technical solutions is the use in the inventive device of new circuit elements of the second and third memory devices, device configuration, and Troubleshooting, third, fourth and fifth inverters, the first and fifth elements And the first and second elements OR.

Thus, the invention conforms to the criterion "novelty".

Analysis of the known technical solutions in the study and related fields allows to conclude that the introduced functional units known. However, their introduction into the device for frame synchronization with the specified relationship p is idet this new device properties. Introduced functional units interact in such a way that allow for a significant increase in hardware cost to extend its functionality, providing one device synchronization band digital transmission of information when the dispersed synchronously and implementation of parallel search of synchronism.

Thus, the invention meets the criterion of "inventive step", as it is for the expert is not obvious from the prior art.

The invention can be used in digital transmission systems with asynchronous merging of digital streams.

Thus, the invention meets the criterion of "industrial applicability".

Figure 1 presents the structural electrical diagram of the device for frame synchronization, figure 2 is an electric diagram of the device configuration and diagnostics.

Device for frame synchronization (figure 1) contains the first random access memory (RAM) is 1, the second RAM 2, the third RAM 3, the register memory (RH) 4, a decoder 5, the valve 6, the generating equipment (TH) 7, environment unit (FU) 8,device configuration and diagnostics (UND) 9, the trigger 10, the first and fifth inverters 11, 12, 13, 14, 15, between the first and fifth elements And 16, 17, 18, 19, 20, the first and second elements OR 21, 22, and the clock input (input T) indicates istwa for frame synchronization (CA) is connected to the corresponding inputs of the distributor 6 and 7, the address outputs 1, ..., m and 1, ..., n which are relevant address outputs of the device for the CA, the address outputs 1, ..., m-TH 7 are also connected to respective address inputs of the first RAM 1, the inputs/outputs 1, ..., N which are connected to the corresponding inputs/outputs RZ 4, information logon (logon) which is an information input device for CA, and outputs (outputs 0, ..., N) are connected to the corresponding inputs of the decoder 5, the output (output IC) which is connected to the corresponding inputs TH 7 and FU 8, the zero output state (output DS"0") connected with the respective input TH 7, and the output of the availability of synchronization (exit f) is the output of the existence of a synchronization device for the CA exit (exit G) pulser TH 7 is connected to the corresponding input of the distributor 6, the first output (output of PC1) and the third exit (exit RS) which are connected respectively with a clock input (input) and input set to zero (log R) flip-flop 10, and the second exit (exit RC) a clock input (entrance To) RZ 4, the input to the read/write (input OE/WE) which is connected to the output of the first inverter 11, an information input (input D) flip-flop 10 is connected to the power bus, the outputs of the first 11 and second 12 inverters are connected respectively to the inputs of a read (input OE) and write (log CE) of the first RAM 1, the address inputs 1, ..., m of the second RAM 2 is connected with westwoodone outputs TH 7, the address outputs 1, ..., n which are connected to the corresponding inputs of the third RAM 3, the selection input (inputs CE) of the first 1, second 2 and third 3 RAM connected to respective outputs UND 9, outputs, 3.0, ..., ZM, PO, ..., PN which are connected to the corresponding inputs of the decoder 5, the inputs read inputs OE) of the second 2 and the third RAM 3 are connected with the output of the fourth inverter 14, recording inputs (inputs WE) second 2 and third 3 RAM connected with each other and with the output of the fifth inverter 15, the inputs/outputs of the position of the end of the cycle (input/output CC) and the position of synchronously in a loop (input/output UCS) of the second RAM 2 is connected to the corresponding inputs/outputs UND 9, the input/output position of the end of the multiframe (input/output KSC) which is connected with the corresponding input/output of the third RAM 3, the input/output position of the end of the cycle of the second RAM 2 is connected with the corresponding input of the TH 7 / output device for the CA, the input/output position of synchronously in the cycle of the second RAM 2 is connected also to the first input of the fifth element And 20, the input/output position of the end of the third multiframe RAM 3 is connected with the respective output device for CA entrance TH 7 and a second input of the fifth element And 20, a third input connected to the output RC distributor 6, the fourth exit (exit RC) which is connected to a second input of the fourth element And 19, the selection input mode(input MODE) device for the CA is connected to the corresponding inputs UND 9 and 7, the input of the third inverter 13 and the first input of the second 17 and 19 fourth elements And the output read (output OE) UND 9 is connected to the input of the fourth inverter 14 and the second input of the first element And 16, the first input and the first input of the third element And 18 is connected to the output of the third inverter 13, the output write (output WE) UND 9 is connected to the input of the fifth inverter 15 and the second input of the third element And 18, the output of which is connected to the first input of the second element OR 22, its second input connected to the output of the fourth element, And 19, and the output with the input of the second inverter 12, the output of the trigger 10 is connected to a second input of the second element And 17, the output of which is connected to the second input of the first element OR 21, its first input connected to the output of the first element And 16, and output to the input of the first inverter 11, the outputs of clock cycles settings (output T) and setting to zero (output RES) UND 9 is connected to the corresponding inputs TH 7, the output of the fifth element 20 is connected to the input end of synchronously (input CSC) FU 8, input the new address (input), installation in the zero state (input RES), write (log CE), read (input OE), configuration, RAM or registers (input RAM/RG), select custom RAM (input A), the information input/output settings (inputs/outputs 0, ..., N) device for the CA is connected to the corresponding inputs UND 9.

Device settings diagnostiki (UND), presented in figure 2, contains from 23 to 32 inverters, from 33rd to 49th St items And 50 on the 52nd elements OR distributor 53, a storage device 54 and 55, controlled valves 56-0, ..., 56-N and 57th in the 62nd, unmanaged valves 63-0, ..., 63-N and 64 to 66, and the input DIR UND 9 is connected to the second inputs of the elements 50, 51, 52 and the input of the inverter 23, the output of which is connected to the output of the first RAM (exit SE) UND 9, with the second inputs of elements And 33, ..., 38, 41, and the first input of the OR element 50 is connected with the output element And 36, and the output - output read (output OE) UND 9, with the input of the inverter 28 and the first inputs of the And elements 41, 44, 45, 46, admission TO UND 9 connected to the first input element And 33 whose output is the output cycle setting (output T) UND 9, and connected to the first input element And 42 connected to its output with a clock input (input T) of the distributor 53, entry RES UND 9 connected to the first input element And 34 whose output is the output setup to zero (output RES) UND 9, and is connected with the input set to zero (input RES) distributor 53, entrance WE UND 9 connected to the first input element And 35 whose output is the output write (output WE) UND 9, and connected to the first input element And 43, the output of which is connected to clock inputs (inputs) triggers storage devices 54 and 55, the input OE UND 9 is connected to the first photomanagement And 36, input RAM/RG UND 9 is connected to the input of the inverter 24 and the first input element And 38, the output of which is connected with the second inputs of the And elements 39, 40, 47, the first input element And 47 connected to the output of the inverter 28, and the output - control inputs of the controllable valves 57 St to 59th, the output of inverter 24 is connected to the first input element And 37, the output of which is connected with the second inputs of the And elements 42, 43, 44, entry And ATC 9 is connected to the input of the inverter 25 and the first input element And 40 its output connected with the second input element And 46 and the first input of the OR element 52, an output connected to the input of the inverter 27, the output of which is the output of the selection RAM 3 (output cèze) UND 9, information inputs/outputs (inputs/outputs 0, ..., N) configuration UND 9 is connected to the outputs of the controllable valves 56-0, ..., 56-N and inputs unmanaged valves 63-0, ..., 63-N, the outputs of which are connected to the appropriate information inputs (inputs D) triggers the storage devices 54, 55 and inputs controllable valves 57, 58, 59, the output of the inverter 25 is connected to the first input element And 39, with its output connected with the second input element And 45 and the first input of the OR element 51, an output connected to the input of the inverter 26, the output of which is the output of the selection RAM 2 exit SE), the output element And 44 connected to stormi inputs of elements And 48, 49, the outputs of which are connected respectively with the input of the mi inverters 31,32, and the outputs of the latter are connected respectively to the control inputs of the controllable valves storage devices 54, 55, the output element And 41 is connected with the control inputs of the controllable valves 56-0, ..., 56-N, the output element 45 is connected to the input of the inverter 29 is connected by its output to the control inputs of the controllable valves 60,61, the output element 46 is connected to the input of the inverter 30 is connected by its output to the control input of the control gate 62, the output 1 of the distributor 53 connected to the first input element And 48 and enable inputs (inputs EC) triggers the storage device 54, the output 2 of the distributor 53 connected to the first input element And 49 and enable inputs (inputs EC) triggers the storage device 55, the same outputs controllable valves storage devices 54, 55 and controllable valves 60, 61, 62 are interconnected and the inputs of the controllable valves 56-0, ..., 56-N, input/output CC UND 9 is connected to the output of the controlled valve 57 and the input unmanaged gate 64, the output of which is connected to the input of the control valve 60, the input/output UCS UND 9 is connected to the output of the controlled valve 58 and the input unmanaged gate 65, the output of which is connected to the input of the control valve 61, the input/output KSC UND 9 is connected to the output of the controlled valve 59 and the input unmanaged gate 66, the output of which is connected to the ode controlled valve 62, the outputs of the respective triggers the storage device 54 are connected to the outputs of the values of synchronously (outputs Z, ..., .N) UND 9, the outputs of the respective triggers the storage device 55 is connected with a resolution outputs (outputs R, ..., P.N) UND 9.

Device for frame synchronization works as follows. Device for frame synchronization (CA) has two modes of operation. The first mode of operation and diagnosis, the second mode of operation. In the first mode, the input device settings and diagnostics (UND) 9 receives signals from the controller working in conjunction with the personal electronic computing machine (PC). Mode settings and diagnostics allowed the signal Log."0", which is fed to the input mode selection (input DIR) CA and next to the appropriate input UND 9.

In UND 9 the output signal from the inverter 23 is allowed the use of elements And 33, ..., 38, 41. Also the output signal from the inverter 23 received through the output SE UND 9 to the corresponding input of the first RAM 1, prohibited his work. Outputs 1, ..., N of the first RAM 1 is set to the third state. Setting a second 2 and third 3 RAM allowed by the signal Log."1 coming from the input RAM/RG devices for the CA via a corresponding input UND 9 to the first input element And 38, and the signal Log."0", coming through an inverter 24 to the first input element And 37 are allowed to configure storage devices 54 and 55. When setting up the second and third RAM 2.3 device for the CA, as well as storage devices 54,55 UND 9 controlled valves 56-0, ..., 56-N, 60, 61, 62 UND 9, and managed valves storage devices 54, 55 AND 9 are closed by signals on their control inputs and controlled valves 57, 58, 59 are open. Thus the outputs of the closed controllable valves are in the third state. When setting up the alarm Log."0" from the SECOND input device for the CA is supplied to the corresponding input UND 9 and then through the element And 36, item, OR 50 and output OE UND 9 on the input side of the inverter device 14 for CA. The Signal Log."1", coming from the output of the inverter 14 to the inputs OE second and third RAM 2, 3, the latter are set in the write mode.

Setting a second RAM 2 is permitted by the signal Log."0", coming from the input device to the CA via a corresponding input UND 9, the inverter 25, the And gate 39, the element 51, the inverter 26 and the output SE UND 9 to the input CE of the second RAM 2.

The configuration of the third RAM 3 is permitted by the signal Log."1"coming from the input device to the CA via a corresponding input UND 9, item 40 item OR 52, the inverter 27 and the output cèze UND 9 to the input CE of the third RAM 3.

Before setting up the second 2 and third 3 RAM devices for CA and storage devices 54,55 UND 9 input RES of the device for the CA to the appropriate input UND 9 and further to the input element AND 34 UND 9 will occupait pulse signal of positive polarity. The signal output element 34 And is fed to the input RES of the distributor 53, setting it to zero state. The signal output element 34 And is output RES UND 9 and further to the input RES ST 7, by setting the loop counters and multiframe last in the zero state.

When setting up the second and third RAM 2, 3 configuration data from the inputs/outputs 0,1 device for the CA through the appropriate inputs/outputs 0,1 UND 9 act respectively to the inputs of unmanaged valves 63-0, 63-1. Output unmanaged valve 63-0 these settings are sent to the input of open controllable valves 57 and 59. Output unmanaged gate 63-1 these settings are sent to the input of an open controlled valve 58. With outputs controllable valves 57, 58 configuration data via the inputs/outputs of CC and PSC UND 9 arrive at the respective inputs/outputs of the second RAM 2. With the output controlled valve 59 configuration data through the input/output KSC UND 9 enter the corresponding input/output of the third OSU.

After that, the signal Log."1" records received from input devices WE CA through the corresponding input UND 9, the And gate 35, the output WE UND 9, the inverter device 15 for the CA to the inputs WE second 2 and third 3 RAM, custom RAM at address zero recorded data settings.

Then the signal Log."1"received from input devices for the CA through with testwuide entrance UND 9, the element 33 and the output VT UND 9 to the input of TN TH 7, the loop counters and multiframe last change status on the unit. Next, write the data to a new address in a custom RAM is the same as described earlier.

After setting the RAM to determine whether it is correct, the setting signal in the zero state, piped RES TH 7, as described earlier, the loop counters and multiframe are in the zero state. Then to the input of the read SECOND device to CA and then to the appropriate input UND 9 signal Log."1". The signal received from the output element And 41 on the control inputs of controllable valves 56-0, ..., 56-N, opens the latter. Also managed open the valves 60 and 61 of the signal at their control inputs from the output of the inverter 29 to verify that the settings for the second RAM 2, or open a controlled valve 62 a signal received at its control input from the output of the inverter 30 when the correctness of the configuration of the third RAM 3. Managed the valves 57, 58, 59 are closed by a signal at their control inputs with the output element And 47. Managed valves storage devices 54, 55 remain closed. The signal is also read from the output element OR 50 UND 9 is supplied to its output first and then through the inverter device 14 for CA - on inputs TH second and retigo RAM 2, 3. The signals from the inputs/outputs of CW and PSK second RAM 2 and input/output KSC third RAM 3 are received at the respective inputs/outputs UND 9.

When checking the correctness of the configuration of the second RAM 2 signals from the inputs/outputs of CC and PSC UND 9 respectively through unmanaged valves 64, 65, managed valves 60, 61, and managed valves 56-0, 56-1 arrive at the inputs/outputs 0,1 UND 9 and then through the corresponding input/output device for the CA - in the controller PC to compare them with the original signals. Further according to the signal, as described earlier, a change of address RAM 2 and reading its data. The result of the determine the correct configuration of the RAM 2 is displayed on the display PC.

When checking the correctness of the configuration of the third RAM 3 signals from input/output KSC UND 9 through unmanaged valve 66 operated valves 62 and 56-0 arrive at the entrance/exit 0 UND 9, and further work is carried out as described in validating the configuration of the second RAM 2.

Configuring storage devices 54, 55 UND 9 is permitted by the signal Log."0", coming, as mentioned previously, the input RAM/RG devices for CA. This allowed the use of elements And 42, 43, 44. The work of controllable valves storage devices 54, 55 prohibited by signals coming respectively from the outputs of the inverters 31 and 32. The valve 53 is in n the left-hand condition, allowing the output signal 1 triggers the storage device 54. As described earlier, the work of controllable valves is prohibited. Configuration data from the inputs 0, ..., N devices for CA go through the appropriate inputs UND 9 and through unmanaged valves 63-0, ..., 63-N on informational inputs triggers the storage device 54. Further according to the recording signal received from the input WE UND 9 through the elements And 35, 43 on the clock inputs of flip storage device 54, last remember these settings. Further according to the signal received from input TO UND 9 through the elements 33, 42 on the clock input of the distributor 53, the latter changes its state, prohibiting data recording configuration triggers the storage device 54 and allowing the write data setup triggers the storage device 55. The record is the same as in the storage device 54.

To verify the correct configuration of storage devices 54, 55 signal input RES UND 9 received through the element And 34 to the input RES of the distributor 53, the latter is set in the zero state, allowing the output signal 1 work element 48. Next, when the signal is read SECOND, piped TH UND 9, open controlled valves of the storage device 54 and managed valves 56-0, ..., 56-N, and the controlled valves of the storage device 55 and the control which caused the valves 57, 58, 59, 60, 61 are closed. Data outputs controllable valves of the storage device 54 receives at respective inputs of controllable valves 56-0, ..., 56-N. Further work is also carried out as described earlier. Then the signal received at the input ON the UND 9, the distributor 53 changes its state, allowing validation of the configuration of the storage device 55. Further work is similar to that described previously.

In configuration mode and diagnostics (check correct settings) on the clock input of the loop counters and multiframe TH 7 receives the output signal of the HS UND 9, and the operation mode is output T device for the CA.

The transfer device for the CA mode is performed by the signal Log."1", arriving at its input DIR. When this signal Log."0", outputs of SE, SE, cèze UND 9 on the CE inputs of the first, second and third RAM 1,2,3, allowed the use of the latter, and the signal Log."1 and the Log."0", coming respectively from outputs of the first and WE UND 9 through the inverters 14 and 15 to the inputs of the first and WE are second 2 and third 3 RAM, the latter are set in the read mode.

To clock signals from the input T of the device for the CA to the input T TH 7, the loop counter is the last counting position in the cycle, and the multiframe counter - the number of cycles in digital transmission. The number of positions in the cycle set signal is scrap, coming from the output of the CC of the second RAM 2 to the appropriate input TH 7, upon receipt of which the count cycle TH 7 positive front of the clock signal is set to the zero state (synchronous reset). The signal CC also enables the counter multiframe, and upon receipt of the next clock signal multiframe counter changes its state. The number of cycles in the multiframe is set by a signal from the output KSC third RAM 3 corresponding input TH 7. Upon receipt of this signal, and the signal input of CC ST 7, the counter performs multiframe synchronous setting in the zero state. The signals from outputs 1, ..., m bits of the counter cycle TH 7 go to corresponding inputs of bits of the first 1 and second 2 RAM, and the signals from outputs 1, ..., n bits of the multiframe counter TH 7 - on the input bits of the third RAM 3. The clock signal also arrives at the clock input T of the distributor 6, the other input of G which receives signals from the output of the pulse generator TH 7. The frequency of the pulse generator are selected in such a way that during the period of the clock signal received at clock input of the distributor 6, the latter formed a distributed sequence of PC1, RS, RSZ, RS. Information signals from input And device for the CA, enter the corresponding input register of saponi the project (RP) 4. The signal received from the output of PC1 of the distributor 6 to the clock input To the trigger 10, the latter is set in one state, since the information input On this trigger is connected to the power bus. The output signal from trigger 10 through the open signal DIR element And 17, the And gate 21 and the inverter 11, received on the SECOND input of the first RAM 1 and input OE/WE, RH 4 sets the first RAM 1 read mode, and RZ 4 - write. Read signals recorded in the first RAM 1 at the corresponding address in the previous cycle, outputs of 1, ..., N of the first RAM 1 to corresponding inputs of RA 4, the output signal RS distributor 6 are memorized respectively in the digits 1, ..., N, and zero discharge to remember the current information signal from the information input And device for CA. The signal received from input RHS of the distributor 6 to the input set to zero trigger 10, last set to the zero state. While the first RAM 1 is set in the recording mode, and RZ 4 - read mode. On a signal received from the output RS distributor 6 through the open signal DIR element And 19, the element OR 22 and the inverter 12 to the input WE first RAM 1 in the last remembered the signals received from the digits 0, ..., N-1 RH 4 respectively through his 1, ..., N outputs to the inputs 1, ..., N of the first RAM 1. Thus, the work per the CSO RAM 1 in cooperation with the work of the AG 4 can be represented as the work of the M shift registers, where M equals the number of positions in the cycle, and the bit width of each register is equal to the number N, where N is the number of cycles in the multiframe.

RH 4 is a bidirectional group of inputs/outputs and unidirectional group outputs. Bidirectional inputs/outputs are connected to the inputs/outputs of the first RAM 1 and the unidirectional outputs to the corresponding inputs of the decoder 5. With outputs bits RH 4 current information signal and the signals read from the first RAM 1, proceed to the inputs 0, ..., N decoder 5. The inputs z0, ..., ZM decoder 5 receives from the corresponding UND 9 signal values synchronously. As the zero position loop can be characters as synchronously, and special characters, as well as in connection with a different number of cycles in the multiframe for different types of digital transmission to the inputs P0, ..., PN decoder 5 from the corresponding UND 9 receives signals that allow the work places, which are symbols of synchronously. The output signal of the SC decoder 5 receives at respective inputs TH 7 and FU 8. Until the output of the decoder 5 signal positive response FU 8 is in the zero state, allowing the signal zero state Log."1", coming from the output DS"0" FU 8 on the appropriate input TH 7, the installation in the first state of the loop counter and install at a maximum the status counter multiframe, and the first positive signal response at the output of the decoder 5 leading edge of the next clock pulse, the loop counter is set in the first state, and the multiframe counter - in maximum condition. The first signal of the positive feedback reversible counter FU 8 translated from zero in the first state, prohibiting signal Log."0" at the output DS of"0" for further installation of smart meters, TH 7, when the signal of the positive feedback, the output of the decoder 5. Now, when the coincidence in time of the signals a positive response and signal the position of synchronously in a loop and signal the end of the multiframe received at the first and second inputs of the element 20, the output signal RS distributor 6, received on the third input element 20, the output signal of the latter in the reversible counter FU 8 is added to the unit, and if the mismatch is subtracted. Signal position synchronously in a loop is formed at the output of the UCS of the first RAM 1 at the zero value of the signals at its address inputs.

When the difference between the number of positive and negative feedback reaches the value input in synchronism, the device for the CA enters the mode of synchronism, as evidenced by the signal Log."1" at the output f of the device for the CA. In this mode, the device for the CA is as long as the difference in the number of negative and positive feedback or suggestions is s will not reach the criteria value is out of synchronism. When this FU 8 is set in the zero state, and the synchronizer enters the search mode matching, as described earlier.

For the technical realization of the device for frame synchronization used static memory (RAM) imported type S (firm CYPRESS SEMICONDICTOR) and user programmable logical integrated circuit type XC 3195 (firm XILINX).

The present invention allows to extend the functionality by providing one device synchronization class transmission information distributed by synchronously and implementation of parallel search of synchronism.

Sources of information

1. RF patent № 2187210, H 04 L 7/08.

2. RF patent № 2190304, H 04 L 7/08, H 04 J 3/06.

Device for frame synchronization, containing the first random access memory (RAM), a register memory (RA), the decoder, generating equipment (TH), environment unit (FU), the distributor, the trigger, the first and second inverters, and a clock input devices for frame synchronization (CA) is connected to the corresponding inputs of the distributor and TH, address outputs 1, ..., m and 1,..., n which are relevant address outputs of the device for the CA, the address outputs 1, ..., m TH also connected to respective address inputs of parvulos, inputs/outputs 1, ..., N which are connected to the corresponding inputs/outputs RH, information input by the information input device for CA, and outputs connected to respective inputs of the decoder, the output of which is connected to the corresponding inputs of the FIRST and FU, the zero output state of which is connected with the corresponding input, and the output of the availability of synchronization is output having a synchronization device for a CA, the output of pulse generator TH is connected to the corresponding input of the distributor, the first and third outputs of which are connected respectively with a clock input and the input set to zero trigger, and the second output clock entrance RH, input read/write which is connected to the output of the first inverter, the information input trigger is connected to the power bus, the outputs of the first and second inverters are connected respectively to the inputs of the reading and writing of the first RAM, characterized in that the introduced second and third RAM device configuration and diagnostics (UND), with third, fourth and fifth inverters, the first and fifth elements And the first and second elements OR, and address inputs 1, ..., m of the second RAM connected to respective outputs, the address outputs 1, ..., n which is connected to the corresponding inputs of the third RAM inputs select the first, second and third RAM is connected to line the respective outputs UND, outputs 3.0, ..., ZM, PO, ..., PN which are connected to the corresponding inputs of the decoder, the input read second and third RAM connected with each other and with the output of the fourth inverter, recording inputs of the second and third RAM connected with each other and with the output of the fifth inverter, the input/output position of the end of the cycle and the position of synchronously in the cycle of the second RAM connected to respective inputs/outputs of the UND, the input/output end positions of the super-frame, which is connected with the corresponding input/output of the third RAM, input/output position of the end of the cycle of the second RAM is connected with the corresponding input TH and output devices for CA entrance/exit position synchronously in the cycle of the second RAM is connected also to the first input of the fifth element And the input/output end positions of the super-frame, the third RAM is connected with the respective output device for the CA, the input and the second input of the fifth element, And a third input connected to the third output of the distributor, the fourth output of which is connected to a second input of the fourth element And the input of the mode selection device for the CA is connected to the corresponding inputs UND and the CS input of the third inverter and the first input of the second and fourth elements And the output of the read-UND connected with the input of the fourth inverter and the second input of the first element And the first input and the first input of the third is lament And is connected to the output of the third inverter, record outputs AND is connected to the input of the fifth inverter and a second input of the third element And whose output is connected to the first input of the second element OR its second input connected to the output of the fourth element, And the output to the input of the second inverter, the output of the trigger is connected to a second input of the second element And whose output is connected to the second input of the first element OR the first its input connected to the output of the first element, And the output to the input of the first inverter, the outputs of clock cycles settings and options are in zero UND connected to respective inputs, the output of the fifth element And connected with the input end of synchronously FU, input the new address, set in the zero state, write, read, configuration, RAM or registers, select the custom of RAM, an information input/output device settings for the CA is connected to the corresponding inputs UND.



 

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The receiver clock // 2242093
The invention relates to radio engineering

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