# Code cyclic synchronization method

FIELD: technology for realization of cyclic synchronization of interference-resistant cyclic codes, in particular, cascade codes.

SUBSTANCE: in accordance to method, at transferring side one synchronization series is selected for N code words following one another, check section of code words is added with modulus two to appropriate section of aforementioned synchronization series. At receiving side received input series, consisting of several code words following each other, is divided onto original interference-resistant cyclic codes polynomial, producing a total of interference-resistant cyclic codes syndrome and synchronization series. By subtracting synchronization series from produced total, interference-resistant cyclic codes syndrome is selected. On basis of interference-resistant cyclic codes syndrome combination of errors in interference-resistant cyclic codes is computed and its weight is evaluated. On basis of error combination weight, trustworthiness degrees of code words following each other are computed. If total trustworthiness degree exceeds threshold value, decision about performing code cyclic synchronization of input series is taken.

EFFECT: increased interference resistance of cyclic synchronization.

2 cl

The invention relates to methods code frame synchronization during the transmission of discrete data and can be used for frame synchronization error-correcting cyclic codes, in particular concatenated codes.

The proposed method code frame synchronization is applicable for synchronization messages transmitted by the sequence of words in error-correcting cyclic code. When the coded frame synchronization clock characteristics are passed on words of error-correcting cyclic code. This does not require the transmission of additional special synchronizing symbols, and uses the redundancy of the error correcting code. Code cycle synchronization can be established in the presence of distortion in the received word error correcting code, not to exceed a certain threshold. After establishing a code frame synchronization, signs synchronization subtract from the words of the error correcting code, not reducing correcting ability of the code. The most effective use of the code frame synchronization in noise-tolerant cascade codes. In this case, synchronization is provided by repetition of signs synchronization in different words internal code cascade code.

There is a method of frame synchronization, etc is where the input sequence, represent the sum modulo two error-correcting code and a synchronization sequence, divided by the generating polynomial of the error correcting code, and as a result providing the synchronization sequence. Upon detection of a binary combination in the selected synchronization sequence, the decision about the presence of frame synchronization [Losev CENTURIES, Brody E.B., cookie monster VI Search and decoding of complex discrete signals, Ed. Vigorita. - M.: Radio and communication, 1988, str].

However, this method is insufficient immunity.

Closest to the proposed method is a method code frame synchronization (prototype), namely, that the accepted input sequence consisting of several consecutive words, each of which represents the sum modulo two error-correcting cyclic code and a synchronization sequence, divided by the generating polynomial of the error-correcting cyclic code. After the division receives the amount of the syndrome of error-correcting cyclic code and a synchronization sequence. Next, from the obtained amount is deducted from the synchronization sequence and produce the syndrome of error-correcting cyclic code. Then the syndrome robust cyclizes the th code calculates the combination of errors in the error-correcting cyclic code and assess its weight. Next, by weight of the combination of errors calculate the reliability of consecutive words of error-correcting cyclic code. Then the reliability of summed together and, in case of exceeding the total veracity of the words of error-correcting cyclic codes the threshold values of total authenticity, decide on a code frame synchronization input sequence [RF Patent №2210870, IPC 7 H 04 L 7/08. Semigin D.A., Kvashennikov Century, Century slepukhin F. W. Method of adaptive coded frame synchronization, prior. 09.08.2001, publ. 20.08.2003].

The disadvantage of this method is the low immunity due to the fact that cyclic code synchronization set is replicated as many times shortest synchronizing sequence, synchronization properties which are worse than the long sync sequence.

The purpose of the invention to increase the noise immunity of the code frame synchronization messages due to the fact that synchronization use the long sync sequence, synchronization properties which are better than the many times repeated shortest synchronizing sequence.

To achieve the goal proposed method code frame synchronization, namely, that the accepted input sequence consisting of not is how many consecutive words each of which represents the sum modulo two error-correcting cyclic code and a synchronization sequence, divided by the generating polynomial of the error-correcting cyclic code. After the division receives the amount of the syndrome of error-correcting cyclic code and a synchronization sequence. Next, from the obtained amount is deducted from the synchronization sequence and produce the syndrome of error-correcting cyclic code. Then the syndrome of error-correcting cyclic code calculates the combination of errors in the error-correcting cyclic code and assess its weight. Next, by weight of the combination of errors calculate the reliability of consecutive words of error-correcting cyclic code. Then the reliability of summed together and, in case of exceeding the total veracity of the words of error-correcting cyclic codes the threshold values of total authenticity, decide on a code frame synchronization input sequence. What is new is the fact that choosing one synchronizing sequence for N(N>1) consecutive error-correcting cyclic codes, each error correcting cyclic code is summed with the corresponding part of the synchronization sequence and the total reliability of error-correcting cyclic to the s is calculated only for those error-correcting cyclic codes, which were added to the different parts of the same synchronization sequence.

And with a synchronizing sequence summarize only the test part of the error-correcting cyclic codes, and successive N error-correcting cyclic codes that summarize with one synchronizing sequence, are internal codes of one cascade code.

The implementation of the method of adaptive coded frame synchronization consider the example of synchronization of the cascade code.

On the transmission side form input sequence, which is then transmitted to the receiving side. For this purpose, the transmitting side of the original message volume For m-ary (m>1) characters at the beginning encode m-ary error-correcting code, for example, m-ary error-correcting code is a reed-Solomon. A reed-Solomon code is the outer code or code first-stage robust cascade code.

In the encoding information is a code word reed-Solomon code (N, K), the information length is equal To, and block - N characters.

Further information code binary code, such as binary Bose-Roy-Chaudhury-Hocquenghem (BCH codes) with generating polynomial g(x). Code BCH is an internal code or code of the second stage robust cascade of the CSOs code. Code BCH has parameters: n - block code length, k is the information length of the code.

Source of information f(x) for each word of the BCH code are symbols of a reed-Solomon code, considered as a binary polynomial of degree k-1. Coding code BCH p_{1}(x) is executed by the formula

A coding BCH code all code symbols reed-Solomon receive N binary words BCH code(n, k) or a binary sequence, the length of which is nN bits.

Next put modulo two characters of the binary sequence BCH codes with symbols binary synchronizing sequence. As a synchronizing sequence select the sequence with good timing properties, for example a reed-Muller (RM) 1-th order (sequence maximum period). When this synchronization sequence is divided into parts p_{2}(x) of length n-k symbols each, and the characters of these parts of the synchronizing sequence summarize with the appropriate n-k check symbols of the corresponding BCH code: R_{3}(x)=p_{1}(x)+R_{2}(x). For this operation, the length of the synchronization sequence shall not be less than V=(n-k)n Between words in concatenated BCH code and cuts synchronizing sequence (code RM) from the established one-to-one correspondence.
The validation part of the first word BCH formed with the first segment synchronizing sequence, the test of the second - second segment synchronizing sequence and so on. This addition is performed with all the words BCH code cascade code.

At the receiving side input sequence, formed as the sum of two sequences, use code for frame synchronization. In the communication channel due to distortion of the signal errors and code words BCH code R_{3}(x) is superimposed combination of errors e(x). Therefore, the input sequence at the receiving side can be represented in the form:

At the receiving side input sequence R_{4}(x) is first divided by the generating polynomial error-correcting code g(x):

Division code BCH p_{1}(x) by the generating polynomial g(x), by definition of the code gives a zero balance. Dividing the segment synchronizing sequence R_{2}(x) by the generating polynomial g(x), the synchronization sequence is not changed, because it is imposed on the checking part of the code and, hence, its degree is less than the degree of the generating polynomial. Divide combination of errors e(x) by the generating polynomial of the code, by definition, gives a remainder of sin is rum code s(x).
Thus, when dividing the input sequence by the generating polynomial residue receive the amount of the syndrome BCH code and the segment synchronizing sequence:

Next, subtracting the synchronization sequence R_{2}(x) from a combination of r(x), receive error-correcting syndrome code s(x). The syndrome code s(x) determines a combination of the error e(x) in the error-correcting cyclic code, BCH. This is possible if the frequency error is within the correcting ability of the code. Combination of errors e(x) for the syndrome s(x) can be calculated in advance and place, for example, in the table. Determination of the errors in the code can be executed using the error table, the entrance of which are combinations of the syndrome s(x), and the output is a combination of the error e(x) in the error-correcting code. To obtain the error table first for all possible combinations of errors e(x) compute the corresponding syndromes s(x) of the code, and then put the combination of the error e(x) in the error table at the address s(x).

After determining the combination of errors calculate its weight, i.e. the number of units in combination errors. Then, by weight errors assess the reliability of the adopted code.

Assessment of the reliability of the adopted code is based on the following considerations. Authenticity code word is determined by the probability of neon the armed errors when correcting errors. Increasing the number of bugs that are fixed in the code word, the probability of undetected errors (the probability of a false decode) and decreases the reliability of the received code word. The ratio of undetected errors [elements of theory of discrete information transmission Ed. Lppath, M., Link, 1972, str], which determines the share of transformations depending on the number correct in the code word error β, is estimated by the formula

where k, n and information, and block length of the code, respectively,

t - the number of errors corrected in the code word.

Estimated number of binary digits f, used for error detection is equal to

Authenticity code word γ(t) when correcting t errors will be evaluated relative to the number of bits of the code word used to detect errors and will be written in the form

Thus the reliability of the code word, in which no error is equal to 1. When the number of errors in the code word its reliability decreases.

Link quality is determined by the total reliability of the received code words. Next, calculate the total reliability of consecutive pomekhoustoichivosti BCH codes. In this case, to calculate the total reliability of the use of reliability only those error-correcting cyclic codes, which are summed with different parts of the same synchronization sequence.

If the total reliability of the code words exceeds a pre-selected threshold value of reliability γ_{max}:

it is driven synchronization. This means that the input information is supplied for further processing. The location of the synchronizing sequence uniquely identifies the beginning of the first error correcting cyclic code, BCH code in cascade or the beginning of the message.

In the proposed method, the decision to frame synchronization is taken depending on the total reliability of the received error-correcting cyclic codes BCH. With the high quality of the communication channel, the number of received error-correcting codes, in which the decision about the frame synchronization decreases. This is because the communication channel is a high-quality number of received undistorted code words increases. Reliability undistorted code words above, and for reliable synchronization requires the acceptance of a smaller number of code words. With the deterioration of the quality of the communication channel total dostovernost the received code words is reduced and reliable synchronization requires a greater number of error-correcting codes, as part of the code words received with errors.

The threshold value of the total reliability of the received code words γ_{max}choose thus to ensure a high probability of frame synchronization, not inferior, at least, the probability of correct decoding of error-correcting cascade code. When the value of this threshold, the total reliability of the received code words may not be enough to establish frame synchronization, and at a low magnitude threshold increases the probability of false synchronization. The optimal choice of the specified parameter provides a high probability of frame synchronization and low probability of false synchronization.

The choice of the threshold values of total reliability of the received code words will show on the example of the cascade code, the inner code is a binary code BCH (31,16)and the outer code is a reed-Solomon code (24,16) over Galois field GF(2^{8}). The length of the synchronizing sequence for this cascade code is equal to 24·(31-16)=360 bits. As a synchronizing sequence can be taken first 360 bits recurrent M-sequence. Its total length is 511 bits. The first 360 bits of this sequence is divided into parts, each of which has a length of 15 bits, the Estimated probability of correct reception of the cascade code in the channel with independent errors when the error rate 0.07 equal to 0.931.
Synchronization is performed on BCH codes, accepted without error or with a single error. The estimated probability of receiving BCH code without errors on a given channel is equal to 0.105, with correction of single errors - 0.246. The average number unmistakably adopted codes in concatenated BCH code of length 24 is 2.520, the average number of BCH codes adopted with one error - 5.904. The reliability of error-free code BCH according to the formula (6) is equal to 1, BCH code with the same error equal to 0.667. The average total reliability of the received BCH codes cascade code on the specified channel is set to 1·2.520+0.667·5.904=6.458. On the other hand, for reliable protection against false synchronization, as shown by the results of the calculations, sufficient to receive undistorted three code words. Therefore, the total reliability can be in the range of values 3<∑γ_{i}<6.458. As the threshold values of total reliability, providing the probability of frame synchronization is not less than the probability of correct reception of the cascade code and reliable protection against false synchronization can be chosen value γ_{max}=(3+6.458)/2=4.729.

In this way the code cycle synchronization is not only error-free code words and the code words with errors. This increases the robustness of the code frame synchronization and allows jet to perform synchronization at a high level of interference in the communication channel, where the number of undistorted code words is reduced.

In the proposed method involves the summation of the synchronizing sequence only test part of the BCH code. This allows you to select when receiving the synchronization sequence. In the prototype, the synchronization sequence summarize with all the BCH code, and therefore is allocated converted synchronization sequence, which may not provide a high synchronization properties.

In the present invention, unlike the known method, is used in N (N>1) times longer sync sequence. The synchronizing sequence properties are determined by the minimum code distance of this sequence from it shifts to the right or to the left by a certain number of digits. With a large minimum code distance of the shift of the synchronizing sequence detect even in the presence of a large number of errors in the communication channel. As long synchronization sequence has a greater minimum code distance than short, the proposed method provides a higher probability of frame synchronization. For example, the minimum code length of M-sequence of length V bits, equal to about V/2 and increases proportionally to the length of the Shin is ioniziruushei sequence.

Achievable technical result of the proposed method code frame synchronization is increasing its noise immunity.

1. The way the code frame synchronization, namely, that the accepted input sequence consisting of several consecutive code words, is divided by the generating polynomial of the error-correcting cyclic code, the result of the division have the sum of the syndrome of error-correcting cyclic code and a synchronization sequence, then from the resulting amount is deducted from the synchronization sequence and produce the syndrome of error-correcting cyclic code, then the syndrome of error-correcting cyclic code calculates the combination of errors in the error-correcting cyclic code and assess its weight, then the weight of the combination of errors calculate the reliability of consecutive code words, then the reliability of summed together, and in the case exceeding the total reliability of the threshold values of total authenticity, decide on a code frame synchronization input sequence, characterized in that on the transmission side selects one of the synchronizing sequence for N (N>1) consecutive code words, sum modulo two test part of the code words with the appropriate is the art of this synchronizing sequence, and total reliability is calculated only for the test parts of the code words.

2. The method according to claim 1, characterized in that successive N error-correcting cyclic codes that summarize with one synchronizing sequence, are internal codes of one cascade code.

**Same patents:**

FIELD: digital communications, namely, engineering of devices for cyclic synchronization of digital information transfer systems with temporal compression.

SUBSTANCE: known device contains random-access memory device, adjustment and diagnostics device, phasing device and generator equipment. Cyclic evenness determining device is introduced to known device. Therefore, cyclic synchronization device provides cyclic synchronization of different digital transmissions, wherein synchronous combination is absent, while on positions at the end of cycle signals are transferred, filling sum of signals of appropriate digital transmission up to evenness.

EFFECT: expanded functional capabilities of device for cyclic synchronization.

2 cl, 3 dwg

FIELD: electric communications engineering, possible use in receiving cycle synchronization devices of systems for transmission of discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, adder, block of shift registers, solving block, generator of cyclic impulses, counter of cycles, comparison block, counter of distorted synchronization impulses, counter of total number of synchronization impulses, AND element, counter of clock impulses, trigger, block for selecting maximal weight of response, threshold selection block, second threshold selection block, block for selection of counting coefficient, signal input, clock input and output of device. Synchronization signal recognition device contains shift register, detector of errors in synchronization group, generator of weight of response to synchronization signal. Solving block contains comparison block, memory block, subtraction block, comparison block, comparison counter, second AND element, third AND element, OR element. By means of second element AND, third element AND, and also element OR in synchronous mode, and also in case of synchronism failure, generation of synchronization signal is performed at output of solving block. Restoration of synchronism after failure and phasing of device for new position of cyclic synchronism is performed in case of occurrence of two events simultaneously: determining of new position of cyclic synchronization signal by solving block and detection of failure of cyclic synchronism by means of cycles counter, comparison block, threshold selection block and count coefficient selection block, because during regular repeating at certain information position of cycle of false synchronization group and random distortion of true synchronization group phase of cyclic impulse generator does not alter, thus causing no false synchronism failure.

EFFECT: increased interference resistance of device for cyclic synchronization.

4 dwg

FIELD: electric communications, possible use in receiving devices for synchronization by cycles of system for transferring discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, forbidding element, first AND element, adder, shift registers block, generator of clock pulses, OR element, cycles counter, counter of distorted synchronization signals, block for selecting allowed number of distorted synchronization signals, block for selecting threshold, block for selecting counting coefficient, counter by exit from synchronization status, and also solving assembly, containing first comparison block, memory block, subtraction block, second comparison block, comparison counter, second AND element, third AND element, second OR element.

EFFECT: increased reliability of operation of device for synchronization by cycles due to excluded possibility of overflow of shift registers block in synchronous operation mode.

1 dwg

FIELD: digital data transfer systems for frame synchronization of correcting codes including noise-immune concatenated codes.

SUBSTANCE: proposed device for adaptive code frame synchronization has delay register 1, error detection assembly 2, decoder unit 10, counter 11, threshold unit 21, synchronizing-sequence generator 18, modulo two output adder 12, random-access memory 15, modulo two adder unit 16, number comparison unit 13, full adder 19, synchronization counter 17, error counter 14, and code converter 20. Error detection assembly is set up of two series-connected Huffman filters 3, 4 and syndrome register; each Huffman filter has register 6/7 and modulo two adder 8/9.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: digital communications;

SUBSTANCE: proposed device is used for frame synchronization of digital time-division multiplex data transmission systems and incorporates provision for synchronizing data transmission class at dispersed sync combination of group signal and for implementing parallel search for synchronism. Device has first, second, and third random-access memories, storage register, decoder, distributor, generator equipment, phasing unit, flip-flop, first and second inverters, adjusting unit, first, second, and third inverters, first, second, third, fourth, and fifth AND gates, first and second OR gates.

EFFECT: enlarged functional capabilities.

1 cl, 2 dwg

FIELD: communications.

SUBSTANCE: device has control circuit, first input of which is connected to output of phase sign decoder, second input is connected to first clock input of device, third input is connected to second clock input of device, circuit OR, connected by its inputs to outputs of controlled system, and output of OR circuit is connected to third block for forming cyclic phasing signal, while the latter is made on basis of same circuit of logic numbers processing and consists of two numbers signals switchboard, arithmetic adder of two numbers, memory device, meant for recording K numbers, on basis of K data words, required for forming of cycle synchronization signal, AND match circuit, decoder, pulse counter, performing function of threshold element.

EFFECT: higher trustworthiness.

1 dwg

FIELD: digital communications.

SUBSTANCE: device has random access memory, adjusting device, synchronous combination decoder, phasing device, generator equipment, three commutators, signals distributor, time analyzer and signals remover.

EFFECT: higher reliability, higher effectiveness, higher interference resistance.

1 cl, 3 dwg

FIELD: digital communications.

SUBSTANCE: device has random access memory, adjusting device, synchronous combination decoder, phasing device, generator equipment, three commutators, signals distributor, time analyzer and signals remover.

EFFECT: higher reliability, higher effectiveness, higher interference resistance.

1 cl, 3 dwg

FIELD: communications.

SUBSTANCE: device has control circuit, first input of which is connected to output of phase sign decoder, second input is connected to first clock input of device, third input is connected to second clock input of device, circuit OR, connected by its inputs to outputs of controlled system, and output of OR circuit is connected to third block for forming cyclic phasing signal, while the latter is made on basis of same circuit of logic numbers processing and consists of two numbers signals switchboard, arithmetic adder of two numbers, memory device, meant for recording K numbers, on basis of K data words, required for forming of cycle synchronization signal, AND match circuit, decoder, pulse counter, performing function of threshold element.

EFFECT: higher trustworthiness.

1 dwg

FIELD: digital communications;

SUBSTANCE: proposed device is used for frame synchronization of digital time-division multiplex data transmission systems and incorporates provision for synchronizing data transmission class at dispersed sync combination of group signal and for implementing parallel search for synchronism. Device has first, second, and third random-access memories, storage register, decoder, distributor, generator equipment, phasing unit, flip-flop, first and second inverters, adjusting unit, first, second, and third inverters, first, second, third, fourth, and fifth AND gates, first and second OR gates.

EFFECT: enlarged functional capabilities.

1 cl, 2 dwg

FIELD: digital data transfer systems for frame synchronization of correcting codes including noise-immune concatenated codes.

SUBSTANCE: proposed device for adaptive code frame synchronization has delay register 1, error detection assembly 2, decoder unit 10, counter 11, threshold unit 21, synchronizing-sequence generator 18, modulo two output adder 12, random-access memory 15, modulo two adder unit 16, number comparison unit 13, full adder 19, synchronization counter 17, error counter 14, and code converter 20. Error detection assembly is set up of two series-connected Huffman filters 3, 4 and syndrome register; each Huffman filter has register 6/7 and modulo two adder 8/9.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: electric communications, possible use in receiving devices for synchronization by cycles of system for transferring discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, forbidding element, first AND element, adder, shift registers block, generator of clock pulses, OR element, cycles counter, counter of distorted synchronization signals, block for selecting allowed number of distorted synchronization signals, block for selecting threshold, block for selecting counting coefficient, counter by exit from synchronization status, and also solving assembly, containing first comparison block, memory block, subtraction block, second comparison block, comparison counter, second AND element, third AND element, second OR element.

EFFECT: increased reliability of operation of device for synchronization by cycles due to excluded possibility of overflow of shift registers block in synchronous operation mode.

1 dwg

FIELD: electric communications engineering, possible use in receiving cycle synchronization devices of systems for transmission of discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, adder, block of shift registers, solving block, generator of cyclic impulses, counter of cycles, comparison block, counter of distorted synchronization impulses, counter of total number of synchronization impulses, AND element, counter of clock impulses, trigger, block for selecting maximal weight of response, threshold selection block, second threshold selection block, block for selection of counting coefficient, signal input, clock input and output of device. Synchronization signal recognition device contains shift register, detector of errors in synchronization group, generator of weight of response to synchronization signal. Solving block contains comparison block, memory block, subtraction block, comparison block, comparison counter, second AND element, third AND element, OR element. By means of second element AND, third element AND, and also element OR in synchronous mode, and also in case of synchronism failure, generation of synchronization signal is performed at output of solving block. Restoration of synchronism after failure and phasing of device for new position of cyclic synchronism is performed in case of occurrence of two events simultaneously: determining of new position of cyclic synchronization signal by solving block and detection of failure of cyclic synchronism by means of cycles counter, comparison block, threshold selection block and count coefficient selection block, because during regular repeating at certain information position of cycle of false synchronization group and random distortion of true synchronization group phase of cyclic impulse generator does not alter, thus causing no false synchronism failure.

EFFECT: increased interference resistance of device for cyclic synchronization.

4 dwg

FIELD: digital communications, namely, engineering of devices for cyclic synchronization of digital information transfer systems with temporal compression.

SUBSTANCE: known device contains random-access memory device, adjustment and diagnostics device, phasing device and generator equipment. Cyclic evenness determining device is introduced to known device. Therefore, cyclic synchronization device provides cyclic synchronization of different digital transmissions, wherein synchronous combination is absent, while on positions at the end of cycle signals are transferred, filling sum of signals of appropriate digital transmission up to evenness.

EFFECT: expanded functional capabilities of device for cyclic synchronization.

2 cl, 3 dwg

FIELD: technology for realization of cyclic synchronization of interference-resistant cyclic codes, in particular, cascade codes.

SUBSTANCE: in accordance to method, at transferring side one synchronization series is selected for N code words following one another, check section of code words is added with modulus two to appropriate section of aforementioned synchronization series. At receiving side received input series, consisting of several code words following each other, is divided onto original interference-resistant cyclic codes polynomial, producing a total of interference-resistant cyclic codes syndrome and synchronization series. By subtracting synchronization series from produced total, interference-resistant cyclic codes syndrome is selected. On basis of interference-resistant cyclic codes syndrome combination of errors in interference-resistant cyclic codes is computed and its weight is evaluated. On basis of error combination weight, trustworthiness degrees of code words following each other are computed. If total trustworthiness degree exceeds threshold value, decision about performing code cyclic synchronization of input series is taken.

EFFECT: increased interference resistance of cyclic synchronization.

2 cl

FIELD: data processing in broadband radio communications and radio navigation.

SUBSTANCE: proposed method intended for use where reception of extended-spectrum data signals keyed by simulation-resistant pseudorandom nonlinear derivative sequences is always preceded by synchronization includes concurrent accumulation of periodic mutually correlated function values of signal segments arriving from output of dynamically matched adjustable filters with two standard sampling lines affording generation of random derivative, as well as determination of time step numbers of their mutual shift corresponding to delay synchronism. Then current delay of entire signal being received is found from combination of these time step numbers. Used as dynamically matched adjustable filters in search channels are acousto-electronic convolvers.

EFFECT: reduced time and hardware requirement for searching broadband delay signals characterized in high simulation resistance.

2 cl, 9 dwg

FIELD: electric and radio communications; frame synchronization receiving devices of digital message transmitting and intercepting systems.

SUBSTANCE: proposed method includes sequential search at single-bit shift, identification of concentrated sync groups in group digital stream, and formation of responses when identifying concentration sync groups on tested clock intervals, and measurement of time intervals between sequential moments of responses across concentrated sync group identifier in terms of clock intervals. Primary sample of N ≥ 3 time intervals is accumulated. Secondary samples of time intervals between moments of first, second, through (N + 1)^{th} reference responses, respectively, and arrival moments of all other primary-sample responses are calculated. Maximal common dividers of probable combinations of two or more time intervals are calculated and particular lines (spectrums) of distribution of maximal common dividers whose values exceed lower boundary of region of probable group signal cycle lengths are formed in the framework of secondary time interval samples. Integrated spectrum of maximal common divider values is formed by summing up all particular maximal common divider spectrums. Regular sequence of true integrated sync group responses is detected by fact of coincidence of maximal common dividers in integrated spectrum whose quantity exceeds desired threshold, and coincidence point abscissa of maximal common dividers is assumed as cycle length. True concentrated sync group responses are identified in primary implementation of stream by serial numbers of particular maximal common divider spectrums wherein we see multiple coincidences of maximal common dividers with found cycle length. Clock interval of group-signal next cycles commencement is predicted. Concentrated sync group responses appearing at predicted clock intervals are assumed as frame synchronization pulses. Decision on input in and output from frame synchronization mode is taken by composite "k/m-r" criterion.

EFFECT: enlarged functional capabilities due to affording frame synchronization in absence of a priori data on group-signal cycle length without impairing noise immunity.

1 cl, 9 dwg