Device for cyclic synchronization

FIELD: electric communications engineering, possible use in receiving cycle synchronization devices of systems for transmission of discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, adder, block of shift registers, solving block, generator of cyclic impulses, counter of cycles, comparison block, counter of distorted synchronization impulses, counter of total number of synchronization impulses, AND element, counter of clock impulses, trigger, block for selecting maximal weight of response, threshold selection block, second threshold selection block, block for selection of counting coefficient, signal input, clock input and output of device. Synchronization signal recognition device contains shift register, detector of errors in synchronization group, generator of weight of response to synchronization signal. Solving block contains comparison block, memory block, subtraction block, comparison block, comparison counter, second AND element, third AND element, OR element. By means of second element AND, third element AND, and also element OR in synchronous mode, and also in case of synchronism failure, generation of synchronization signal is performed at output of solving block. Restoration of synchronism after failure and phasing of device for new position of cyclic synchronism is performed in case of occurrence of two events simultaneously: determining of new position of cyclic synchronization signal by solving block and detection of failure of cyclic synchronism by means of cycles counter, comparison block, threshold selection block and count coefficient selection block, because during regular repeating at certain information position of cycle of false synchronization group and random distortion of true synchronization group phase of cyclic impulse generator does not alter, thus causing no false synchronism failure.

EFFECT: increased interference resistance of device for cyclic synchronization.

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The invention relates to telecommunication and can be used in the receiving device sync cycles of transmission of discrete messages.

A device for frame synchronization on and. C. the USSR 436393 class G 11 19/00, publ. 15.07.74, bull. No. 46, containing, as the proposed device, the detector of the clock, the unit shift registers, an adder, a crucial node, and the main output of the detector clock connected to the first input of the adder, the output of which is connected to the signal input of the shift registers, the main output of which is connected to the second input of the adder. In addition, in the known device, the main output of the unit shift registers is connected with the signal input of the decision making node. This adder is made in the form of n-bit reversible counter which performs a counting function response of the detector clock on each of the pulse positions of cycles of the observation interval, and n shift registers of unit shift registers perform the saving of the results account for the duration of the cycle. In clock intervals defined by clock pulses from a clock pulse is cheating values of bits of the n-bit counter in the first cell of the corresponding shift registers and write to the same counter value of the last cell registration of the AE shift. If the heartbeat interval is the response of the detector clock, the n-bit counter is added to the unit and, thus, the value of the binary number corresponding to the number of responses accumulated previously in this position the loop is incremented. If the position loop is no response of the detector, the number recorded in parallel binary code into an n-bit counter with the last cell of register is decreased by one. After a cycle in cells of registers in a parallel binary code are recorded the results of the response of the detector for all N pulse positions. Based on the analysis of these results, a crucial node determines the position number, which corresponds to the largest binary number of responses of the detector clock, and thus decides the position of synchronism. The output of the decision making node is an output device. A disadvantage of the known device is the low immunity, defined high probability of false positives (false detection of synchronism). Mode matching with regular repetition on some information of the position loop false singlegroup and random distortion of the true singlegroup may cause false detection of synchronism, i.e. fails to sequential matching, although true, is grography will be sent to the specified position of the loop.

A device for frame synchronization on and. C. the USSR 1172052 class H 04 L 7/08, publ. 07.08.85, bull. No. 29, containing, as the proposed device, the detector of the synchronization signal, the adder, the unit shift registers, a crucial node, the driver of such pulses, the block selection threshold and the cycle counter. Moreover, the main output of the detector clock connected to the first input of the adder, the output of which is connected to the signal input of the shift registers. The main output of the unit shift registers connected to the second input of the adder, and an additional output unit shift registers to the signal input of the decision making unit, which consists of the first block compare block of memory, the subtraction unit, the second unit of comparison and counter comparison. Thus the output of the first unit of comparison is connected to the control input of the memory block, the output of which is jointly connected to the second input of the first unit of comparison and the first input of the subtraction unit. The second input of the subtraction unit is combined with data input of the memory block, the first input of the first unit of comparison is the signal input of the decision making node. The output of the subtraction unit is connected to the second input of the second unit of comparison. The output of the second unit of comparison is connected to the reset input of the counter comparison. When this control inputs and clock inputs of the decision making node are sootvetstvenno the first input of the second block comparison and the clock input of the counter comparison. The output of the decision making node is connected to the reset inputs of the former (cyclic pulses and block shift registers. The output of shaper cyclic pulses connected to the counting input of counter cycles. The clock input of the unit shift registers combined with a clock input of the Recognizer clock, a casting site and shaper of such pulses, and the control input of the decision making node coupled to the output of the block selection threshold. When this signal input, a clock input of the detector clock and the output of the shaper cyclic pulses are respectively the signal input, a clock input and output devices. In addition, the known device also contains an element of interdiction and counter the distorted signals. The second input element of the ban is connected to the output of the detector clock. The output of shaper cyclic pulses connected to the first input element of the ban. The output of the loop counter is connected to the control input of the block selection threshold and the control input of the counter distorted signals. The output element of the ban is connected to the counting input of the counter distorted signals, the output of which is connected to the address input of the block selection threshold. The output of the counter comparison is connected to the reset input of the memory block and an output of the decision making node. A disadvantage of the known device is low homepostalcode, defined high probability of false detection of synchronism. Mode matching with regular repetition on some information of the position loop false singlegroup and random distortion of the true singlegroup may occur shaper installation cycle pulses in the wrong phase, i.e. fails to sequential matching, although the true singlegroup will be sent to the specified position of the loop.

Closest to the present invention is a device for frame synchronization according to the patent of Russian Federation №2239953 class H 04 L 7/08, publ. 26.11.2004, bull. No. 31, prototype, containing, as the proposed device, the detector of the synchronization signal, the adder, the unit shift registers, a crucial node, the driver of such pulses, the counter distorted clock, a count of the total number of clock pulses, the first element And the counter clock pulses, a trigger block selection maximum weight response, the block selection threshold. This Recognizer clock contains a shift register, the detector errors singlegroup and shaper weight response to the synchronization signal. A crucial node contains the first block of comparison, a memory unit, a subtraction unit, a second unit of comparison, the counter comparison. Moreover, the signal input device is connected to the signal input of the detector clock. The signal input of the Recognizer synchroni the Nala is an information input of the shift register, the output of which is connected to the input of the error detector in singlegroup. The clock input of the detector clock connected to clock inputs of the shift register and driver weight response to the synchronization signal. The first output of the error detector in singlegroup connected to the first input of the shaper weight response to the synchronization signal. The second output of detector errors singlegroup jointly connected to the input of counter data distorted clock pulses and to the third input of the shaper weight response to the synchronization signal, to the second input of which is connected to the output unit selecting the maximum weight of response. The output of shaper weight response to the synchronization signal connected to the first input of the adder, the output of which is connected to the signal input of the shift registers. The main output of the unit shift registers connected to the second input of the adder, and an additional output to the signal input of the decision making node. Thus the output of the first unit of comparison is connected to the control input of the memory block, the output of which is jointly connected to the second input of the first unit of comparison and the first input of the subtraction unit. The second input of the subtraction unit is combined with data input of the memory block, the first input of the first unit of comparison is the signal input of the decision making node. The output of the subtraction unit is connected to the second input of the second Comparer, you are the od which is connected to the reset input of the counter comparison. When this control input and a clock input of the decision making node are, respectively, the first input of the first unit of comparison and the clock input of the counter comparison. The output of the decision making node is connected to the reset inputs of the former (cyclic pulses and block shift registers. The clock input of the shaper cyclic pulses combined with the first input element And a clock input Recognizer clock, a crucial node of the unit shift registers, counter distorted clock and counter clock pulses. The control input of the decision making node coupled to the output of the block selection threshold. The output of the counter distorted clock is connected to the address inputs of the block selection maximum weight response and the block selection threshold. The output of shaper cyclic pulses connected to the control input of the counter distorted clock pulses and the input set trigger and the reset input of the trigger is connected to the output of the counter clock pulses. The trigger output is connected to the reset input of counter clock pulses and a second input of the first element And whose output is connected to a clock input of a counter of the total number of clock pulses. The output count of the total number of clock pulses is connected to the reset input of the counter distorted clock and control inputs of the block selection maximum weight response and the block selection threshold. If this is m signal input of the detector clock the clock input of the shaper cyclic pulses and the output of the shaper cyclic pulses are respectively the signal input, a clock input and output devices. In addition, in the known device the output of the counter comparison is connected to the reset input of the memory block and an output of the decision making node. A disadvantage of the known device is the low immunity, defined high probability of false detection of synchronism. Mode matching with regular repetition on some information of the position loop false singlegroup and random distortion of the true singlegroup may occur shaper installation cycle pulses in the wrong phase, i.e. fails to sequential matching, although the true singlegroup will be sent to the specified position of the loop.

Transmission feature of deterministic sequential clock is the frequency of its repetition on the same positions of the transmission cycle of the group signal. This Recognizer clock can recognize in the received multicast signal is not only true singlegroup, but false, randomly generated information on the positions of the cycle. At the output of the detector clock generated responses in the form of weights (the permissible number of distorted singlesymbol) and zeros (PR is exceeded distorted singlesymbol). The required accuracy of decision-making decisive node is achieved through the accumulation response of the detector clock in the unit shift registers. Mode of synchronism when determining critical node positions of a cyclical clock is reset by a unit shift registers and phasing shaper cycle pulses. Upon detection of the true clock phase initial installation of the driver of such pulses will not change and apparatus for frame synchronization will remain in a state of synchronism. When taking singlegroup with the number of distorted singlesymbol more valid number at the output of the detector clock is generated zero response and the accumulation of synchroinformation in cells of the unit shift registers corresponding to the true synchrogram, is not carried out. Recognition by the Recognizer clock code group information on the positions of the cycle leads to the accumulation of responses in cells of the unit shift registers corresponding to a false synchrogram. When the regular repetition on some information of the position loop false singlegroup and random distortion of the true singlegroup may occur shaper installation cycle pulses in the wrong phase, i.e. fails to sequential matching, although the true singlegroup will be coming and the specified position in the cycle. These factors make high demands on the noise immunity of the device for frame synchronization.

Device for frame synchronization contains Recognizer clock, the adder, the unit shift registers, a crucial node, the driver of such pulses, the counter distorted clock, a count of the total number of clock pulses, the first element And the counter clock pulses, a trigger block selection maximum weight response, the block selection threshold. This Recognizer clock contains a shift register, the detector errors singlegroup and shaper weight response to the synchronization signal. A crucial node contains the first block of comparison, a memory unit, a subtraction unit, a second unit of comparison, the counter comparison. Moreover, the signal input device is connected to the signal input of the detector clock. The signal input of the detector clock information is the input of the shift register, the output of which is connected to the input of the error detector in singlegroup. The clock input of the detector clock connected to clock inputs of the shift register and driver weight response to the synchronization signal. The first output of the error detector in singlegroup connected to the first input of the shaper weight response to the synchronization signal. The second output of detector errors singlegroup joint is connected to the data input of the counter distorted clock pulses and to the third input of the shaper weight response to the synchronization signal, to the second input of which is connected to the output unit selecting the maximum weight of response. The output of shaper weight response to the synchronization signal connected to the first input of the adder, the output of which is connected to the signal input of the shift registers. The main output of the unit shift registers connected to the second input of the adder, and an additional output to the signal input of the decision making node. Thus the output of the first unit of comparison is connected to the control input of the memory block, the output of which is jointly connected to the second input of the first unit of comparison and the first input of the subtraction unit. The second input of the subtraction unit is combined with data input of the memory block, the first input of the first unit of comparison is the signal input of the decision making node. The output of the subtraction unit is connected to the second input of the second block of comparison, the output of which is connected to the reset input of the counter comparison. When this control input and a clock input of the decision making node are, respectively, the first input of the first unit of comparison and the clock input of the counter comparison. The output of the decision making node is connected to the reset inputs of the former (cyclic pulses and block shift registers. The clock input of the shaper cyclic pulses combined with the first input element And a clock input Recognizer clock, a crucial node of the unit shift registers, counter claim is by a clock and counter clock pulses. The control input of the decision making node coupled to the output of the block selection threshold. The output of the counter distorted clock is connected to the address inputs of the block selection maximum weight response and the block selection threshold. The output of shaper cyclic pulses connected to the control input of the counter distorted clock pulses and the input set trigger and the reset input of the trigger is connected to the output of the counter clock pulses. The trigger output is connected to the reset input of counter clock pulses and a second input of the first element And whose output is connected to a clock input of a counter of the total number of clock pulses. The output count of the total number of clock pulses is connected to the reset input of the counter distorted clock and control inputs of the block selection maximum weight response and the block selection threshold. When this signal input to the detector of the clock, the clock input of the shaper cyclic pulses and the output of the shaper cyclic pulses are respectively the signal input, a clock input and output devices.

The technical result in the implementation of the invention is to improve the noise immunity of the device for frame synchronization is achieved by the introduction of the second block selection threshold, the third block compare block selection coefficient accounts and the loop counter. In addition, a crucial node in titsa the second element, And the third element, And, and OR. Thus the output of the counter distorted sync together also connected to the address inputs of the second block selection threshold and the block selection coefficient accounts. In addition, the output counter of the total number of clock pulses together also connected to the control input of the second block selection threshold and the block selection coefficient accounts. The output of the second block selection threshold is connected to the second data input of the third block comparison to the first data input which is connected to the output of the adder. The output of the third unit of comparison is connected to the first auxiliary input control of the decision making node. The output of the decision making node together also connected to the reset inputs of the third block comparison and the loop counter, to the data input of which is connected to the output of the block selection coefficient accounts. Thus the output of the shaper cycle of the pulses together are also connected to the counting input of the cycle counter and the second additional control input of the decision making node. The output of cycle counter connected to the control input of the third block comparison. In addition, the output of the counter comparison jointly connected to the second input of the second element And to the first input of the third element And. the Output of the second element And the third element And connected respectively to first and second inputs of the element And The And the output of which is connected to the reset input of the memory block and an output of the decision making node. While the first and second additional control inputs of the decision making node are, respectively, the first input of the second element And the second input of the third element I.

With the introduction of the second block selection threshold, the third block compare block selection coefficient accounts, cycle counter, and in addition, the introduction to a crucial node of the second item And the third item, and the item OR increases the noise immunity of the device for frame synchronization mode of synchronism, as with regular repetition on some information of the position loop false singlegroup and random distortion of the true singlegroup phase shaper cycle of the pulses does not change, i.e. it is not a false failure of synchronism. The phase change of the driver of such pulses is possible only in case of lost of synchronism with the second block selection threshold, the third block compare block selection coefficient accounts and the loop counter. The failure of synchronism is detected if the amount of accumulation of the responses of the detector clock on the position of the true clock for k cycles, where k is the number of cycles of testing on the output from the synchronism) is lower than the threshold value accumulation response q. The AOC is e, the number of cycles test k at the output of the synchronism and the threshold value of accumulation q adaptive change depending on the probability of erroneous reception of singlesymbol that provides in each specific case (at a certain value of the probability of erroneous reception of singlesymbol) the minimum time of determination of the output from the synchronism (failure of synchronism), which will ensure the required immunity. When this blocks determine the values of k and q (depending on the probability of erroneous reception of singlesymbol) are respectively the second block selection threshold and the block selection coefficient accounts. The number of cycles k (for which the test output from the synchronism) is carried out using the loop counter. The decision on the output of the matching is performed using the third unit of comparison. With the second item And the third item, and the item OR by the formation of the synchronization signal at the output of the decision making node when the loss of synchronism (with simultaneous receipt of a signal failure detection of synchronism with the output of the third unit of comparison and signal detection of the synchronization signal from the output of the counter compare respectively to the first and second inputs of the second element). Using the third e is ment And and also element OR by the formation of the synchronization signal at the output of the decision making node in the mode of synchronism (with simultaneous signal detection clock output counter comparison and the frame synchronization signal output device respectively on the first and second inputs of the second element).

Conducted by the applicant's analysis of the prior art, including searching by the patent and scientific and technical information sources, and identify sources that contain information about the equivalents of the claimed invention, has allowed to establish that the applicant had not discovered similar, characterized by signs, identical with all the essential features of the claimed invention. Select from a list of identified unique prototype, as the most similar in essential features analogue, has identified a set of essential towards perceived by the applicant to the technical result of the distinctive features in the claimed device, set forth in the claims. Therefore, the claimed invention meets the criterion of "novelty".

To check compliance with the claimed invention, the criterion of "inventive step", the applicant conducted an additional search of the known solutions to identify signs that match the distinctive features of the prototype at what nakami claimed device. The search results showed that the claimed invention not apparent to the expert in the obvious way from the prior art, as defined by the applicant. Not identified the impact of changes under the essential features of the claimed invention, to achieve a technical result. In particular, the claimed invention does not provide the following transformations: addition of known means of any known part attached to it according to certain rules, to achieve a technical result, in respect of which it is the effect of such additions; the replacement of any part of the other known means known part to achieve a technical result, in respect of which it is the effect of such a change; the exclusion of any part of the funds while the exclusion of its functions and the achievement of a result of such exclusion; an increase of similar elements to enhance the technical result due to the presence in the vehicle is such elements; the execution of a known drug or part of a known material to achieve a technical result due to the known properties of the material; the creation of tools, consisting of well-known parts, the choice of which and tie who between them carried out based on known rules, recommendations and achievable technical result is due only to the known properties of the parts of this object and the relationships between them; change quantitative attributes or relations of signs, if known fact of the influence of each on the technical result, and the new characteristic values or their relationship could be obtained from the known dependencies. Therefore, the claimed invention meets the criterion of "inventive step".

The invention is illustrated graphics, which depict: figure 1 - structural diagram of an apparatus for frame synchronization, figure 2 - block diagram of the error detector in singlegroup in figure 3 - functional diagram of the counter 6 cycles figure 4 - functional block circuit 7 comparison.

Information confirming the ability of the invention to provide the above technical result are as follows.

Device for frame synchronization contains Recognizer 1 clock, the adder 2, block 3 shift registers, the deciding unit 4, a driver 5 cyclic pulses, the counter 6 cycles, block 7 comparison, the counter 8 distorted pulses, the counter 9 total number of pulses element 10 And the counter 11 clock pulses, a trigger 12, block 13 selecting the maximum weight of the response unit 14 choosing the horns, unit 15 the choice of the threshold, the block 16 ratio selection account, the input signal 17, entry 18 clock and the output device 19. The detector 1 clock register contains 20 of the shift, the detector 21 errors in singlegroup, shaper 22 weight response to the synchronization signal. A crucial node 4 contains the comparison block 23, block 24 of the memory unit 25 of the subtraction unit 26 comparison, the counter 27 comparison element 28 And the element 29 And the element 30 OR. When this input signal 17 is connected to the signal input of the detector 1 clock. The signal input of the detector 1 clock information is the input of the register 20 of the shift, the output of which is connected to the input of the detector 21 errors in singlegroup. The clock input of the detector 1 clock connected to clock inputs of the register 20 of the shift and shaper 22 weight response to the synchronization signal. The first output of the detector 21 errors in synchrogram connected to the first input of the shaper 22 weight response to the synchronization signal. The second output of detector 21 errors in singlegroup jointly connected to the data input of the counter 8 distorted clock pulses and to the third input of the shaper 22 weight response to the synchronization signal, to the second input of which is connected the output of block 13 of selecting the maximum weight of response. The output of driver 22 weight response to the synchronization signal connected to the first input of the adder 2, the output of which is connected to the n conjunction to the signal input unit 3 shift registers and the first input data block 7 comparison. The main output unit 3 shift registers connected to the second input of the adder 2, and the additional output to the signal input of the decision making unit 4. Thus the output of the comparison block 23 is connected to the input of the control unit 24 to the memory, the output of which is connected to the second input of the comparison block 23 and the first input unit 25 subtraction. The second input unit 25 subtraction combined with data input unit 24 to the memory, the first input unit 23 of the comparison signal is the input of the decision making unit 4. The output of the subtraction unit 25 is connected to the second input unit 26 of the comparison, the output of which is connected to the reset input of the counter 27 comparison. The output of the counter 27 comparison jointly connected to the second input of the element 28 And to the first input element 29 And. the Output element 28 And the element 29 And connected respectively to first and second inputs of the element 30 and whose output is connected to the reset input of the memory block and an output of the decision making node. When this control input, a clock input, and first and second additional control inputs of the decision making node 4 are, respectively, the first input unit 26 of the comparison, the clock input of the counter 27 comparison of the first input element 28 And the second input element 29 I. the Output of the decision making node is connected to the reset inputs of unit 3 of the shift register, shaper 5 cyclic pulses, the counter 6 cycles and block 7 against the deposits. The clock input of the shaper 5 cyclic pulses combined with the first input element 10 And a clock input of the detector 1 clock, the decision making unit 4, unit 3 shift registers, the counter 8 distorted clock pulses and the counter 11 clock pulses. Control input, first and second complementary control inputs of the decision making unit 4 are connected respectively with the output of block 14 of the choice of the threshold, the output unit 7 comparison and output devices. The output of the counter 8 distorted sync jointly connected to the address inputs of the block 13 selecting the maximum weight of the response unit 14 of the choice of the threshold, block 15 of the choice of the threshold and the block 16 ratio selection account. The output of the counter 9 total number of clock jointly connected to the reset input of the counter 8 distorted clock pulses and the input control unit 13 selecting the maximum weight of the response unit 14 of the choice of the threshold, block 15 of the choice of the threshold and the block 16 ratio selection account. The output of shaper 5 cyclic pulses jointly connected to the control input of the counter 8 distorted pulses to the control input of the trigger 12 and to the counting input of the counter 6 cycles. The reset input of trigger 12 is connected with the output of the counter 11 clock pulses. The trigger output is 12 jointly connected to the reset input of the counter 11 clock pulses and a second input element 10, the output of which is connected to t tovim input of the counter 9 total number of clock pulses. The output unit 15 of the choice of the threshold is connected with the second input unit 7 comparison. The output of block 16 ratio selection account is connected to the data input counter 6 cycles, the output of which is connected to the control input of the block 7 to compare. When this signal input of the detector 1, the clock input of the shaper 5 cyclic pulses and the output of the shaper 5 cyclic pulse signal is input 17, a clock input 18 and the output 19 of the device.

Device for frame synchronization works as follows. At the signal input of the detector 1 clock group enters the digital signal containing the deterministic group of the synchronization signal that is repeated with a repetition rate of the cycles. Information items group code signal group information symbols, is identical to singlegroup, are formed randomly. During each clock interval in the register 20 offset is written to one symbol of the received signal, and with the arrival of the next character previous moves to the next cell in the shift register. Thus, for m clock intervals (where m is the number of characters in singlegroup) in the register is written m character code combination. During each clock interval compares patterns of each of the received sequence of m symbols with "mine is th" singlegroup, recorded in the detector 21 errors in singlegroup, and the result of the comparison is converted into an s - bit binary number mOsh(where mOsh- the number of errors in singlegroup, s=[log2m]+1, where [ ] is the integer part of the number)is input to the imaging unit 22 of the weight of the response to the synchronization signal.

Figure 2 for example shows a functional diagram of the error detector in singlegroup having the structure 1101. The detector errors singlegroup consists of a decoder singlegroup (element DD1.1), encoder (elements DD2-DD5) and subtractive devices (elements DD6 and DD1.3-DD1.5). To the input of the decoder from the output of the register 20 of the shift to parallel code group served the signal. With the arrival of each clock pulse at the clock input of the shift register group signal shifted by one step to the left. The decoder is configured to detect singlegroup ID 1101. The encoder is designed to generate binary numbers accurately detected singlesymbol in singlegroup. Subtractive device performs the operation of subtracting from the number of characters in singlegroup m (in our case m=4). the number accurately detected singlesymbol in singlegroup. At the output of subtractive device, which is the output of the detector 21 errors in synchrogram, is formed by a binary number of erroneously received singlesymbol in synchro is the RUPE. The detector 21 errors in synchrogram can be implemented, for example, on the chip: DD1 - CLN; DD2 - CIJ; DD3 - CLA; DD4 - CLA; DD5 - CLL; DD6 - KIM.

In the imaging unit 22 of the weight of the response to the synchronization signal depending on the magnitude accurately detected singlesymbol in singlegroup formed response w (in the form of binary numbers). Shaper 22 weight response to the synchronization signal comprises comparing the device and the storage device. Comparing the device is intended for comparison of the magnitude of the maximum weight of response to the synchronization signal u (u can change from 1 to m) with the value of erroneously received singlesymbol mOsh. If u>mOshthen compare the device generates a control signal that allows to record in a storage device the number accurately detected singlesymbol mNEIS. If u ≤mOshthen compare the device generates a control signal that resets the storage device to zero. Thus, when the input detector 1 clock combination code serogroup at the output of the storage device, which is the output of the shaper 22 weight response to the synchronization signal, is formed by a weighting factor w. The value of the weighting factor varies depending on the number of errors in singlegroup:

Shaper 22 weight response to the synchronization signal may be implemented, for example, as described in the description of the invention to the patent of Russian Federation №2239953 class H 04 L 7/08, publ. 26.11.2004, bull. No. 31, 3.

From the output of the shaper 22 weight response to sync response w is supplied to the first input of the adder 2. The adder 2 is a parallel combinational adder, which has the s-bit input of the first term (low-order bits of the n bit input and n-bit inputs of the second term are respectively the first and the second input of the adder, while the other (n-s) bit inputs of the first summand is connected to the source of the "zero" level.

Unit 3 shift registers includes n-bit (n=[log2N·u]+1, N is the number of positions in one cycle) shift registers. United clock inputs and the United inputs reset shift registers are respectively a clock input and a reset input block 3 shift registers, and the signal inputs, the outputs of the last bits and outputs the first digits of all shift registers are respectively the signal input, main output and an additional output side 3 shift registers. Thus, the response of the detector 1 clock in the i-th clock interval, formed in the adder 2 with the previous account of the responses to the i-th position of the loop coming from the main output unit 3 shift registers. A new result of counting responses, more on w still written in the form n-bit binary number in the corresponding first cell (bits) shift registers unit 3 shift registers. When this binary number recorded up to that in the first cell block 3 shift registers, and all other numbers are stored in subsequent similar cells, in parallel shifted by one digit and the output unit 3 shift registers to the second input of the adder 2 is supplied the result of counting responses (i+1)-th clock interval. If the response of the detector clock (i+1)-th clock interval is not present, then the previous result account of the responses to (i+1)-th position of the cycle corresponds to the first cell block 3 shift registers, and other numbers that are stored in the same cell block 3 shift registers are shifted by one digit, etc. Unit 3 shift registers provides storage of account results of the responses to each position of the loop within the loop duration.

The value of n determines the memory capacity of account results. At the same time the account of the responses to each of the positions of the cycle with an additional output unit 3 shift registers sequentially arrive at the signal input of the decision making unit 4. In the final node 4, for example in the i-th clock interval, the input binary number in parallel code representing the current my the account of the responses to the i-th position of the cycle, simultaneously supplied to the first input unit 23 of the comparison, the input data block memory 24 and the second input unit 25 subtraction. In block 23 comparison of the input number is compared with the binary number stored in the block memory 24, and if it exceeds the number of block memory 24, the output of the comparison block 23 is formed impulse, which, when the input control unit 24 to the memory, provides the Erasure of the old and the new record (input) number. After that, the input unit 23 of the comparison are equal to a binary number. If the input number is equal to or less than the number stored in the block memory 24, the content of the latter is not changed. Thus, in block 24 of the memory is overwritten greatest the current account responses to any of the position loop, which is then compared to the results account for the subsequent positions of the cycle. The resulting difference between the number of unit 24 to the memory and the input number) at the output of block 25 subtraction in the form of binary numbers in parallel code is compared in block 26 comparison with a threshold number d received at its first input (which is the control input of the decision making node 4) from the output of block 14 of the choice of the threshold. In this case, if the number output unit 25 of the subtraction is less than the threshold number d, the output of the second unit 26 comparison to the reset input of the counter 27 comparison is "single" (deny) potential, the cat is who installs and maintains the "zero" state. When the i-th clock interval, the number output unit 25 of the subtraction is equal to or greater than the number d, the output of the second unit 26 comparison comes "zero" (enabling) the potential and the counter 27 comparison produces a single clock pulse received at its clock input, which is the clock input of the decision making unit 4. If the largest binary number written in the block memory 24 will exceed each of the N-1 subsequent numbers coming one after another with an additional output unit 3 shift registers, an amount equal to or greater than the threshold number d, the counter 27 comparison will produce the following N consecutive clock pulses, then the output is formed by the single pulse signal, which is supplied to the second input element 28 And to the first input element 29 And. the Passage of a single pulse signal output from the counter 27 comparison of the output element 28 And is in receipt of single pulse signal at the first input element 28 And the output unit 7 comparison. The passage of the single pulse signal output from the counter 27 comparison of the output element 29 And is carried out when receiving a frame synchronization signal from the output of the shaper 5 cyclic pulses to the second input element 29 I. Element 30 and provides the passage of the single pulse signal output resh the irradiation unit 4 or the output element 28 And, or from the output element 29 And. the output Signal of the decision making node 4 is a signal timing (phasing) of the device. In the first case, the synchronization signal at the output of the decision making unit 4 is formed with the loss of status of synchronism. In the second case, the output synchronization signal is generated in synchronous mode.

The sync signal from the output of the decision making unit 4 is supplied to the reset inputs of the block 24 of the memory unit 3 shift registers of the imaging unit 5 cyclic pulses, the counter 6 cycles and block 7 comparison. As a result, the block 24 and memory unit 3 shift registers, the counter 6 cycles and the trigger unit 7 are reset to "zero". Then from the output of block 26 comparison begins to act prohibiting "single" potential and the counter 27 comparison is also reset to "zero". The output signal synchronized final node 4 is the phase shaper 5 cyclic pulses so that at the output 19 of the device start coming regularly following cycle pulses, a time coinciding with the response of the detector 1 clock on the true singlegroup. The process of finding a temporary position of a cyclical clock in binary stream group signal begins again. When the next synchronization signal of the decision making node 4 will be formed under the condition detection timing is donkey loss condition of synchronism (single pulse at the output of the element 28 And) or synchronized (single pulse at the output of the element 29). In the first case, the sync signal deciding node 4 to change the phase of the initial installation of the driver 5 cyclic pulses. In the second case, the initial setup phase shaper 5 cyclic pulses will not change. The blocks 23 and 26 comparison can be performed, for example, in the form of n-bit binary comparator forming the sign "more", "less" with the appropriate sign of the difference values of the input operands, and a sign of their equality supplied to the first input of P and the second input of the Q blocks. Thus the outputs of the first and second blocks of the comparison is output P>Q comparator. Block memory 24 may be made in the form of n-bit register with parallel input. When this data inputs, a control input, a reset input and output unit 24 to the memory are respectively the input data, a clock input, a reset input and output data n-bit register. Block 25 subtraction can be performed in a full n-bit parallel adder. The bit width of the adder is provided a serial output connection of the transfer of the adder least significant bits with a carry-in input of adder senior ranks. To perform a full adder operation of subtracting a number from the unit 24 to the memory, coming to the first input of the subtraction unit, subject inversion, and the number coming from the additional output unit 3 shift registers is and the second input of the subtraction unit, inversion is not exposed (for example, see figure 2 - elements DD6, DD1.3-DD1.5). The counter 27 comparison and shaper 5 cycle pulses can be in the form of serially connected binary-synchronous decimal counter and decoder. When the reset inputs of the counter 27 comparison and shaper 5 cyclic pulses are input reset BCD counter. Accordingly, the clock inputs of the counter 27 comparison and shaper 5 cyclic pulses are clock inputs of the BCD counter. The outputs of the counter 27 comparison and shaper 5 cyclic pulse is the output of the decoder, determining a condition of BCD counters. During this phase shaper 5 cycle pulses can be performed by setting at zero the counter.

Fail (loss) state matching device for frame synchronization is determined if the number of accumulated responses for k cycles of observation exceeds the threshold number q. While the threshold number q and the number of cycles of observation k is determined depending on the quality of the communication channel. The failure condition of synchronism is determined using a counter 6 cycles, block 7 comparison unit 15 of the choice of the threshold and the block 16 ratio selection account. The counter 6 cycles determines the measurement interval by counting k pulses siklova the synchronization with the output device 19. The factor accounts k counter 6 cycles is selected by using the block 16 ratio selection account. Reset counter 6 cycles and block 7 compare by using the synchronization signal from the output of the decision making unit 4.

Figure 3 presents a functional diagram of the counter 6 cycles, which consists of a counting device (DD1), the comparison circuit (DD2) and element And (DD3). The counter 6 cycles represents a BCD synchronous pulse counter, the output of which is connected to the first comparator input binary numbers. The counting device is intended for pulse counting frame synchronization, which are received from the output device. The comparator is designed to recognize the achievements of the counting device status maximum account equal to the ratio of accounts k, which is served in the binary code output unit 16 to the second input of the comparator. Upon reaching the counting device maximum account k at the output of the comparator is formed by single potential. When this element And the output of the counter 6 cycles formed a single control pulse, which is input to the control unit 7 comparison. Reset counter 6 cycles is performed by the synchronization signal from the output of the decision making node 4 to the reset input of the counting device. Counter b cycles can be implemented, for example, on the chip: DD1 - K555 the E6; DD2 - CSP; DD3 - CLI.

4 shows a functional block circuit 7 comparison, which consists of comparing the device (DD1), item, OR (DD2), of element AND-NOT (DD3.1), inverter (DD3.2) and storage devices (DD4). The result of comparison output from the comparing device is briefly stored in the storage device when receiving a control signal at the control input unit 7 comparison. When P≤Q in the storage device is written to the logical signal "unit". When P>Q in the storage device is recorded signal is a logical "zero". In the first case (P≤Q) in block 7 of the comparison is determined by the breakdown condition of synchronism device for frame synchronization, and the second (P>Q) failure condition of synchronism is missing. Reset the storage device in the zero state is received at a reset input block 7 comparison of the synchronization signal from the output of the decision making unit 4. Unit 7 comparison can be implemented, for example, on the following chips: DD1 - CSP; DD2 - CLL; DD3 - CLS; DD4 - K555 on TM2.

The process of forming the threshold numbers d for the final node 4, the threshold numbers q for unit 7 comparison, the maximum weight of response to the synchronization signal u to detector clock 1 and factor accounts k (the number of cycles of testing by the output from the synchronism) with whom etchika 6 cycles as follows. The s-bit data input of the counter 8 distorted clock receives a binary number mOshequal to the number of errors in singlegroup. The counter 8 distorted clock calculates the total number of errors in synchrogram, and the counter 9, the total number of pulses transmitted for a certain period of time Q. the frame synchronization Signal from the output of the shaper 5 cyclic pulse sets the trigger 12 in the "single" status, and "single" signal (enable signal) from the output of the trigger 12 is fed to the reset inputs of the counter 11 clock pulses and a second input element 10 And. While the counter 11 clock pulses translates into "accounts" and permitted the passage of clock pulses from the output of the element 10 And to the clock input of the counter 9 total number of clock. The counter 11 provides a passage through the element 10 And for one cycle of a certain number of clock pulses equal to the number of pulses in singlegroup m, then resets the trigger 12 to "zero". The counter 11 a clock pulse signal of a logical "zero" output of the trigger 12 is reset to "zero" and is translated in the mode "stop". Counting the number R of distorted pulses during the time the account is quite a large number of such clock pulses Q, it is possible periodically to determine the probability (castest) erroneous pickup is and clock according to the formula P Osh=R/Q, i.e. to produce a current assessment of the degree of distortion of the received digital signal. The counters 9 and 11 may be performed as a shaper 5 cyclic pulses in the form of serially connected binary-synchronous decimal counter and decoder. Reset both counters - synchronous. Thus the decoder counter 11 clock pulses is configured to identify the state of the binary-decimal counter equal to the number of pulses in singlegroup m, and the decoder counter 9 total number of clock pulses is configured to identify the state of the binary-decimal counter equal to the number of pulses surveillance Q. the Trigger 12 can be made in the form of RS-flip-flop. When the input S is connected to the output of the shaper 5 cyclic pulses, and the input R to the output of the counter 11 clock pulses. The capacity of the counter 9 total number of pulses is equal to the value of Q, so after counting each Q clock pulses at its outputs a single pulse, with which the block 13 selecting the maximum weight response in blocks 14 and 15 of the choice of thresholds, as well as in block 16 of the selection coefficient accounts instead kept them in the binary number is overwritten by the contents of counter 8 distorted pulses. After that, the counter 8 distorted clock is reset to "zero" and the quality review process p is animemanga signal during the subsequent follow Q clock repeats.

The counter 8 distorted clock consists of summing device and a storage device. When the input data counter 8 distorted pulses are input summing device serves a number of erroneously received clock mOshfrom the second output of the detector 21 errors in synchrogram. This number is summed with the number of bugs in synchrogram accumulated during the previous period. To the control input of the counter 8 distorted pulses from the output of the shaper 5 cyclic pulses are received, the cyclic pulses. This provides a count of the counter 8 only distorted sync R belonging to true synchrogram. The counter 8 distorted clock can be implemented, for example, as described in the description of the invention to the patent of Russian Federation №2239953 class H 04 L 7/08, publ. 26.11.2004, bull. No. 31, 4.

Unit 13 selecting the maximum weight response, blocks 14 and 15 of the choice of the threshold and the block 16 ratio selection account depending on the values written to them in the binary number R make the selection, respectively, a certain number of maximum weight response to the synchronization signal u, the threshold number d, the threshold number q and k-factor. The selected number u, d, q and k output units 13, 14, 15 and 16 in parallel code are given correspondingly to the second input of the shaper 22 weight feedback or suggestions is and the synchronization signal, the control input of the decision making unit 4, the second input unit 7 and the data input counter 6 cycles. Unit 13 selecting the maximum weight response, blocks 14 and 15 of the choice of the threshold and the block 16 ratio selection accounts can be made in the form of permanent storage devices, memory elements which are recorded the results of calculations of numbers maximum weight response u, threshold numbers d and q, and the ratio of account k depending on the probability of erroneous reception of a single character of the input group of the digital signal (see Kalinnikov CENTURIES, tashlinskii A.G. Technique for finding the internal parameters of the system frame synchronization in parallel and recircularii search. - Ulyanovsk: UFWOC, 2002. 35 S. - Depv CVNI the defense Ministry 23.09.02. No. b, publ. STR, Serb, vol 61, 2002). The value of the measured probability of erroneous reception of a single character from the output of the counter 8 distorted clock is fed to the address inputs of the storage devices units 13, 14, 15 and 16. The output of numbers u, d, q and k blocks 13, 14, 15 and 16 is carried out when entering the control input reading (CS) permanent storage devices signal the end of the measurement the probability of erroneous reception of the synchronizing pulses POshfrom the output of the counter 9 total number of clock pulses. Thus, during the time of account Q shaper 22 weight response to the synchronization signal serves to max the maximum weight of response to the synchronization signal u, at a crucial node 4 - threshold number d, block 7 comparison threshold number q, and the loop counter 6 - factor account k, which can take in each case one of the h discrete values (gradation) depending on signal quality. The required number of gradations h maximum weight of response to the synchronization signal u, the threshold numbers d and q, and the ratio of account 1 is determined on the basis of maintaining the probability of false detection of the synchronization signal within the required limits with various changes in the size of ROsh. Under the laws of the formation of specific values of the maximum weight response urunit 13 selecting the maximum weight of the response threshold of the number of drunit 14 the choice of the threshold, the threshold number of qrunit 15 the choice of threshold, ratio account k unit 16 ratio selection account can be written in the form:

ur=F1(Ar≤POsh<Br),

dr=F2(Ar≤POsh<Br),

qr=F3(Ar≤POsh<Br),

kr=F4(Ar≤POsh<Br),

where F1F2F3F4- pre-selected rules, respectively, for block 13 selecting the maximum weight response, blocks 14 and 15 of the choice of thresholds and block 16 ratio selection accounts for which value of POsh=R/Q, taking the value is within the r-th period (r varies from 1 to h) dimensions, is in compliance with well defined values of the maximum weight response urthreshold numbers drand qrand factor accounts kr;rand Brrespectively the lower and upper bound values of ROshfor the r-th interval.

The required noise immunity of the device, which is determined by the probability of false detection of the synchronization signal, is achieved by the fact that the restoration of synchronism after its failure and the phasing device under a new cyclical position matching is carried out upon occurrence of two events: the definition of a critical node 4, a new position of a cyclical clock and failure detection (loss) cyclical synchronism with the counter 6 cycles, block 7 comparison of the block selection threshold 15 and block selection factor accounts 16. And with item 28 item 29 item 30 produces a sync signal at the output of the decision making node 4 in synchronous mode, and in the event of a failure of synchronism. In addition, the required noise immunity of the device is ensured by the choice of the law of formation of the maximum weight of response to the synchronization signal urfor block 13 selecting the maximum weight response threshold numbers drand qrfor units 14 and 15 of the choice of thresholds and factor accounts krfor block 16 ratio selection with the ETA on the respective measured values of R Oshwithin any r-th interval with boundaries Andrand Braccording to the principle: the higher the value of POshthe greater should be the maximum weight of a response to the synchronization signal urthreshold number of drfactor account krand the threshold number of qr. When this is achieved the minimum recovery time simultaneity, since the time interval of observation of the response of the detector 1 clock at the end of which the decision on the phase of the clock cycle, adaptive changes depending on the magnitude of ROshand in each specific case (at a certain value of POshis approaching the minimum possible, which will ensure the required immunity. The Q-value, which determines the ratio of the account of the counter 9 total number of pulses must be chosen, on the one hand, large enough to provide the desired precision of the estimate of the error probability POsha single character, on the other hand, is sufficiently low to ensure that the measurement of POshbetween two failures of synchronism in cycles and tracking of changes to the conditions of communication. If we assume that failures of synchronism in cycles occur relatively infrequently, i.e. intervals of time, much longer than the time of account Q cycle synchro is mulsow, in practice, the value of Q can be chosen as:

where B1- the upper boundary value of POshwithin the first measurement interval, which corresponds to the lowest threshold number of d1; [ ] means rounding to the nearest integer.

The above data confirm that the implementation of the use of the claimed device the following cumulative conditions:

the tool embodying the claimed device in its implementation, is intended for use in the receiving device sync cycles of transmission of discrete messages;

for the claimed device, as it is characterized in the claims, confirmed the possibility of its implementation using the steps described in the application or known before the priority date tools and methods;

the tool embodying the claimed invention in its implementation, is able to achieve perceived by the applicant of the technical result.

Thus, the claimed invention meets the criterion of "industrial applicability".

Device sync cycles containing Recognizer clock, the main output of which is connected to the first input of the adder, the output of which is connected to the signal input of the unit shift registers, basically the output of which is connected with the second input of the adder, as an additional output of the unit shift registers connected to the signal input of the decision making unit, which consists of the first block compare block of memory, the subtraction unit, the second unit of comparison and counter comparison with the first unit of comparison is connected to the control input of the memory block, the output of which is jointly connected to the second input of the first unit of comparison and the first input of the subtraction unit, the second input is combined with the first input of the first unit of comparison, and also to the input of the data memory block and is the signal input of the decision making node, a clock input and a control input which are respectively the clock input of the counter and the first comparison the input of the second block of comparison, a second input connected to the output of the subtraction unit, and the output of the second unit of comparison is connected to the reset input of the counter comparison with the final node is connected to the reset inputs of the former (cyclic pulses and block shift registers, a clock input which is combined with the clock inputs of the detector clock, a critical node, counter distorted pulses of the first element And the counter clock pulses and shaper of such pulses, and the control input of the decision making node coupled to the output of the first block selection threshold when the input counter data distorted synchronal is s connected to the secondary output of the detector clock, and the output of the counter distorted sync jointly connected to the address inputs of the block selection maximum weight response and the first block selection threshold and a count of the total number of clock pulses, the output of which is jointly connected to the reset input of the counter distorted pulses and also with the control inputs of the first block selection threshold and the block selection maximum weight response, the output of which is connected with the control input of the Recognizer clock, and the output of the counter clock pulses is connected to the reset input of trigger, the input set which is connected to the output of the shaper cyclic pulses to the control input of the counter distorted pulses and the trigger output is connected to the reset input of the counter clock pulses and a second input of the first element And whose output is connected to a clock input of a counter of the total number of pulses and the signal input of the Recognizer clock, clock input and the output of the shaper cyclic pulses are respectively the signal input, a clock input and output device, characterized in that it introduced the cycle counter, the third block comparison, the second block selection threshold, the block selection coefficient accounts, and at the crucial site entered the second element And the third element And the element OR, in this case the output of the counter comparison compatible with the but connected to the first input of the third element And and with the second input of the second element And whose output is connected to the first input of the OR element, with the second input connected to the output of the third element And the output element OR, which is the output of the decision making node is connected to the reset input of the memory block, and the first input of the second element And the second input of the third element And are respectively the first and second additional control inputs of the decision making node, the output of which is jointly connected to the reset inputs of the third block comparison and the loop counter, and the output of the counter distorted sync together also connected to the address inputs of the block selection factor account and the second block selection threshold, and the output counter of the total number of the pulses together are also connected to the control inputs of the block selection ratio of the invoice and the second block selection threshold, the output of which is connected to the second data input of the third block comparison to the first data input which is connected to the output of the adder, and the output of the third unit of comparison is connected to the first auxiliary input control of the decision making node, the second additional control input which is connected to the output of the device, which is also connected to the counting input of counter cycles, the data input of which is connected to the output of the block selection coefficient accounts, and Ihad cycle counter connected to the control input of the third Comparer.



 

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The receiver clock // 2242093
The invention relates to radio engineering

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2 cl, 9 dwg

FIELD: electric and radio communications; frame synchronization receiving devices of digital message transmitting and intercepting systems.

SUBSTANCE: proposed method includes sequential search at single-bit shift, identification of concentrated sync groups in group digital stream, and formation of responses when identifying concentration sync groups on tested clock intervals, and measurement of time intervals between sequential moments of responses across concentrated sync group identifier in terms of clock intervals. Primary sample of N ≥ 3 time intervals is accumulated. Secondary samples of time intervals between moments of first, second, through (N + 1)th reference responses, respectively, and arrival moments of all other primary-sample responses are calculated. Maximal common dividers of probable combinations of two or more time intervals are calculated and particular lines (spectrums) of distribution of maximal common dividers whose values exceed lower boundary of region of probable group signal cycle lengths are formed in the framework of secondary time interval samples. Integrated spectrum of maximal common divider values is formed by summing up all particular maximal common divider spectrums. Regular sequence of true integrated sync group responses is detected by fact of coincidence of maximal common dividers in integrated spectrum whose quantity exceeds desired threshold, and coincidence point abscissa of maximal common dividers is assumed as cycle length. True concentrated sync group responses are identified in primary implementation of stream by serial numbers of particular maximal common divider spectrums wherein we see multiple coincidences of maximal common dividers with found cycle length. Clock interval of group-signal next cycles commencement is predicted. Concentrated sync group responses appearing at predicted clock intervals are assumed as frame synchronization pulses. Decision on input in and output from frame synchronization mode is taken by composite "k/m-r" criterion.

EFFECT: enlarged functional capabilities due to affording frame synchronization in absence of a priori data on group-signal cycle length without impairing noise immunity.

1 cl, 9 dwg

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