Device for cylce synchronization of data blocks

FIELD: communications.

SUBSTANCE: device has control circuit, first input of which is connected to output of phase sign decoder, second input is connected to first clock input of device, third input is connected to second clock input of device, circuit OR, connected by its inputs to outputs of controlled system, and output of OR circuit is connected to third block for forming cyclic phasing signal, while the latter is made on basis of same circuit of logic numbers processing and consists of two numbers signals switchboard, arithmetic adder of two numbers, memory device, meant for recording K numbers, on basis of K data words, required for forming of cycle synchronization signal, AND match circuit, decoder, pulse counter, performing function of threshold element.

EFFECT: higher trustworthiness.

1 dwg

 

The present invention relates to communication technology, namely, devices frame synchronization of data blocks in the data transmission devices using error-correcting coding to improve the reliability of reception of the information.

The device cyclical phasing is one of the main blocks of telecode apparatus in the synchronous transmission of information, which largely determine the authenticity of messages. In the known device frame synchronization typically use special cyclic combination that precedes the message being transmitted resistant passage and at the same time eliminating false starts equipment. To exclude false positives usually significantly increase the number of digits in cyclic combinations [Martynov E.M. Synchronization in systems of transmission of discrete messages. M: the Relationship 1972 (str-186)].

A disadvantage of the known device is a significant probability of false starts of the receiver telecode equipment when working on real communication channels in the presence of interference, and reduced speed of information transfer, as required, the additional time required for transmission of the cyclic combination that reduces the bandwidth of the communication channel.

A device for siklova the sync blocks of information, coded FSO code [asssss No. 849521 H 04 L 7/08, publ. 25.07.81], adopted for the prototype.

The device frame synchronization node contains error detection is made of two series-connected filters Huffman and register node, and filter Huffman consists of a register filter and adder filter, the decoder phase characteristic, which is connected to an input of the second output node of the error detection, the block forming the frame synchronization signal, the first input connected to the first output of the second filter Huffman site error detection, and the second input is connected to the output of the decoder, the phase characteristic.

A significant drawback of the above device frame synchronization information units selected by the authors for the prototype is the following: fault counter from one to n of the total number K, when n≤K-P (where K is the total number of counters, R - number of counters selected for the threshold, n is the number of faulty meters of the device, which may correct the signal processing sequential phasing)incurred in the production cycle of the products, as well as during operation when operating on channels (lines) without noise (without distorting factors) remain unnoticed, because without functioning n defective accounts is Chikov when receiving a block of information will overcome the threshold R and thus, correctly determined the end of the information block information and the generated frame synchronization signal (SSS)to ensure proper decoding of a data block.

When working on real communication channels in the presence of interference can be recorded correctly certain non-coded information words in a faulty meters, which for this reason will be excluded when calculating the threshold R for the formation of SCS. When there is the defective one to n counter (K) device threshold R may not be overcome. In this case SCS will not be generated and decoding of a data block will be impossible. This will lead to a significant reduction in the reliability of reception of the information on real communication channels. For exceptions noted in the process of training devices during acceptance testing requires special expensive test equipment, additional structural complexity of the device and special process audits, verifying the serviceability of all the counters in the prototype. Similarly, during operation in the program of routine maintenance should be provided of the operation to determine the correct operation of all the counters, which also require the use of specially who enoy and test equipment. A marked disadvantage of the device frame synchronization (sequential phasing) increases the cost of manufacture and increases the cost of routine maintenance during operation. In addition, there is a probability that in the interval of time between the two regulations, fault counters (1 to n) will remain undetected, and the complex connection with the use of the device frame synchronization will operate with reduced characteristics, the most important parameter is the reliability of the connection.

A disadvantage of the known device for frame synchronization block information is also insufficient reliability of the device due to complex hardware implementation, especially when the number of counters To quite large.

The aim of the invention is to simplify the hardware implementation of the device by replacing the counters, devices, and they are composed of decoders, control circuits (in the prototype for ease of description they were not specified) one logical processing circuit numbers, resulting in increased reliability of operation and, as a consequence, the reliability of data reception, the improvement of production technology and technology use, as well as improving weight and size characteristics of the device. However, the use of a single logical schema processing numbers when the failure or malfunction of any component of the device frame synchronization will lead to failure of the device as a whole, which is immediately detected in the automatic control mode, complex communication, and therefore the characteristics of the device in terms of reliability of data reception remain constant and equal to theoretical values at the time of use. It does not require special maintenance work, which also reduces the cost of operation of the device. This objective is achieved in that the device frame synchronization node contains error detection is made of two series-connected filters Huffman and register node, and filter Huffman consists of a register filter and adder filter, the decoder phase characteristic, which is connected to an input of the second output node of the error detection, the processing unit cyclical phasing, the first input connected to the first output of the second filter Huffman site error detection, and the second input is connected to the output of the decoder, the phase characteristic. New is the fact that it introduced the control circuit, the first input of which is connected to the output of the decoder, the phase characteristic, the second input is connected to the first clock input the device is VA, the third input is connected to the second clock input of the circuit OR connected with its inputs to the outputs of the control circuit, and the output of the circuit OR connected to a third input of the processing unit cyclical phasing (BFSZF), and the processing unit cyclical phasing performed on the same logic processing numbers and consists of the switch signals of the two numbers, arithmetic adder of two numbers, a storage device designed to record To numbers, the number of information words required for the formation of the frame synchronization signal, schema matching And decoder, pulse meter, perform the function of the threshold element, and discharges from the sixth to the tenth input B of the switch signals of the two numbers is connected to the first input BFSZF, the discharge from the first to the fifth and eleventh input B of the switch signals of the two numbers is connected to the power bus, and the twelfth bit of the input B of the switch signals of the two numbers is connected with the bus “signal ground”, the switch signals of the two numbers in their places of entrance And connected to the outputs of the storage device, the outputs from the first to the eleventh switch signals of the two numbers is connected with the discharge from the first to the eleventh input B arithmetic adder of two numbers, the twelfth bit of the input B and the twelfth is azrad log And arithmetic adder two numbers connected to the power bus, the carry-in input of P0arithmetic adder of two numbers is connected to the output schema matching And schema matching And is connected to its first input with the output of the decoder and a second input connected to the second input BFSZF, the clock inputs of the storage device is connected to the third input BFSZF, the inputs of the decoder is also connected to the outputs from the first to the fifth storage device, the information input D which is connected to the output bits from the first to the eleventh arithmetic adder of two numbers, output the twelfth discharge of which is connected to a clock input of the pulse counter enable input V which is connected with the second output of the control circuit, and the installation log R pulse counter and on the installation inputs R of the storage device signal initial setup WELL, at the output of the pulse counter is formed by a frame synchronization signal (SSS).

The invention is illustrated by the drawing, which shows the structural diagram of the device frame synchronization data blocks.

The device frame synchronization node contains error detection 1, consisting of two series-connected filter Huffman 2, each of which, in turn, consists of register 3 and the adder 4; register node 5, the decoder phase characteristic 6, scheme administered the I 7, scheme OR 8, the processing unit cyclical phasing 9, performed on the same logic processing numbers, which consists of the switch signals of the two numbers 10, an arithmetic adder of two numbers is 11, the storage device 12 intended to write To number, number To the data words required for the formation of the frame synchronization signal, schema matching And 13, the decoder 14, the pulse counter 15, which performs the function of the threshold element.

The device operates as follows.

The information provided on the information input Ref. And node error detection 1, is converted into the first filter Huffman 2, consisting of a register of the filter 3 and the adder filter 4, is fed to the second filter Huffman 2 and further register of node 5, the output of which is fed to the input of the decoder, the phase characteristic 6. The structure of the filters Huffman 2, register of node 5 and decoder phase characteristic 6 is determined by the polynomials selected for encoding. In the described embodiment, for example, the code uses Bose-Chowdhury-Falkvinge (31,16) (BCH). In the allocation phase characteristic in the decoder phase characteristic 6 from the output register of the filter 3 of the second filter Huffman 2 bits from the sixth to the eleventh input B of the switch signals of the two numbers 10 processing unit cyclical phasing 9 p the steps five digit number, corresponding to the number of the code words in the information unit received information sequence. The switch signals of the two numbers 10 for the two inputs B and a connected five younger bits of the input B to the power bus. The connection is due to the fact that the correct phase characteristic (AF) can be selected only on the thirty-first bit sequence BCH code. The eleventh digit of the input B of the switch signals of the two numbers 10, as the first five, connected to the power bus, the twelfth bit of the input B of the switch signals of the two numbers 10 is connected to signal ground. The bits of the second input And the switch signals of the two numbers 10 are connected to the outputs of the storage device 12. The input R of the switch signals of the two numbers 10 is connected via a second input BFSZF 9 to the output of the decoder, the phase characteristic 6. The outputs from the first to the eleventh switch signals of the two numbers 10 connected to the discharge from the first to the eleventh input B arithmetic adder of two numbers is 11, which writes the results of the summation of the signals at its inputs a and B, and the discharge from the second to the eleventh input And arithmetic adder two numbers 11 connected to the bus "signal ground".

The carry-in input R0signal transfer arithmetic adder two numbers 11 is connected to the output of the circuit matches And 13. Scheme ppsr is Denia And 13 connected to its first input connected to the output of the decoder 14, and a second input through the second input BFSZF 9 to the output of the decoder, the phase characteristic 6.

The inputs of the decoder 14 is connected to the outputs from the first to the fifth storage device 12. The output bits from the first to the eleventh arithmetic adder two numbers 11 are connected to information inputs D of the storage device 12. The output of the twelfth digit arithmetic adder two numbers 11 is connected to a clock input of the pulse counter 15, which performs the function of the threshold device.

Enable input V pulse counter 15 is connected to the second output of the control circuit 7. Installation input R of the pulse counter 15 is connected to the signal initial setup WELL received at the input device frame synchronization. From the output of the pulse counter 15, the frame synchronization signal enters the interfacing device for further processing.

The decoder phase characteristic 6 upon detection of the combination of the phase characteristic (OP) error-free code word of the block of information in the information sequence issues a control signal to the first input of the control circuit 7. The second input of the control circuit 7 is the first clock input of the frame synchronization I 1.

To the second input of the control circuit 7 receives a signal with a clock frequency of, For·m times the speed loads the Oia elements of the information words

K·m·FPFP,

where K is the number of correctly computed numbers of data words required for calculation and generation of the frame synchronization signal block of information;

m is an integer (for example m=2-3);

FPFPthe arrival rate at the input of the elements of the information words.

The third input of the control circuit is a second clock input of the frame synchronization I 2.

The third input of the control circuit 7 receives a signal with a frequency equal to the rate of supply of the elements of the information words (FPFP).

From the first output control circuit 7 to the first input circuit OR 8 receives the generated phase and time relative to the signal FPFPsignals of the phase characteristic in the middle of the period of time corresponding to the "log 1" signal FPFP. From the second output of the control circuit 7 to the second input circuit OR 8 is supplied To the clock signals overwrite the numbers in the cells of the storage device in the time period corresponding to the "log 0" signal FPFP.

The output of the circuit OR 8 is connected to the clock inputs of the storage device (memory) 12.

The storage capacity should be sufficient to account For the numbers (the number of phase characteristics used to generate frame synchronization signals, or the number of counters in proto the IPE), the maximum value of each number is equal to the number of bits in a block of information, i.e. is determined by the product

L·M,

where L is the number of bits in the word BCH information block;

M - the number of words BCH code in the info block.

As a storage device for recording numbers To (with a maximum value of L·M) and sequential overwrite them (transfer) it is convenient to use shift registers equal in number to the PLand the number of stages of each of RLregisters equal to K.

The storage device is made of PLregisters, each register K bits, where PL- bit binary number of bits of the information block (L·M).

Upon receipt of error-free code word in the node error detection 1 device frame synchronization in register 3 filter Huffman 2 is formed by a number containing the number of information words BCH five digits in the binary number. The decoder phase characteristic 6 upon detection of the combination of the phase characteristic (OP) code data word of a data block outputs a signal to the input R of the switch signals of the two numbers 10, in which the switch connects the signals from its output to the input B of the arithmetic adder of two numbers is 11.

The generated number at the output of the arithmetic adder two numbers 11 to be equal to the number b is t in the block of information from the start block to the end of a data word, in highlighting this OP generated by the decoder phase characteristic 6.

This number is the first signal of the series K·FPFPwith the control circuit 7 via a scheme OR 8 is written in the first cell of register (1-PL) a storage device (memory) 12.

If the OP correctly generated for the first data word, the first signal FC in the first cell of the registers (the first step memory) will be written the number L if for the second word in the first cell of the registers will be written the number 2L, for the third word - 3L and so on. Signals from the series·FPFPcoming from the control circuit 7 through the scheme, OR 8 number of first-stage registers memory 12 sequentially overwritten - cell 1-RLin cell 1'-R'L; cell 1'-R'Lin cell 1"-P"Land so the Last signal from the series K·FPFPreceived in the memory 12, the number will be rewritten in cell 1To-R

K
L
.

The decoder 14 connected by its inputs to the outputs from the first to the fifth of the final stages of the five memory registers 12 (for consideration of the example code BCH (31/16)), provides the translation of the 5 least significant bits of the state 11111 state 00001 (bypassing the state 00000) transfer 1 in the high order bit (this operation simplifies the estimatio numbers L*M) by adding the number two.

With the arrival of the next signal FPFPthat sequence To the bars, from the control circuit 7 via a scheme OR 8 will happen consecutive overwriting numbers in the corresponding bits of the registers. After performing dubbing to the number in an arithmetic adder two numbers 11 shall be increased by one or two (the number 2 in the times when the decoder 14).

Subsequent operations including determining the number of received bits in the block of information recorded on the first signal generated by the OP with the arrival of subsequent signals FPFPsimilar to the above.

When forming the second signal FP by connecting the output of the decoder, the phase characteristic 6 to prohibit the entrance of schema matching And 13 with a signal from the output of the circuit matches And 13 are prohibited from performing the arithmetic operations of addition by the adder of two numbers is 11. Signal OP through the scheme, OR 8 previously recorded number of the first bits of the registers (1-PL) ZU 12 is rewritten in the second discharge registers (1'-R'L) Memory 12, and released the first bits of the registers (1-PL) Memory 12 is written to the generated number that corresponds to the selected AF.

Then with the arrival of subsequent signals FPFPthe steps of the registers will be overwritten already two numbers defining the number of bits of the information block, but calculated:

the first is formed on the first decoder phase characteristic 6 signal FP and the operations of summation by the described algorithm

the second is formed on the second decoder phase characteristic 6 signal FP and the operations of summation by the described algorithm.

That is, upon proper reception of two data words both numbers recorded in two levels of registers memory 12 will be the same.

With the arrival of the next signal OP of the above operations with numbers in the speed register memory 12 will be similar.

Thus, at the end of the information block, provided that the number of generated signals FC when receiving a unit of information equal to or greater than K, the registers in the memory 12 is written To the numbers:

1 the number in the first digit registers (1-PL) ZU 12,

2 the number of second bits in registers (1'-PL) ZU 12,

To the number To the bits of the registers (1K-R

K
L
) ZU 12.

If all words are spelled correctly with the correct numbers of data words, the number of all stages of the register memory 12 will be the same and equal to the number of bits of the information block.

After the end of the signal FPFPcorresponding to the last bit of information block with what halami series K· FPFPwith schema OR 8 through the memory 12 and the switch signals of the two numbers 10 arithmetic adder two numbers 11 with the output of PL+1issues To signal overflow. When connecting the output of PL+1arithmetic adder two numbers 11 to the clock input of the pulse counter 15, and the connection enable input V pulse counter 15 to the second output of the control circuit 7 that generates the signals of the series To·FPFPoutput P of the pulse counter 15 produces signal SCS (signal overcoming the selected threshold, when the total number To signal overflow).

Errors and distortions in the code word signal SCS will be issued to the pulse counter 15, if the number of overflows arithmetic adder two numbers 11 is not less than the threshold R, i.e. when at the end of the information block in the memory registers 12 will be recorded not less than R numbers correctly with certain numbers of data words.

Thus, the use in the inventive device to a single schema logical processing numbers instead of counters used in the prototype, significantly reduces the number of chips in the device, and therefore, reduces the amount of devices in comparison with the prototype by about 25-50%. Indeed, increasing the number To all the links and elements of the device are virtually unchanged, and only increases the number of rasra the s R Lregisters, which slightly increases the number of chips of the device. A significant decrease in the number of elements in the device in the appropriate number of times increases the reliability and reduces the cost of the device.

However, the use of a single logical schema processing numbers when the failure or malfunction of any component of the device frame synchronization will lead to failure of the device as a whole, which is immediately detected in the automatic control mode, complex communication, and therefore the characteristics of the device in terms of reliability of data reception remain constant and equal to theoretical values at the time of use. It does not require special maintenance work, which also reduces the cost of operation of the device.

The device frame synchronization node contains error detection is made of two series-connected filters Huffman and register node, and filter Huffman consists of a register filter and adder filter, the decoder phase characteristic, which is connected to an input of the second output node of the error detection, the processing unit cyclical phasing, the first input connected to the first output of the second filter Huffman site error detection, and the second input connection of the EN with the output of the decoder, the phase characteristic, characterized in that it introduced the control circuit, the first input of which is connected to the output of the decoder, the phase characteristic, the second input is connected to the first clock input of the third input is connected to the second clock input of the circuit OR connected with its inputs to the outputs of the control circuit, and the output of the circuit OR connected to a third input of the processing unit cyclical phasing (BFSZF), and BFSZF performed on the same logic processing numbers and consists of the switch signals of the two numbers, arithmetic adder of two numbers, a storage device designed to record To numbers according to the quantity of data words required for the formation of the frame synchronization signal, schema matching And, decoder, pulse meter, perform the function of the threshold element, and discharges from the sixth to the tenth input B of the switch signals of the two numbers is connected to the first input BFSZF, the discharge from the first to the fifth and eleventh input B of the switch signals of the two numbers is connected to the power bus, and the twelfth bit of the input B of the switch signals of the two numbers is connected with the bus “signal ground”, the switch signals of the two numbers in their places of entrance And connected to the outputs of the storage device, the outputs from the first on the eleventh switch signal the two numbers are connected with the discharge from the first to the eleventh input B arithmetic adder of two numbers, the twelfth digit of the input B and the twelfth bit of the input And the arithmetic adder of two numbers is connected to the power bus, the carry-in input R0arithmetic adder of two numbers is connected to the output of the circuit matches “And”schema matching “And” connected to its first input with the output of the decoder and a second input connected to the second input BFSZF, the clock inputs of the storage device is connected to the third input BFSZF, the inputs of the decoder are connected to the outputs from the first to the fifth storage device, the information input D which is connected to the output bits from the first to the eleventh arithmetic adder of two numbers, output the twelfth discharge of which is connected to a clock input of the pulse counter enable input V which is connected with the second output of the control circuit, and installation input R of the counter pulses and installation inputs R of the storage device signal initial setup WELL, at the output of the pulse counter is formed by a frame synchronization signal.



 

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