Adaptive code frame synchronization device

FIELD: digital data transfer systems for frame synchronization of correcting codes including noise-immune concatenated codes.

SUBSTANCE: proposed device for adaptive code frame synchronization has delay register 1, error detection assembly 2, decoder unit 10, counter 11, threshold unit 21, synchronizing-sequence generator 18, modulo two output adder 12, random-access memory 15, modulo two adder unit 16, number comparison unit 13, full adder 19, synchronization counter 17, error counter 14, and code converter 20. Error detection assembly is set up of two series-connected Huffman filters 3, 4 and syndrome register; each Huffman filter has register 6/7 and modulo two adder 8/9.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

 

The invention relates to systems for the transmission of discrete data and can be used for frame synchronization correcting codes, in particular robust cascade codes.

In the device code frame synchronization clock features defining the beginning (end) of error-correcting code, passed in the error-correcting code. For frame synchronization is not required, the transmission in the communication channel additional characters, and uses the redundancy of error-correcting code. After the establishment of the frame synchronization signs synchronization are removed from the error-correcting code, does not reduce the ability of code to detect and correct errors.

The most effective use of the code frame synchronization in noise-tolerant cascade codes. In this case, synchronization is provided by repetition of signs synchronization in different words of the inner code error correcting cascade code.

The main task is to increase the noise immunity of the device frame synchronization when operating in non-stationary communication channels with variable parameters and a high level of noise. In such channels, it is advisable to use the device, the adaptive code frame synchronization. Adaptation in the proposed device called the W automatic and purposeful change of code frame synchronization in order to achieve optimal functioning of the device under varying conditions of reception of messages in the communication channel.

You know the device code frame synchronization, containing a register of the delay, the node detecting the error, the block decoders, a counter, a threshold unit, a clock generator sequence, the output of the modulo two, and register delays and node error detection combined input and is connected to the information input device, the node error detection is made in the form of two series-connected filters Huffman and syndrome register, and each filter Huffman consists of serially connected register and modulo two, the input of the syndrome register is connected to the output of the second filter Huffman, and the output connected to the input of block decoders, the output of clock generator sequence connected to the first input of the output adder modulo two, a second input connected to the output register delay, and the output is connected with the information output device (USSR Author's certificate No. 849521, CL H 04 L 7/08, publ. 1981).

However, this device has insufficient immunity.

Closest to the proposed device is the device (prototype)containing the register delay, the node detecting the error, the block decoders, a counter, a threshold unit, a clock generator sequence, the output of the modulo DV is, random access memory (RAM), a block of adders modulo two, the Comparer rooms, a full adder and counter synchronization, and register delays and node error detection combined input and is connected to the information input device, the node error detection is made in the form of two series-connected filters Huffman and syndrome register, and each filter Huffman consists of serially connected register and modulo two, the input of the syndrome register is connected to the output of the second filter Huffman, and the output connected to the input of block decoders, the output of clock generator sequence connected to the first input of the output adder modulo two, a second input connected to the output register delay, and the output is an information output device. The first output of the block decoders connected to the input of the adders modulo two, the other input of which is connected to the output register of the second filter Huffman, the second output of block decoders connected to the enable input of the RAM write, output unit modulo two are connected with inputs of block comparisons of rooms, the other input of which is connected with the older bits of the counter, the output of block comparisons of rooms connected with the older bits of the address input of RAM, the younger RA is a series of address input of which is connected with the younger digits counter, the clock input of the counter is connected to the synchronization input of the device, and also to a clock input of the counter synchronization, set the inputs of which are connected to the outputs of block modulo two, the enable input of counter synchronization connected to the output of the threshold unit, the output of the RAM is connected to the input of the full adder, the output of the full adder is connected with the information input RAM output counter synchronization connected with the allow input of the clock generator sequence is synchronized output device (Patent RF №2197788, IPC 7 H 04 L 7/08, publ. 2003).

A disadvantage of the known device is a low noise, due to the fact that, when the frame synchronization is not considered as receiving code words of the channel.

The purpose of the invention to increase the noise immunity of the device code frame synchronization messages and, consequently, enable the operation of the device in communication channels with high noise level due to the fact that the presence of frame synchronization is determined taking into account the quality of the communication channel.

To achieve the objectives of the proposed device adaptive code frame synchronization, containing a register of the delay, the node detecting the error, the block decoders, a counter, a threshold unit, a clock generator in which sledovatelnot, the output of the modulo two, random access memory (RAM), a block of adders modulo two, the Comparer rooms, a full adder and counter synchronization, and register delays and node error detection combined input and is connected to the information input device, the node error detection is made in the form of two series-connected filters Huffman and syndrome register, and each filter Huffman consists of serially connected register and modulo two, the input of the syndrome register is connected to the output of the second filter Huffman, and the output connected to the input of block decoders, the output of clock generator sequence connected with the first input of the output adder modulo two, a second input connected to the output register delay, and the output is an information output device. The first output of the block decoders connected to the input of the adders modulo two, the other input of which is connected to the output register of the second filter Huffman, the second output of block decoders connected to the enable input of the RAM write, output unit modulo two are connected with inputs of block comparisons of rooms, the other input of which is connected with the older bits of the counter, the output of block comparisons of rooms connected with senior digits of the address input of RAM, low-order bits of the address input of which is connected with the younger bits of the counter, the clock input of the counter is connected to the synchronization input of the device, and also to a clock input of the counter synchronization, set the inputs of which are connected to the outputs of block modulo two, the enable input of counter synchronization connected to the output of the threshold unit, the output of the RAM is connected to the input of the full adder, the output of the full adder is connected with the information input RAM output counter synchronization connected with the allow input clock timing sequence and an output of the synchronization device. What's new is that in the device entered the adder errors and code Converter, and the output of block decoders connected to the input of the adder errors, the output of which is connected to the input of the code Converter, the output of which is connected with the second input of the full adder, the output of which is connected to the input of the threshold unit.

The drawing shows a structural electrical diagram of the device.

Device adaptive code frame synchronization register contains delay 1, the node error detection 2, is made of two series-connected first filter 3 and the second filter 4 Huffman and syndrome register 5, and each filter is respectively the C registers 6 and 7 and adders 8 and 9 modulo two, the block decoders 10, a counter 11, the output of the adder 12 in module two, unit comparison of rooms 13, the adder error 14, RAM 15, a block of adders 16 modulo two counter synchronization 17, the generator 18 synchronizing sequence, the full adder 19, a code Converter 20 and the threshold block 21.

The device operates as follows.

On the transmission side is formed in the input sequence. This sequence is the sum modulo two of the three sequences: internal binary cascade code with1synchronizing of binary sequences with2and the sequence c3violating the cyclical properties of the source code.

First, in the transmitting side of the original message, the volume of k m-ary (m>1 characters, coded m-ary error-correcting code, for example, m-ary error-correcting code is a reed-Solomon. A reed-Solomon code is the outer code or code first-stage robust cascade code.

In the coding of the information is received code word reed-Solomon code (n, k), the information length is equal to k, and the block - n characters.

Further information is coded with a binary code, such as binary Bose - Roy-Chaudhury - Hocquenghem (BCH codes) with the check polynomial h1(x). Code BCH is an internal code or code is m second-stage robust cascade code. Code BCH has parameters: n1- block code length, k1information length of the code.

The source information for each word of the BCH code are symbols of a reed-Solomon code, considered as a sequence of binary symbols. A coding BCH code will be n binary words BCH code (n1,k1).

Next is the addition modulo two synchronizing sequence2with the words BCH code. As a synchronizing sequence selected binary code with block length n1and information length of k1for example, the code of the reed-Muller (RM) 1-th order (sequence maximum period) with the check polynomial h2(x). Between the numbers of words in concatenated BCH code and an information part of the synchronizing sequence (code RM) is one-to-one correspondence. The first word BCH is folded sequence obtained by encoding 1 code of the Republic of Moldova, the second in the encoding code RM-2, etc. This addition is performed with all the words BCH code. If the check polynomials summable codes h1(x) and h2(x) are coprime and are divisors of binomial xn1+1, the result is n words cyclic BCH code with block length n1and information - k1+ksub> 2. This code will be quite certain guaranteed minimum code distance and to have certain curative properties.

The third sequence with3which are the words BCH, will be constant for all words in the sequence of length n1bits that violate the cyclical properties of BCH code. Such a sequence may be any sequence that is not a code word BCH code, for example, a sequence of 10000...000.

At the receiving side input sequence, formed as the sum of three sequences, is supplied to the information input device frame synchronization. When this input sequence is written to the register delay 1 and simultaneously fed to the input node of the error detection 2, consisting of two series-connected first filter 3 and the second filter 4 Huffman and register syndrome 5.

In the first filter 3 and the second filter 4 Huffman is the multiplication of the input sequence, respectively, on a test polynomials BCH codes and PM - h1(x) and h2(x). Thus, in the first filter 3 Huffman is calculated syndrome BCH code or a sequence with1and in the second filter 4 - syndrome code of the Republic of Moldova or the sequence c2.

Upon receipt of error-free words with ngram code is zero and the syndrome register 5 will be written to the combination of the d 0corresponding transformed into the first filter 3 and the second filter 4 Huffman sequence c3.

The proposed device provides a cyclic synchronization is not only inerrant words BCH code, but according to a BCH code, accepted with errors.

When the input misspelled words, the multiplicity of which lies within the correcting ability of the code in the syndrome register 5 will be written to a combination of some set {di}, the corresponding transformed into the first filter 3 and the second filter 4 Huffman sequences with3and the error vector.

The block decoders 10 upon detection of combinations of d0or a combination of the set {di} generates the enable signal to the write input of RAM 15.

At this point of time in the register 7 of the second filter 4 Huffman is a combination that uniquely corresponding to the sequence c2because the sequence c1removed by the first filter 3 Huffman, and the sequence c3is constant.

This combination from the output of the register 7 is supplied to the input of the adders 16 modulo two. In block adders 16 corrects discharges considered combination so that at the output of adders 16 module two was the combination corresponding to the number of words BCH code. For this unit on the encoders 10 by detecting combinations of the syndrome in the syndrome register 5 determines the vector of errors and issues appropriate correction signals to the second inputs of unit adders 16 modulo two.

The block structure of the decoders 10 corresponds to the combinations of the syndrome to correct the error vectors. Combination syndrome, you should recognize that obtained by calculating a syndrome for each of the required vector of errors. Example of construction of the block decoders errors presented in Clark, J., ml, Kane, J. Encoding with error correction in digital communication systems: Lane. from English. - M.: Radio and communication, 1987, p.96-101.

Adjusted combination with a unit output of the adders 16 is supplied to the first input of the comparison of numbers 13. To the second input of block comparisons of rooms 13 receives signals from the senior ranks of the counter 11.

The counter 11 operates at a clock frequency received at the input of the synchronization device. The frequency of cycles is equal to the rate of supply of information to the input device.

The counter 11 is composed of two parts: the low-order bits are the conversion factor equal to the word length code BCH - n1, the most significant change in signal transfer with low and consider the number of words BCH code received at the input device. The number of high-order bits of the counter is selected to provide an account of all n words BCH code cascade code.

In block compare numbers 13 calculates a difference between the numbers of code words, calculated on the adopted code words and counting sketchcom. For correctly received code words this difference should be constant, since the most significant bit of the counter 11 is changed synchronously with the numbers of code words received at the input device code frame synchronization.

The output of the Comparer rooms 13 is connected to the address inputs of the RAM 15. The remaining address inputs of the RAM 15 is connected with the younger bits of the counter 11. Thus, the address input of RAM 15 receives signals that determine the phase of the received code words or the location of the code words in concatenated BCH code.

In the RAM 15 for each address corresponding to the phase of the received code words stored number corresponding to the total reliability received from the communication channel code words. Signal installation, which is not shown in the figure, the contents of the RAM 15 is set to zero. With the arrival of the next code word to the contents of the RAM 15, the corresponding total reliability code words adopted in this phase, using the full adder 19 adds the specified number, the value of which depends on the reliability of the received code word.

Link quality is determined by the total reliability of the received code words.

Assessment of the reliability of a received code word is the number of errors in the code word using the adder errors 14 and the code Converter 20.

Assessment dost is loyalty to separate a received code word is performed as follows. Authenticity code word is determined by the number of errors in the code word. Estimated number of binary digits f, which is used to detect errors in the block decoders 10, will be equal to

where k, n and information, and block length of the code, respectively, a t - number of errors in the code word.

Authenticity code word γ(t) for the detection of t error estimate of the relative number of bits of the code word used for error detection, and written as

thus the reliability of the code word, which is not detected any errors, equal β - some factor introduced to normalize the values of confidence. The normalizing factor chosen so that the value of reliability was expressed as a whole number (or a value close to an integer), which allows to simplify the implementation of the device. With the increase in the number of errors t in a received code word authenticity code words in accordance with the last formula will be reduced.

At the output of block decoders 10 when receiving a code word is a binary combination corresponding to the error vector. This binary combination is fed to the input of adder error 14, which performs the summation of the bits of the input binary combination is, and as a result, the output of the adder error 14 produces the number of errors t in a received code word. Next is the number of errors received at the input of the code Converter 20. Code Converter implements a functional relationship between the number of errors t in a received code word and the reliability of the code word γ(t), which is defined by the formula (1). The code Converter is a combinational logic circuit. To implement this scheme, a functional relationship according to the formula (1) set in tabular form. Argument of this functional dependence, the specified table will be the number of errors in the code word, and the output is the reliability of the code word γ(t). The number of errors in the code word can vary from 0 to the maximum number of errors that can detect error-correcting code. To be used in practice, error correcting codes, this number, as a rule, will not exceed the value of two, three errors, and table-valued functional relationship according to the formula (1) will be given only three or four points. This tabular dependence will be considered as the truth table of some Boolean functions. The truth table logic function will create a logic function and Boolean combinational circuit that implements this table, as described, for example in Wakerly j. F. P is elektrownie digital devices volume 1, Moscow, Postmarket, 2002, str. Due to the fact that the volume of the table defining the functional relationship (1) is small, and the implementation of the code Converter 20 will require minor hardware costs.

After receiving the output of the full adder 19 total reliability of the received code words is a comparison of the reliability threshold value.

If the total reliability of the code words with matching numbering and synchronizing sequences exceeds a certain pre-selected threshold γmax

it is driven synchronization. This means that the input information is supplied for further processing. The excess of the total reliability of the received code words given value of the threshold is determined by the block 21. At the output of the threshold unit 21 occurs, the enable signal received at the first input of counter synchronization 17. This signal is set counter synchronization 17 in the state corresponding to the number of the last received code word. While the number of the last code word in which occurred the threshold is exceeded, the output of unit adders 16 modulo two comes on the installation inputs counter synchronization 17. The enable signal low-order bits of the counter of synchronization is then 17 are set to 0, and in the older records the number of the last code word.

The full amount of counter synchronization 17 is equal to n code words of the code BCH or n·n1because the length of each word BCH is n1bit. To the clock input of counter synchronization 17 is supplied with the clock frequency of the input synchronization device code frame synchronization, equal to the speed information is received at the input of this device, and after receiving all words BCH code cascade code at the output of the counter synchronization 17 there is a signal overflow.

This signal generator 18 synchronizing sequence starts generating a synchronization sequence is equal to the sum of sequences with2and c3.

The sync sequence is fed to the first input of the output adder 12 modulo two.

The number of bits of the register delay 1 is selected equal to the length of the entire cascade code, and at the onset of the synchronization sequence to the second input of the output adder 12 modulo two received code word cascade code.

The sync sequence is removed from the code words, and an information output device code frame synchronization receive words of the source code BCH or a sequence with1.

Simultaneously, the signal overflow with you the ode counter synchronization 17 is output synchronization device code frame synchronization, accompanying the beginning of the cascade code.

In the proposed device the number of code words with matching numbering and synchronizing sequences, in which the decision about the presence of frame synchronization is established depending on the quality of the communication channel. The reliability of the decision is undistorted code words above, and for reliable synchronization requires the acceptance of a smaller number of code words. With the deterioration of the quality of the communication channel reliability of the received code words is reduced, and for reliable synchronization requires a greater number of matches numbering and timing sequences as part of the code words received with errors.

The maximum number of errors tmaxfound in the code word, and the threshold value of the total reliability γmaxcode words with matching numbering and synchronizing sequences chosen in such a way as to ensure a high probability of frame synchronization, not inferior, at least, the probability of correct reception of error-correcting cascade code without regard to frame synchronization. The optimal choice of these parameters provides a significant increase in the probability of frame synchronization in comparison with the known device.

For example, cascading code, in the morning code which is a binary code BCH (31, 16)and the outer code is a reed - Solomon code (24, 16) over the Galois field GF(28), the probability of establishing frame synchronization in a communication channel with independent errors, the error rate of 0.05 is in the prototype 0,97. At the same time for a rational choice of the parameters of the proposed device: the maximum number of errors detected in the code word tmax=1, the threshold value of the total reliability of the received code words γmax=6 and normalizing factor β=3 the probability of establishing frame synchronization in the proposed device will be at least 0,99. The reliability of the code word is accepted without error according to the formula (1), equal to 3, the reliability of the code words with a single error, according to the same formula, is equal to 2. Therefore, cycle synchronization is established by two accepted without error code words (3+3=6) or three code words, if at least one of the first two taken with a single error (3+2+2>6, 2+3+2>6, 2+2+3>6, 2+2+2=6).

In the present invention, unlike the known device, when determining frame synchronization consider the quality of the communication channel. The quality of the communication channel is estimated the total reliability of the received code words, which in turn is determined by the multiplicity of errors detected in the received code words. Each adopted a code word if the is some number, characterizing the reliability of a code word errors in the code word. Taking into account the values of authenticity receiving code words characterizing the quality of the communication channel, increases immunity frame synchronization.

Achievable technical result of the proposed device adaptive code frame synchronization is to increase the noise immunity.

Device adaptive code frame synchronization, containing a register of the delay, the node detecting the error, the block decoders, a counter, a threshold unit, a clock generator sequence, the output of the modulo two, random access memory (RAM), a block of adders modulo two, the Comparer rooms, a full adder and counter synchronization, and register delays and node error detection combined input and is connected to the information input device, the node error detection is made in the form of two series-connected filters Huffman and syndrome register, and each filter Huffman consists of serially connected register and modulo two, the input of the syndrome register is connected to the output of the second filter Huffman, and the output connected to the input of block decoders, the output of the generator synchronizing sequence is connected to the first input of ipodnova of modulo two, the second input is coupled to the output register delay, and the output is an information output device, the first output of the block decoders connected to the input of the adders modulo two, the other input of which is connected to the output register of the second filter Huffman, the second output of block decoders connected to the enable input of the RAM write, output unit adders modulo two are connected with inputs of block comparisons of rooms, the other input of which is connected with the older bits of the counter, the output of block comparisons of rooms connected with the older bits of the address input of the RAM low-order bits of the address input of which is connected with the younger bits of the counter clock input the counter is connected to the synchronization input of the device, and also to a clock input of the counter synchronization, set the inputs of which are connected to the outputs of unit adders modulo two, the enable input of counter synchronization connected to the output of the threshold unit, the output of the RAM is connected to the input of the full adder, the output of the full adder is connected with the information input RAM output counter synchronization connected with the allow input clock timing sequence and an output of the synchronization device, characterized in that the device entered the adder errors and code Converter, the output of block decoders connected to the input of the adder errors the output of which is connected to the input of the code Converter, the output of which is connected with the second input of the full adder, the output of which is connected to the input of the threshold unit.



 

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