Device for cyclic synchronization

FIELD: digital communications, namely, engineering of devices for cyclic synchronization of digital information transfer systems with temporal compression.

SUBSTANCE: known device contains random-access memory device, adjustment and diagnostics device, phasing device and generator equipment. Cyclic evenness determining device is introduced to known device. Therefore, cyclic synchronization device provides cyclic synchronization of different digital transmissions, wherein synchronous combination is absent, while on positions at the end of cycle signals are transferred, filling sum of signals of appropriate digital transmission up to evenness.

EFFECT: expanded functional capabilities of device for cyclic synchronization.

2 cl, 3 dwg

 

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal.

The known device for frame synchronization are sync synchronously transmitted at certain positions of the loop digital transmission.

However, there are digital transmission in which to control the quality and health of the tract of acceptance looping, which contains a portion of the bits of one of the standard digital transmission, to which is added n check bits, which are transmitted signals, complementary sum signals of standard digital transmission up to parity, where n is the number depending on the type of modulation. For example, for the modulation type FM-4, in which one clock signal corresponds to two information, the number n is equal to two.

A device for frame synchronization [1], comprising a memory device, the device configuration and diagnostics, the storage device criteria input in synchronism, the storage device criteria exit synchronism, the decoder synchronously, environment unit, generating equipment, inputs and outputs of the devices that are connected in a certain way.

The disadvantages of this device are the following:

- inability to carry out qi is gross synchronization (in the absence of the positions of synchronously) by checking signals, transmitted in a cycle of even parity;

- the impossibility of synchronization in digital transmission with views of the phase modulation of the FM-4, FM-8 and various types of quadrature-amplitude modulation.

The closest to the technical nature of the claimed invention is selected as a prototype device for frame synchronization [2], containing the decoder of synchronously, device configuration and diagnostics, power generating equipment, environment unit, storage devices, prescrotal signals, a counter, a decoder, the inputs and outputs of the devices that are connected in a certain way.

The specified device allows cyclic synchronization of a large class of digital gear synchronously transmitted in each cycle.

The disadvantage of this device is the inability to carry out cyclic synchronization of digital transmission, in which there is no singlecompany, and for quality control and health tract of acceptance looping, which contains a portion of the bits of digital data, to which are added n check bits, which are transmitted signals, complementary sum signals for digital transmission up to parity.

An object of the invention is the extension of functionality by providing one device frame sync is anizatio a variety of digital transmission, lacking singlecompany, and the positions at the end of the cycle of the transmitted signals, the complementary sum signals corresponding digital data to the parity.

This task is achieved in that in a device for frame synchronization, containing random access memory (RAM)device configuration and diagnostics (UND), generating equipment (TH), environment unit (FU), and clock input devices for frame synchronization connected with the respective input, the address outputs of which are connected to corresponding inputs of RAM and are address outputs of the device for frame synchronization, the output of the read record outputs and output device selection configuration and diagnostics are connected to corresponding inputs of RAM, input/output end of the loop which is connected with the corresponding input, input/output UND and an output end of the cycle the device for frame synchronization, outputs cycles settings and options are in zero UND connected to respective inputs, the output of the zero state FU is connected with the corresponding input, and the output of the availability of synchronization FU is the corresponding output device for frame synchronization, information inputs/outputs, input mode selection, new address, set to zero, write, read, set the RAM or the reg is tra UND are the corresponding inputs of the device for frame synchronization, input mode selection TH connected with the respective input device for frame synchronization according to the invention introduced the determinant of the cyclic parity (OCC), the input end of the loop which is connected with the corresponding output of RAM, control inputs with corresponding outputs of UND, clock and information inputs to the corresponding inputs of the device for frame synchronization, the output of the determining parity with the respective input FU, the output of the temporary dispenser OCC connected to the corresponding inputs FU and GUO.

OCC contains one to ten triggers, the group of items, modulo two, the item, AND IS NOT, first and second elements And the element OR the first and second inverters, the input end of the cycle OCC connected with the allow of the entrance of the seventh trigger, with the first input element AND-NOT and information input of the first trigger, the output of which is connected to the information input of the second trigger, the output of which is connected to the information input of the third trigger and clock input of the ninth trigger its output connected to the input of the second inverter, the output of which is connected with the information input tenth the trigger output of the tenth trigger is output by determining the parity OCC, the output of the third trigger is connected to the information input of the fourth three of the Hera and the second input element OR first input connected to the output of the sixth trigger, and the output from a clock input of the tenth trigger, the output of the fourth flip-flop connected to the information input of the fifth trigger, with the input set to zero the ninth trigger and the second input of the second element And whose output is the output of the temporary dispenser OCC, information inputs And1... , Andnand control inputs 1,...,n OCC connected respectively with the first and second inputs of the group of elements And whose output and the output of the eighth flip-flop connected to the corresponding inputs of the modulo two, the output of which is connected to the second input of the first element And whose output is connected to the information input of the eighth trigger, the output of the seventh trigger connected to the first input of the second element And the input of the first inverter and a second input element AND whose output is connected to the first input of the first element And the output of the first inverter is connected to the information input of the seventh trigger, the output of the fifth trigger connected with the information input of the sixth trigger clock input and clock inputs of the first, second, third, fourth, fifth, seventh and eighth triggers are a clock input OCC, the eighth output of the trigger is connected to the information input of the ninth trigger.

The novelty of technical solutions Zack is udaetsya in use in the claimed device identifier cyclic parity.

Thus, the invention conforms to the criterion "novelty".

Analysis of the known technical solutions in the study and related fields allows to conclude that the introduced functional units known. However, their introduction into the device for frame synchronization with the above links gives this unit the new properties. Introduced functional units interact in such a way that allow you to extend its functionality, providing one device synchronization of different digital transmission of information, in which there is no singlecompany, and the positions at the end of the cycle of the transmitted signals, the complementary sum signals corresponding digital data to the parity.

Thus, the invention meets the criterion of "inventive step", as it is for the expert is not obvious from the prior art.

The invention can be used in digital transmission systems with a temporary seal of digital streams.

Thus, the invention meets the criterion of "industrial applicability".

Figure 1 presents the structural electrical diagram of the device for frame synchronization, figure 2 - schematic of the determinant of the cyclic parity, figure 3 - schematic diagram of the device configuration and diagnostics the ticks.

Device for frame synchronization (figure 1) contains random access memory (RAM) 1, device configuration and diagnostics (UND) 2, environment unit (FU) 3, generating equipment (TH) 4, the determinant of the cyclic parity (OCC) 5, and a clock input (input T) devices for frame synchronization (CA) connected with the respective input TH 4, the address outputs (outputs 0,...,N) which are connected to corresponding inputs of RAM 1 and are address outputs of the device for the CA, the output read (output OE), the recording output (output WE) and output selection (output CE) UND 2 connected to respective inputs of the RAM 1, the input/output end of the cycle (input/output CC) which is connected with the respective input TH 4, input/output AND 2 and is the output end of the cycle the device for the CA, the outputs of clock cycles settings (output T) and setting to zero (output RES) UND 2 are connected to corresponding inputs of the FIRST 4, the zero output state (output DS "0") FU 3 is connected with the corresponding input is ON 4, and the output the presence of synchronization (exit f) FU 3 is the corresponding output device for the CA information inputs/outputs (inputs/outputs 1,...,N), the input mode selection (input DIR), new address (input), set to zero (input RES), write (log CE), read (input OE), set the RAM or register (input RAM/RG) UND 2 are the corresponding inputs of the device for the CA, the stroke mode selection (input DIR) TH 4 connected with the respective input devices for CA, the input end of the cycle (input CC) ACC 5 is connected with the corresponding output of RAM 1, the control inputs (inputs 1,...,n) with the corresponding outputs UND 2, clock (input T) and informational inputs (inputs And1..., Andn) - with the corresponding inputs of the device for the CA, the output of the determining parity (output H) with the respective input FU 3, the output of the temporary dispenser (yield BP) OCC 5 is connected to the corresponding inputs FU 3 and 4.

OCC (figure 2) contains one to ten triggers 6,...,15, the group of items 16, modulo two 17, item AND NOT 18, the first and second elements 19, 20, OR element 21, the first and second inverters 22, 23, and the input end of the cycle (input CC) OCC connected with the allow logon (logon EU) seventh trigger 12, with the first input element AND-NOT 18 and data input (D input) of the first trigger 6, the output of which is connected to the information input of the second trigger 7, the output of which is connected to the information input of the third trigger 8 and a clock input (entrance To) the ninth of the trigger 14, its output connected to the input of the second inverter 23, the output of which is connected with the information input tenth of the trigger 15, the output of the tenth trigger 15 is the output of the determining parity (output H) OCC, the output of the third trigger 8 is connected with the information input of the fourth flip-flop 9 and the second input cell battery (included) is one OR 21, first input connected to the output of the sixth trigger 11, and the output from a clock input tenth of the trigger 15, the output of the fourth flip-flop 9 is connected to the information input of the fifth trigger 10, with the input set to zero (log R) ninth trigger 14 and the second input of the second element 20 whose output is the output of the temporary dispenser (yield BP) OCC, information inputs And1..., Andnand control inputs 1,...,n OCC connected respectively with the first and second inputs of the group of elements And 16, the outputs of which and the eighth output of the trigger 13 is connected to the corresponding inputs of the modulo two 17 whose output is connected to the second input of the first element And 19, the output of which is connected to the information input of the eighth trigger 13, the output of the seventh trigger 12 is connected to a first input of the second element 20, the input of the first inverter 22 and the second input element AND-NOT 18, the output of which is connected to the first input of the first element And 19, the output of the first inverter 22 connected to the information input of the seventh trigger 12, the output of the fifth trigger 10 is connected to the information input of the sixth trigger 11, a clock input and clock inputs of the first 6, second 7, 8 third, fourth, 9, 10 fifth, seventh 12 and 13 eighth triggers are a clock input (input T) OCC, the eighth output of the trigger 13 is connected with the information the first input of the ninth trigger 14.

UND (figure 3) contains the inverters 24,...,31, elements, And 32,...,42, items, OR 43, 44, a storage device 45, controlled gates 46-1,...,46-N, 47, 48, unmanaged valves 49-1,...,49-N, 50, and input DIR UND connected to the second inputs of the elements OR 43, 44 and the input of the inverter 24, the output of which is connected to the second inputs of elements And 32,...,37, 41, and the first input of the OR element 43 is connected to the output element And 35, and the output from the first input element And 39, 40, 41, to the input of inverter 29, with the input of the inverter 28, the output of which is output read (output OE) UND, log ON AND connected to the first input element And 32 whose output is the output cycle setting (output T) UND, the input set to zero (input RES) UND connected to the first input element And 33 whose output is the output setup to zero (output RES) UND, entrance WE UND connected to the first input element And 34, the output of which is connected to the input of the inverter 27, and connected to the first input element And 38, the output of which is connected to clock inputs (inputs) triggers the storage device 45, the output of inverter 27 is a recording output (output WE) UND, input OE UND connected to the first input element And 35, the input RAM/RG UND connected to the input of the inverter 25 and the first input element And 37, the output of which is connected with the second inputs of the elements 40, 42 and the first input of the OR element 44, the first input element And 42 seediness output inverter 29, and the output with the control input of the control valve 47, the output of the inverter 25 is connected to the first input element And 36, the output of which is connected with the second inputs of the And elements 38, 39 and enable inputs (inputs EC) triggers the storage device 45, the outputs of the controllable valves which are connected with the corresponding inputs of the controllable valves 46-1,...,46-N, the control inputs of which are connected together and are connected with the output element And 41, the output of the OR element 44 is connected to the input of the inverter 26, the output of which is output select (output CE) UND, the output element And 39 is connected to the input of the inverter 31, and its output connected to control inputs of the controllable valves of the storage device 45, the output element 40 is connected to the input of the inverter 30, the output of which is connected with the control input of the control valve 48, the output of which is connected to the input of the control gate 46-1, outputs unmanaged valves 49-1,...,49-N are connected to the appropriate information inputs (inputs D) triggers the storage device 45, the input of the control valve 47 is connected to the output unmanaged valve 49-1, the input of the control valve 48 is connected to the output unmanaged valve 50, information inputs/outputs (inputs/outputs 1,...,N) UND connected respectively to the outputs of the controllable valves 46-1,...,46-N and inputs unmanaged valves 49-1,...49-N, entrance/exit CC UND coupled to the output of the controlled valve 47 and the entrance unmanaged valve 50, control outputs (outputs 1,...,n) of the storage device 45 are the corresponding outputs of UND.

Device for frame synchronization works as follows.

Device for frame synchronization (CA) has two modes of operation. The first mode of operation and diagnosis, the second mode of operation. In the first mode, the inputs UND 2 receives signals from the controller working in conjunction with the personal electronic computing machine (PC). Mode settings and diagnostics allowed the signal Log."0", which is fed to the input mode selection (input DIR) CA and next to the appropriate input UND 2.

In UND 2 signal from the output of the inverter 24 may be activated elements And 32,...,37, 41. Configuring RAM 1 is permitted by the signal Log."1 coming from the input RAM/RG devices for the CA via a corresponding input UND 2 at the first input element And 37, and the signal Log."0", coming through an inverter 25 to the first input element And 36, you can customize the storage device 45. When configuring RAM 1 device for the CA, and the storage device 45 UND 2 are controlled gates 46-1,...,46-N, 48, and managed the gates of the storage device 45 UND 2 are closed by signals on their control inputs and a controlled valve 47 is of Tcrit. Thus the outputs of the closed controllable valves are in the third state. When setting up the alarm Log."0" from the SECOND input device for the CA is supplied to the corresponding input UND 2 and then through the element And 35, item, OR 43, the inverter 28 and the output of the TH UND 2 - input OE RAM 1 device for CA, setting the RAM 1 in the recording mode.

Before you configure the RAM 1 to the input RES of the device for the CA receives a pulse signal of positive polarity. This signal, acting through the appropriate entrance UND 2, the And gate 33 and the corresponding output UND 2, to the input of RES TH 4, sets the loop counter is the latest in a zero state.

When the RAM configuration 1 configuration data input/output 1 device for the CA through the corresponding input/output 1 UND 2 are received respectively at the input unmanaged valve 49-1. Output unmanaged valve 49-1 these settings are sent to the input of an open controlled valve 47, and then output through the input/output CC UND 2 - the entry/exit CC RAM 1.

After that, the signal Log."1"received from input devices WE CA through the corresponding input UND 2, the And gate 34, the inverter 27 and the output WE UND 2 input WE of the RAM 1, the last at address zero recorded data settings.

Then the signal Log."1"received from input devices to the CA via a corresponding input UND 2, the And gate 32 and the output VT UND 2 input T IS ABOUT 4, the loop counter is the last changes its state by one. Next, the write data at the new address custom RAM 1 is the same as described earlier.

After setting the RAM 1, to determine whether it is correct, the setting signal in the zero state, piped RES TH 4, as described earlier, the loop counter is the last set to the zero state. Then to the input of the read SECOND device to CA and then to the appropriate input UND 2 signal Log."1". The signal received from the output element And 41 on the control inputs of controllable valves 46-1,...,46-N, opens the latter. Also offers controlled valve 48 with the signal received at its control input from the output of the inverter 30. Managed the valve 47 is closed by the signal received at its control input from the output element And 42. The controlled valves of the storage device 45 remain closed. The signal read from output OE UND 2 is supplied to the SECOND input of the RAM 1. The signals from input/output CC RAM 1 through the input/output CC UND 2, unmanaged valve 50 opened operated valves 48 and 46-1 is fed to the input/output 1 & 2 and then through the corresponding input/output device for the CA - in the controller PC to compare them with the original signals. Further according to the signal, as described earlier, a change of address RAM 1 and sityva is their data. The result of the determine the correct configuration of the RAM 1 is displayed on the display PC.

Configuring the storage device 45 UND 2 permitted signal Log."0", coming, as mentioned previously, the input RAM/RG UND 2. When this signal from the output of the inverter 25 through the OR element 36 may be permitted items And 38, 39 and triggers the storage device 45. The work of controllable valves of the storage device 45 is prohibited by the signal coming from the output of the inverter 31. The work of controllable valves 46-1,...,46-N prohibited by the signal from the output element And 41. The work of controllable valves 47, 48 are prohibited signals respectively from the output element And 42 and the inverter 30.

These settings with inputs 1,...,N devices for CA go through the appropriate inputs AND 2 and through unmanaged valves 49-1,...,49-N for informational inputs triggers the storage device 45. Further according to the recording signal received from the input WE UND 2 through the elements And 34, 38 on the clock input triggers the storage device 45, last remember these settings.

To verify the configuration of the storage device 45 to the input of TH UND 2 signal read through the items AND 35, OR 43, AND 39 and inverter 31 opens the controlled valves of the storage device 45, and the output signal from the element And 41 open controlled gates 46-1,...,46-N. the Control is controlled valves 47 and 48 are closed.

Data outputs controllable valves of the storage device 45 are received at the respective inputs of the controllable valves 46-1,...,46-N. Further work is also carried out as described earlier.

In configuration mode and diagnostics (check correct settings) on the clock input of the counter cycle TH 4 receives the output signal of the HS UND 2, and in mode - output T device for the CA.

The transfer device for the CA mode is performed by the signal Log."1", arriving at its input DIR. When this signal Log."0", coming from the output of the CE UND 2 input CE RAM 1, allowed the use of the latter, and the signal Log."0 and Log."1", coming respectively from outputs of the first and WE UND 2 inputs OE and WE RAM 1, the latter is set in the read mode.

The operation of the device for the CA as follows. The address inputs of RAM 1 receives signals from the respective outputs of the FIRST 4, last address output CC RAM 1 is the signal of the end of the cycle, which, by acting on the appropriate input TH 4, provides synchronous setting to zero of the counter cycle TH 4 when you receive a positive front of the clock pulse following the occurrence of signal CC. The signal CC from the output of RAM 1, the signals from the control output 1,...,n UND 2, information and clock signals respectively with inputs And1..., Andnand Tons of devices is for the CA act to corresponding inputs of the determinant of the cyclic parity (OCC) 5. Signals to control output 1,...,n UND 2 specify the type of modulation, i.e. the number of information inputs (subchannels) for one clock input. For example, if the modulation type FM-2 number of subchannels is equal to one. In this case, the control input 1 OCC 5 signal Log."1", and the other control inputs signal Log."0". When the modulation type FM-4 the number of subchannels is equal to two. In this case, control inputs 1 and 2 OCC 5 signal Log."1", and the other control inputs signal Log."0". OCC 5 checks the digital signals flow in the loop on parity. Even parity is on all subchannels. If parity output H OCC 5 is formed of a positive response (signal Log."1"), and in the absence of parity - negative response (signal Log."0"). The output signal H OCC 5 is supplied to the corresponding input FU 3. The output signal from BP OCC 5 is supplied to corresponding inputs of FU 3 and 4.

Before the first positive response to the input H FU 3, the latter is in the zero state, and the signal Log."1"coming from the zero output state (output DS "0") FU 3 on the appropriate input TH 4, allowed the use of his remover tact. Remove tick in TH 4 takes place after receiving at its input the BP signal from the corresponding output OCC 5. Remove tick changes the phase of the counter cycle is About 4 relative to the phase of the cycle digital transmission.

In the described mode, the device for the CA works up until the output H OCC 5 is formed a positive response. After receiving the inputs H and BP FU 3 signal a positive response and the output signal of the temporary dispenser OCC reversible counter FU 3 is installed in the positive mode account and increases its state unit. When this signal Log."0", formed on DS "0" output FU 3 prohibits the operation of the remover tact TH 4. Thus, in the presence of positive signal response on input H FU 3 reversible counter recent increases your status on the unit and in the absence of a positive response decreases by one. When the difference in the number of signals of positive and negative feedback reaches specified in FU 3 values, the device for the CA enters the mode of synchronism, as evidenced by the signal Log."1" at the output of the availability of synchronization (exit f) FU 3. In this mode, the device for the CA is as long as the difference in the number of signals of negative and positive feedback on input H FU 3 reaches the last value. When this FU 3 is set in the zero state, and a device for the CA enters the search mode matching, as described earlier.

The determinant of the cyclic parity (figure 2) works as follows. To determine C clovey parity used two cycles of the digital transmission. The cycle number is determined by the trigger 12 and the inverter 22 connected in a certain way and representing the divider by two. The work of the divider by two is permitted by the signal coming from the input end of the cycle (input CC) ACC 5 input EU of the trigger 12.

Triggers 6, 7, 8, 9, 10, 11 OCC 5 connected in series with each other, represent a temporary allocator, the outputs of which are formed spaced in time signals when receiving information input trigger 6 temporary allocator signal input CC OCC 5.

Information signals from the inputs And1..., Andnand control signals from inputs 1,...,n OCC 5 are received respectively in the first and second inputs of the group of elements And 16. Depending on the type of modulation permitted and prohibited the respective elements And groups of elements And 16. Outputs of group elements And 16 signals arrive at the inputs of the modulo two 17. The signals Log."0", outputs of prohibited items And groups of items And 16 to the inputs of the modulo two 17, do not affect the operation of the latter. To the corresponding input of the modulo two 17 receives the output signal of the trigger 13, which is memorized by the summation of the signals at the previous time step. The output signal from the modulo two 17 through the element And 19 postopen information input trigger 13 and on the leading edge of the next clock signal is memorized in the past. When the divide-by-two is in the first state, the signal Log."0" at the output of the trigger 12 of the divider flowing through the element AND IS NOT 18 at the first input element And 19, may be activated last. The Signal Log."0" at the output of the trigger 13 indicates the presence of a cyclic parity, and the signal Log."1" - in the absence of cyclic parity. The output signal of the trigger 13 is supplied to the information input of the trigger 14, and a signal from the trigger output 7 of the provisional distributor to the clock input of the trigger 14, is remembered in the past. The output signal of the trigger 14 through the inverter 23 is supplied to the information input of the trigger 15 and the signal coming from the trigger output 8 of the provisional dispenser through the second input of the OR element 21 to the clock input of the trigger 15, is remembered in the past. The Signal Log."1" at the output of the trigger 15 indicates the presence of a cyclic parity, and the signal Log."0" - in the absence of cyclic parity. After storing the signal in the trigger 15, the signal coming from the trigger output 9 of the provisional dispenser on the input set to zero trigger 14, the latter is set in the zero state.

In the first state of the divide-by-two signal Log."0", coming from the trigger output 12 to the first input element And 20 are forbidden to work and last C is prohibited the passage of the output signal of the trigger 9 temporary dispenser at the entrance BP OCC 5 and further to the input of the FIRST 4. Thus TH 4 doesn't remove the stroke.

Upon receipt of the next signal input CC OCC 5 enable input of the trigger 12 of the divider by two, the last on the leading edge of the next clock signal is set at the second state. When this signal Log."1"coming from the trigger output 12 to the first input element And 20, may be permitted the latter, and, therefore, allowed the passage of the output signal of the trigger 9 temporary dispenser at the entrance BP OCC 5.

By the time the signal at the output of the trigger 11 temporary dispenser on the information input trigger 15 receives the signal Log."1", and on the leading edge of the signal coming from the trigger 11 through the element OR 21 on the clock input of the trigger 15, the latter is set in one state.

When the divide-by-two is in a single state, may be permitted element AND-NOT 18. In this case, when a signal input of CC at the first input element AND-NOT 18, the output of this element is formed by the signal Log."0", which through the element And 19 is supplied to the information input of the trigger 13, and the last on the leading edge of the next clock signal is set to the zero state. The cutting edge of the same clock signal is set in the zero state of the trigger 12 of the divider by two. The divide-by-two switching the t in the first state.

The present invention allows to extend the functionality by providing one device frame synchronization of different digital transmission, in which there is no singlecompany, and the positions at the end of the cycle of the transmitted signals, the complementary sum signals corresponding digital data to the parity.

Sources of information

1. RF patent №2187210, H 04 L 7/08, 10.08.2002.

2. RF patent №2237374, H 04 L7/08, 27.09.2004.

1. Device for frame synchronization, containing random access memory (RAM)device configuration and diagnostics (UND), generating equipment (TH), environment unit (FU), and clock input devices for frame synchronization connected with the respective input, the address outputs of which are connected to corresponding inputs of RAM and are address outputs of the device for frame synchronization, the output of the reading, recording output and the output of the mode select device configuration and diagnostics are connected to corresponding inputs of RAM, input/output end of the loop which is connected with the corresponding input, input/output UND and is the output end of the cycle the device for frame synchronization, outputs cycles settings and options are in zero UND connected to respective inputs, the output of the zero state FU is connected with the corresponding whodo the TH, the presence of synchronization FU is the corresponding output device for frame synchronization, information inputs/outputs, input mode selection, new address, set to zero, write, read, set the RAM or register UND are the corresponding inputs of the device for frame synchronization, the input mode selection TH connected with the respective input device for frame synchronization, characterized in that the entered identifier cyclic parity (OCC), the input end of the loop which is connected with the corresponding output of RAM, control inputs with corresponding outputs of UND, clock and information inputs to the corresponding inputs of the device for frame synchronization, the output of the determining parity with the respective input FU, the output of the temporary dispenser OCC connected to the corresponding inputs FU and GUO.

2. The device according to claim 1 characterized in that the determinant of the cyclic parity contains one to ten triggers, the group of items, modulo two, the item, AND IS NOT, first and second elements And the element OR the first and second inverters, the input end of the cycle OCC connected with the allow of the entrance of the seventh trigger, with the first input element AND-NOT and information input of the first trigger, the output of which is connected to the information input of the second TRIG the EPA, the output of which is connected to the information input of the third trigger and clock input of the ninth trigger its output connected to the input of the second inverter, the output of which is connected with the information input tenth of a trigger, the output of the tenth trigger is output by determining the parity OCC, the output of the third trigger is connected to the information input of the fourth flip-flop and a second input of the OR element, the first input connected to the output of the sixth trigger, and the output from a clock input of the tenth trigger, the output of the fourth flip-flop connected to the information input of the fifth trigger, with the input set to zero the ninth trigger and the second input of the second element And whose output is the output of the temporary dispenser OCC, information inputs And1..., Andnand control inputs 1,...,n OCC connected respectively with the first and second inputs of the group of elements And whose output and the output of the eighth flip-flop connected to the corresponding inputs of the modulo two, the output of which is connected to the second input of the first element And whose output is connected to the information input of the eighth trigger, the output of the seventh trigger connected to the first input of the second element And the input of the first inverter and a second input element AND whose output is connected to the first input of the first element And output the first inverter is connected to the information input of the seventh trigger the fifth output of the trigger is connected to the information input of the sixth trigger clock input and clock inputs of the first, second, third, fourth, fifth, seventh and eighth triggers are a clock input OCC, the eighth output of the trigger is connected to the information input of the ninth trigger.



 

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FIELD: digital communications;

SUBSTANCE: proposed device is used for frame synchronization of digital time-division multiplex data transmission systems and incorporates provision for synchronizing data transmission class at dispersed sync combination of group signal and for implementing parallel search for synchronism. Device has first, second, and third random-access memories, storage register, decoder, distributor, generator equipment, phasing unit, flip-flop, first and second inverters, adjusting unit, first, second, and third inverters, first, second, third, fourth, and fifth AND gates, first and second OR gates.

EFFECT: enlarged functional capabilities.

1 cl, 2 dwg

FIELD: communications.

SUBSTANCE: device has control circuit, first input of which is connected to output of phase sign decoder, second input is connected to first clock input of device, third input is connected to second clock input of device, circuit OR, connected by its inputs to outputs of controlled system, and output of OR circuit is connected to third block for forming cyclic phasing signal, while the latter is made on basis of same circuit of logic numbers processing and consists of two numbers signals switchboard, arithmetic adder of two numbers, memory device, meant for recording K numbers, on basis of K data words, required for forming of cycle synchronization signal, AND match circuit, decoder, pulse counter, performing function of threshold element.

EFFECT: higher trustworthiness.

1 dwg

FIELD: digital communications.

SUBSTANCE: device has random access memory, adjusting device, synchronous combination decoder, phasing device, generator equipment, three commutators, signals distributor, time analyzer and signals remover.

EFFECT: higher reliability, higher effectiveness, higher interference resistance.

1 cl, 3 dwg

The receiver clock // 2242093
The invention relates to radio engineering

The invention relates to telecommunication and can be used in the receiving device sync cycles of transmission of discrete messages

The invention relates to techniques for digital communication, namely, devices for frame synchronization in digital communication systems with a temporary seal

The invention relates to communication systems

FIELD: digital communications.

SUBSTANCE: device has random access memory, adjusting device, synchronous combination decoder, phasing device, generator equipment, three commutators, signals distributor, time analyzer and signals remover.

EFFECT: higher reliability, higher effectiveness, higher interference resistance.

1 cl, 3 dwg

FIELD: communications.

SUBSTANCE: device has control circuit, first input of which is connected to output of phase sign decoder, second input is connected to first clock input of device, third input is connected to second clock input of device, circuit OR, connected by its inputs to outputs of controlled system, and output of OR circuit is connected to third block for forming cyclic phasing signal, while the latter is made on basis of same circuit of logic numbers processing and consists of two numbers signals switchboard, arithmetic adder of two numbers, memory device, meant for recording K numbers, on basis of K data words, required for forming of cycle synchronization signal, AND match circuit, decoder, pulse counter, performing function of threshold element.

EFFECT: higher trustworthiness.

1 dwg

FIELD: digital communications;

SUBSTANCE: proposed device is used for frame synchronization of digital time-division multiplex data transmission systems and incorporates provision for synchronizing data transmission class at dispersed sync combination of group signal and for implementing parallel search for synchronism. Device has first, second, and third random-access memories, storage register, decoder, distributor, generator equipment, phasing unit, flip-flop, first and second inverters, adjusting unit, first, second, and third inverters, first, second, third, fourth, and fifth AND gates, first and second OR gates.

EFFECT: enlarged functional capabilities.

1 cl, 2 dwg

FIELD: digital data transfer systems for frame synchronization of correcting codes including noise-immune concatenated codes.

SUBSTANCE: proposed device for adaptive code frame synchronization has delay register 1, error detection assembly 2, decoder unit 10, counter 11, threshold unit 21, synchronizing-sequence generator 18, modulo two output adder 12, random-access memory 15, modulo two adder unit 16, number comparison unit 13, full adder 19, synchronization counter 17, error counter 14, and code converter 20. Error detection assembly is set up of two series-connected Huffman filters 3, 4 and syndrome register; each Huffman filter has register 6/7 and modulo two adder 8/9.

EFFECT: enhanced noise immunity.

1 cl, 1 dwg

FIELD: electric communications, possible use in receiving devices for synchronization by cycles of system for transferring discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, forbidding element, first AND element, adder, shift registers block, generator of clock pulses, OR element, cycles counter, counter of distorted synchronization signals, block for selecting allowed number of distorted synchronization signals, block for selecting threshold, block for selecting counting coefficient, counter by exit from synchronization status, and also solving assembly, containing first comparison block, memory block, subtraction block, second comparison block, comparison counter, second AND element, third AND element, second OR element.

EFFECT: increased reliability of operation of device for synchronization by cycles due to excluded possibility of overflow of shift registers block in synchronous operation mode.

1 dwg

FIELD: electric communications engineering, possible use in receiving cycle synchronization devices of systems for transmission of discontinuous messages.

SUBSTANCE: device contains synchronization signal recognition device, adder, block of shift registers, solving block, generator of cyclic impulses, counter of cycles, comparison block, counter of distorted synchronization impulses, counter of total number of synchronization impulses, AND element, counter of clock impulses, trigger, block for selecting maximal weight of response, threshold selection block, second threshold selection block, block for selection of counting coefficient, signal input, clock input and output of device. Synchronization signal recognition device contains shift register, detector of errors in synchronization group, generator of weight of response to synchronization signal. Solving block contains comparison block, memory block, subtraction block, comparison block, comparison counter, second AND element, third AND element, OR element. By means of second element AND, third element AND, and also element OR in synchronous mode, and also in case of synchronism failure, generation of synchronization signal is performed at output of solving block. Restoration of synchronism after failure and phasing of device for new position of cyclic synchronism is performed in case of occurrence of two events simultaneously: determining of new position of cyclic synchronization signal by solving block and detection of failure of cyclic synchronism by means of cycles counter, comparison block, threshold selection block and count coefficient selection block, because during regular repeating at certain information position of cycle of false synchronization group and random distortion of true synchronization group phase of cyclic impulse generator does not alter, thus causing no false synchronism failure.

EFFECT: increased interference resistance of device for cyclic synchronization.

4 dwg

FIELD: digital communications, namely, engineering of devices for cyclic synchronization of digital information transfer systems with temporal compression.

SUBSTANCE: known device contains random-access memory device, adjustment and diagnostics device, phasing device and generator equipment. Cyclic evenness determining device is introduced to known device. Therefore, cyclic synchronization device provides cyclic synchronization of different digital transmissions, wherein synchronous combination is absent, while on positions at the end of cycle signals are transferred, filling sum of signals of appropriate digital transmission up to evenness.

EFFECT: expanded functional capabilities of device for cyclic synchronization.

2 cl, 3 dwg

FIELD: technology for realization of cyclic synchronization of interference-resistant cyclic codes, in particular, cascade codes.

SUBSTANCE: in accordance to method, at transferring side one synchronization series is selected for N code words following one another, check section of code words is added with modulus two to appropriate section of aforementioned synchronization series. At receiving side received input series, consisting of several code words following each other, is divided onto original interference-resistant cyclic codes polynomial, producing a total of interference-resistant cyclic codes syndrome and synchronization series. By subtracting synchronization series from produced total, interference-resistant cyclic codes syndrome is selected. On basis of interference-resistant cyclic codes syndrome combination of errors in interference-resistant cyclic codes is computed and its weight is evaluated. On basis of error combination weight, trustworthiness degrees of code words following each other are computed. If total trustworthiness degree exceeds threshold value, decision about performing code cyclic synchronization of input series is taken.

EFFECT: increased interference resistance of cyclic synchronization.

2 cl

FIELD: data processing in broadband radio communications and radio navigation.

SUBSTANCE: proposed method intended for use where reception of extended-spectrum data signals keyed by simulation-resistant pseudorandom nonlinear derivative sequences is always preceded by synchronization includes concurrent accumulation of periodic mutually correlated function values of signal segments arriving from output of dynamically matched adjustable filters with two standard sampling lines affording generation of random derivative, as well as determination of time step numbers of their mutual shift corresponding to delay synchronism. Then current delay of entire signal being received is found from combination of these time step numbers. Used as dynamically matched adjustable filters in search channels are acousto-electronic convolvers.

EFFECT: reduced time and hardware requirement for searching broadband delay signals characterized in high simulation resistance.

2 cl, 9 dwg

FIELD: electric and radio communications; frame synchronization receiving devices of digital message transmitting and intercepting systems.

SUBSTANCE: proposed method includes sequential search at single-bit shift, identification of concentrated sync groups in group digital stream, and formation of responses when identifying concentration sync groups on tested clock intervals, and measurement of time intervals between sequential moments of responses across concentrated sync group identifier in terms of clock intervals. Primary sample of N ≥ 3 time intervals is accumulated. Secondary samples of time intervals between moments of first, second, through (N + 1)th reference responses, respectively, and arrival moments of all other primary-sample responses are calculated. Maximal common dividers of probable combinations of two or more time intervals are calculated and particular lines (spectrums) of distribution of maximal common dividers whose values exceed lower boundary of region of probable group signal cycle lengths are formed in the framework of secondary time interval samples. Integrated spectrum of maximal common divider values is formed by summing up all particular maximal common divider spectrums. Regular sequence of true integrated sync group responses is detected by fact of coincidence of maximal common dividers in integrated spectrum whose quantity exceeds desired threshold, and coincidence point abscissa of maximal common dividers is assumed as cycle length. True concentrated sync group responses are identified in primary implementation of stream by serial numbers of particular maximal common divider spectrums wherein we see multiple coincidences of maximal common dividers with found cycle length. Clock interval of group-signal next cycles commencement is predicted. Concentrated sync group responses appearing at predicted clock intervals are assumed as frame synchronization pulses. Decision on input in and output from frame synchronization mode is taken by composite "k/m-r" criterion.

EFFECT: enlarged functional capabilities due to affording frame synchronization in absence of a priori data on group-signal cycle length without impairing noise immunity.

1 cl, 9 dwg

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