Digital frequency synthesiser

FIELD: radio engineering.

SUBSTANCE: result is achieved due to introduction to digital frequency synthesiser of buffer amplifier-pulse shaper (31), the first counter-divider (32), the second counter-divider (33), the main counter-divider (34) and additional counter-divider (35).

EFFECT: enlarging functional capabilities of the device due to possibility of formation of high-frequency signals for transmitter-receivers and service signals with various controlled phase shift and with various frequencies.

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The invention relates to electrical engineering and can be used in radio stations as exciter transmitter (send) heterodyne receiver (PFP), as well as for generating signals for devices angular quadrature modulation and self-compensation of amplitude and phase distortions occurring in the paths of formation and processing of radio signals.

Known dvukhkontsevoi digital frequency synthesizer (CSC) with frequency modulation (FM) with the consistent inclusion of the rings, built on the basis of pulse-phase-locked loop (IFPC) with a frequency divider with variable division factor (DPCD) in the feedback circuit of each ring (see patent GR No. 56747, NS 3/09, H03L 7/18 from 10.09.2006).

The first ring IFPC in this CSC narrowband, operates on the same frequency with the FM output signal which is the reference for the second ring.

The second ring IFPC wide-band, dual-channel - it can work either on channel fast switching frequency for a given program using the second (fractional) DPCD, or channel normal operation CSC using the third (integer) DPCD. Output frequency range and spacing of the frequencies on both channels the same. Frequency modulation in each channel is performed by point-to-point scheme with the use of FM signal with the first ring.

The disadvantage of the local device is that it is impossible to obtain high performance when switching from one frequency to another within the range of PFP or send, and when switching ranges and send PFP while maintaining high spectral purity of the output signal and wide-band modulation with minimum distortion.

The closest in technical essence to the present invention is dvukhkontsevoi CSC with frequency modulation (see patent GR No. 63996, NS 3/09, H03L 7/18 from 10.06.2007), which is taken as a prototype.

The block diagram of the device of the prototype is shown in figure 1, where we have introduced the following notation:

1 - reference generator (DG);

2 and 7, the first and the second frequency divider with a fixed division factor (DFCD);

3 and 8, the first and second frequency-phase detector (CPD);

4 and 9, the first and second low pass filters (LPF);

5, 11, 27 - first, second and third driven generators (UG);

6 and 12, the first and the second frequency divider with variable division factor (DPCD);

17, 20 and 26 of the first, third and fifth keys (CL);

24, 25, 28 and 29 of the first, second, third and fourth buffer amplifier (BU);

10 is a source of modulating signal (IMS);

13 - the first controlled attenuator (UA);

30 - adder (SUM);

23 - microcontroller (MC).

The device prototype contains a microcontroller MK 23, connected in series reference generator EXHAUST gas 1, the first choice of the frequency divider with a fixed division ratio of DFCD 2, the first frequency-phase detector CPD 3, the first lowpass filter LPF 4, the first controllable oscillator UG 5 and the first frequency divider with variable division factor DPCD 6, the output of which is connected to a second input of the first CFD 3; connected in series to the second DFCD 7, the second CPD 8, the second low-pass filter 9, the first key CL 17, the second ANGLE 11, the first BU 24 and the second BU 25 whose output is the first output device; the output UG 5 is connected to the input DFCD 7; connected in series with the fifth key CL 26, the third ANGLE 27 third BU 28 and the fourth BU 29 whose output is the second output; connected in series IC 10, the first UA 13 and the third key CL 20, the output of which is connected to the modulating input of the first 5 UG; and connected in series adder SUM 30 and the second DPKG 12. Moreover, the output of the first buffer amplifier BU 24 connected to the first input of the adder SUM of 30, and the output of the third buffer amplifier BU 28, also connected with the second input of the adder SUM 30. Thus the output of the second DPKG 12 is connected with the second input of the second CFD 8. From the first output of the microcontroller MC 23 of the first control bus is connected to the control inputs of the second DFCD 7, the second CPD 8, the second DPKG 12, the first DPCD 6 and the first UA 13. From the second output of the microcontroller MC 23 second control bus is connected to the control inputs pervogo 17, third CL 20, fifth CL 26, the first BU 24, the second BU 25, the third BU 28, the fourth BU 29, UG second 11 and third ANGLE 27. This second low-pass filter 9, in addition, is connected to the input of the fifth key CL 26.

The device prototype works as follows.

In CSC with FM, there are two cascaded ring IFPC. The first ring IFPC narrowband, operates at one fixed frequency and is made on the basis of series-connected first UG 5, the first DPCD 6, the first CFD 3 and the first low-pass filter 4, the output of which is connected with the control input 5 UG. On the reference input of the first CFD 3 comes from the EXHAUST gas 1 through the first DFCD 2 reference pulse signal with a sufficiently high frequency of the comparison, when the narrow bandwidth of the ring allows a significant interference with a frequency comparison of the control signal at input 5 UG. The result can be obtained at its output spectral clean signal, which is the reference for the second ring IFPC. In transfer mode, the first ring is a single point on FM modulating input UG 5, i.e. in this mode, the reference signal for the second ring is frequency-modulated.

The second ring IFPC on the basis of series-connected second DFCD 7, the second CFD 8 and the second low-pass filter 9 and the second DPKG 12, UG second 11 and third UG 27 - a fast, has two plumage is glycaemic output, working alternately. With one output (Output 1) signal for the local oscillator of the receiver with another {Exit 2) - FM signal for the exciter transmitter. The range of output frequencies and even grid spacing of frequencies for them may be different. Output frequency range 27 UG pathogen transfer is determined by the specified requirements for the station, and for the heterodyne receiver of the second YR 11 has a frequency range that is shifted relative to the UG 27 to an intermediate frequency f_GETS=f_Send+f_FC. Because of the use of fractional DPCD with a large fragmentation grid step frequency 11 UG you can choose significantly less than for UG 27 (FTEs). This allows you to more accurately adjust the frequency of the heterodyne receiver based on process deviations the average frequency f_FCquartz filters tract intermediate frequency in PFP and to improve the noise immunity PFP and its performance.

The control signal in the second ring from the output of the second CFD 8 through the second low-pass filter 9 is supplied or after the first key CL 17 on the first control input of the second switched YR 11 or through fifth key CL-26 at the first control input of the third switched UG 27. With the release of the second YR 11 frequency (RF) signal through the switching of the first buffer amplifier BU 24 is supplied to the first input of the adder SUM 30 and simultaneously through switching the second is 25 on "Output 1" of the device. And with the third dial-a UG 27 RF signal through the third switching BU 28 is supplied to the second input of SUM 30 and simultaneously through fourth switching BU 29 goes to "Output 2" device. Output SUM 30 one or the other of the RF signal fed to the input of the second DPKG 12 (DPCD), the output of which is formed a short pulse supplied to the second input of the second CFD 8. At the first input of the second CFD 8 come short of the reference pulses from the output of the second DFCD 7, formed after dividing the RF signal output from UG 5 of the first ring. In comparison of these two streams of pulses in frequency and phase at the output CPD 8 is formed by the control voltage, which is filtered by the second low-pass filter 9 and via the appropriate keys arrives at the first input or the second YR 11 or the third UG 27, adjusting their frequency up to a phase under the reference signal.

The second switching UG 11 and the third switching UG 27 are switched alternately and simultaneously with the corresponding keys on the input (CL 17 or CL 26) and with buffer amplifiers at the outputs (BU 24, 25 BU or BU 28, BU 29) according to control signals received via the second control bus from MK 23. When off the second YR 11, is the third ANGLE 27 and Vice versa. On the first or second input of the SUM 30 receives an RF signal to or from YR 11 or YR 27 and between the outputs of the device polychaets the good isolation "prolazu" RF signals.

Modulating the signal in the FM mode output IC 10 through the first WHA 13 and the third key CL 20 is supplied to the modulating input of the first UG 5, the output of which is FM reference signal is input to the second ring. On the control input of the first UA 13 comes from the microcontroller MC 23 on the first control bus, the corresponding control signal, which changes the gear ratio when changing the output frequency of the second ring. Thereby automatically stabilizes a given level of deviation of the frequency synthesizer in a wide range of selectable frequencies at a certain constant level of the modulating signal from the IC 10.

On the first control bus from MK 23, the control signals into a serial binary code, go to the first DPCD 6, the second DPKG 12, the second CFD 8 and the second DFCD 7 for inclusion in the operating state at a given frequency and mode. The control signals from the MK 23 changing the operation mode of the second CFD 8 current: transient current from the output CPD 8 large, and therefore the bandwidth of the ring IFPC and performance is great; mode synchronism current CFD is small and the bandwidth of the ring is reduced to provide the desired sideband suppression in the spectrum of the output signal CSC.

The first control bus from MK 23 is a standard three-wire interface, depo three wires coming into a serial binary code pulse signals: 1) clock pulses; 2) information signal; 3) the momentum resolution record of information transmitted in one of the blocks of the synthesizer.

A disadvantage of the known device the prototype is as follows.

Modern radios are usually in addition to the RF signals required for PFP and send, are formed of different service signals to create an information sequence, ringtones and exchange, to obtain quadrature channels modulation, for self-compensation of amplitude and phase distortions occurring in the paths of formation and processing of radio signals, etc. These signals are generated from different sources of fluctuations, often not coherent with each other, with different stability. As a result of simultaneous operation of various incoherent sources of vibrations between them can produce beats that are interference in the work of the station.

At the same time, the functionality of the system CSC with MK can be much wider. You can, for example, to synthesize using system CSC with MK variety of auxiliary oscillations, greatly enhancing the efficiency of modern radio. All variations from CSC are formed from a single highly stable source that excludes the possibility of beating between them.

The device prototype generated RF signals for PFP and send.

T is thus, the drawback of the prototype is its limited functionality.

To eliminate this disadvantage in a digital frequency synthesizer containing serially connected reference oscillator, a first frequency divider with a fixed division ratio of the first frequency-phase detector, the first lowpass filter, the first controllable oscillator and the first frequency divider with a variable division ratio, the output of which is connected to a second input of the first frequency-phase detector, connected in series, the second frequency divider with a fixed division ratio of second frequency-phase detector, a second lowpass filter, the first key, the second controllable oscillator, the first buffer amplifier, the output of which is connected to the first input of the adder and the input of the second the buffer amplifier whose output is the first output and the second frequency divider with a variable division ratio, a signal input connected to the output of the adder, and the output connected to the second input of the second frequency-phase detector; a signal input of the second frequency divider with a fixed division factor is connected with the output of the first controlled oscillator; connected in series with the fifth key, the third controllable oscillator and the third is ferny amplifier, thus the output of the third buffer amplifier is connected to the second input of the adder and the input of the fourth buffer amplifier whose output is the second output device and the input of the fifth key is connected with the output of the second lowpass filter; the microcontroller, the first control bus which is connected to the control inputs of the first and second frequency divider with a variable division ratio of second frequency-phase detector, the second frequency divider with a fixed division ratio; a second control bus of the microcontroller are connected to control inputs of the first and fifth keys, second and third driven generators, the first, second, third and fourth buffer amplifier, entered serially connected buffer amplifier-shaper pulses, a first counter-divider and the second counter-divider, the output of which is a third output; connected in series additional counter-divider and the main counter-divider, the output of which is the fourth output, and the output of buffer amplifier-shaper pulses, in addition, connected to the signal input of the counter-divider, and the output of the first counter-divider, in addition, is connected with the second (signal) input main counter-divider; with these the m input of the buffer amplifier is a pulse shaper connected to the output the first controlled oscillator, and control inputs of the first, second, primary and secondary counters-dividers is connected to the first control bus of the microcontroller.

The block diagram of the proposed device is presented in figure 2, where we have introduced the following notation:

1 - reference generator (DG);

2 and 7, the first and the second frequency divider with a fixed division factor (DFCD);

3 and 8, the first and second frequency-phase detector (CPD);

4 and 9, the first and second low pass filters (LPF);

5, 11, 27 - first, second and third driven generators (UG);

6 and 12, the first and the second frequency divider with variable division factor (DPCD);

17 and 26, the first and fifth keys (CL);

24, 25, 28 and 29 of the first, second, third and fourth buffer amplifier (BU);

30 - adder (SUM);

23 - microcontroller (MC);

31 is a buffer amplifier-shaper pulses (BUF);

32 - first counter-divider (PDS);

33 - second counter-divider (IRR);

34 is the primary counter-divider (MDA);

35 - additional counter-divider (DSD).

The proposed device comprises a microcontroller MK 23, connected in series reference generator EXHAUST gas 1, the first frequency divider with a fixed division ratio of DFCD 2, the first frequency-phase detector CPD 3, the first lowpass filter LPF 4, the first controllable oscillator UG 5 and the first frequency divider is variable division factor DPCD 6, the output of which is connected to a second input of the first CFD 3. The yield of 5 UG also connected to the inputs of the second DFCD 7 and PUFF 31, the output of which is connected to the signal inputs of the ADI PDS 35 and 32, the output of which is connected to the signal input IRR 33, the output of which is the "Outlet 3" device. In addition, the output PDS 32 is connected to the first signal input of the OSD 34 whose output is "4" devices. The second input (reset input and initial setup) the OSD 34 is connected to the output of DSD 35.

The proposed device comprises a serially connected second DFCD 7, the second CPD 8, the second low-pass filter 9, the first key CL 17, the second ANGLE 11, the first BU 24 and the second BU 25, the output of which is the "Output 1" device connected in series with the fifth key CL 26, the third UG 27, the third BU 28 and the fourth BU 29, the output of which is the "Output 2" of the device; and also connected in series adder SUM 30 and the second DPKG 12. In addition, the output of the first buffer amplifier BU 24 connected to the first input of the adder SUM of 30, and the output of the third buffer amplifier BU 28 is connected with the second input of the adder SUM 30. Thus the output of the second DPKG 12 is connected with the second input of the second CFD 8. From the first output of the microcontroller MC 23 of the first control bus is connected to the control inputs of the second DFCD 7, the second CPD 8, the second DPKG 12, the first DPCD 6, PDS 32, IRR 33, the OSD 34 and D Is D 35. From the second output MK 23 second control bus is connected to the control inputs of the first CL 17, fifth CL 26, the first BU 24, the second BU 25, the third BU 28, the fourth BU 29, UG second 11 and third ANGLE 27. Moreover, the output of the second low-pass filter 9 is connected, furthermore, to the input of the fifth key CL 26.

The proposed device operates as follows.

In CSC with FM, there are two cascaded ring IFPC. The first ring IFPC narrowband, operates at one fixed frequency and is made on the basis of series-connected first UG 5, the first DPCD 6, the first CFD 3 and the first low-pass filter 4, the output of which is connected with the control input 5 UG. On the reference input of the first CFD 3 comes from the EXHAUST gas 1 through the first DFCD 2 reference pulse signal with a sufficiently high frequency of the comparison, when the narrow bandwidth of the ring allows a significant interference with a frequency comparison of the control signal UG 5. This allows to obtain at its output spectral clean signal, which is the reference for the second ring IFPC and for forming auxiliary and utility signals.

In the proposed device output 5 UG formed one RF signal with a highly stable frequency, which is fed to the input DFCD 7 and input to BUF 31, the output of which is formed a pulse signal shape close to a square wave (see the temporal charts figa). This output BUF 31 is fed to the signal inputs of the first counter-divider PDS 32 and counter-divider RS 35. Output PDS 32 pulse sequence (see figb) is fed to the signal inputs of the second counter-divider IRR 33 and the main counter-divider NIDS 34. Output IRR 33 is formed in one of the two branches of the managed digital phase shifter and the signal without phase shift (see timing diagrams on FIGU enters "Exit 3" device. To exit the OSD 34 receives the signal of the second branch managed Phaser on "Exit 4" device with a controlled discrete phase shift relative to the signal "Output 3" (see timing diagrams on Figg-l). Blocks PDS 32, IRR 33, the OSD 34 and RS 35 form a digitally controlled phase shifter (PV) with almost any resolution phase change signal of one branch of PV relative to another and high stability set the value of the phase. The signal "Output 3" (without phase shift) can also be used for forming different service signals. The operation of the PV is from the MK 23 on the first control bus, the output of which corresponding signals are sent to the control inputs of PDS 32, IRR 33, the OSD 34 and RS 35. Discrete job phases fits well into the structure of the commands MK 23. In the beginning both of the counter-divider In The D 33 and the OSD 34 starting account at the same time (synchronously) on command from the MK 23, and then in the OSD 34 is specified phase shift.

The characteristic of PV in the proposed device consists of the following.

On signal input DSD 35 receives the pulsed RF signal (see figa), and the control input RS 35 on the first control bus is supplied from the output MK 23, the control signal that sets the number of input RF pulses (periods)that DSD 35 must consider and on which it is necessary to shift the phase of the signal at the output of the OSD 34. At the end of the account on the output DSD 35, a signal is generated initial setup, which is supplied to the second input of the OSD 34, resets it to the initial state, from which begins the account, and thereby determines the specified phase shift PV "Output 4" on "Outlet 3" (see Figg-l) with high precision and stability.

For example, let the frequency at the output of the first 5 UG f_P=100 MHz, the same frequency and at the exit BOOTH 31, the division ratio (account) in the PDS 32 can be K=2 and more (see figb), since its division ratio controlled from MK 23 (as well as the ratios IRR 33 and the OSD 34). When K=2 the output frequency of PDS 32 is 100 MHz : 2=50 MHz. Figure 3 b shows the timing diagram of the pulses at the output IRR 33 ("Output 3") when K=8. The frequency of the pulses at the output IRR 33 50 MHz : 8=6.25 MHz. The same division ratio and the same frequency output ("Output 4") has the OSD 34, only here mo is but to shift the initial phase relative to the phase at the Output 3 control signal from the MK 23.

If you want to shift the phase of the pulses at the Output 4 on 4 basic RF period (see figa), DSD 35 should count 4 input pulse and to generate a reset signal and setting output to the second input of the OSD 34. Since then, the OSD 34 considers input pulses with a shift of 4 elementary period (see Figg) regarding the "Exit 3" (without the phase shift on figv). Moreover, the reset signal and the installation runs with output DSD 35 once from MK 23 of the control input RS 35 set value of the phase shift.

The frequency of the pulses at the outputs IRR 33 and the OSD 34 can be substantially reduced by signals from the MK 23. This also significantly decreases one discrete phase shift.

Figure 3, W separately shown in the example installation option on the outputs PV ("Exit 3 and Exit 4") quadrature signals (with a shift of 90°).

Thus, the choice of operating frequencies and discrete values of the phase shift digital PV may be the most diverse and installed from the MK 23.

The second ring IFPC, as in the prototype, on the basis of series-connected second DFCD 7, the second CFD 8 and the second low-pass filter 9 and the second DPKG 12, UG second 11 and third UG 27 - a fast, has two switchable output, working alternately. With one output (Output 1) signal for the local oscillator of the receiver, with the other (Exit 2) - FM signal is La exciter transmitter. The range of output frequencies and even grid spacing of frequencies for them may be different. Output frequency range 27 UG pathogen transfer is determined by the specified requirements for the station, and for the heterodyne receiver of the second YR 11 has a frequency range that is shifted relative to the UG 27 to an intermediate frequency f_GETS=f_Send+f_FCand because of the use of fractional DPCD with a large fragmentation grid step frequency 11 UG you can choose significantly less than for UG 27 (FTEs). This allows you to more accurately adjust the frequency of the heterodyne receiver based on process deviations the average frequency f_FCquartz filters tract intermediate frequency in PFP and to improve the noise immunity PFP and its performance.

The control signal in the second ring from the output of the second CFD 8 through the second low-pass filter 9 is supplied or after the first key CL 17 on the first control input of the second switched UG 11, or through the fifth key CL-26 at the first control input of the third switched UG 27. With the release of the second YR 11 frequency (RF) signal through the switching of the first buffer amplifier BU 24 is supplied to the first input of the adder SUM 30 and simultaneously through the second switching BU 25 for the first "Output 1" of the device. And with the third dial-a UG 27 RF signal through the third switching BU 28 is supplied to the second input of SUM 30 is simultaneously via dial-up fourth BU 29 is supplied to the second output "Output 2".

Output SUM 30 one or the other of the RF signal fed to the input of the second DPKG 12 (DPCD), the output of which is formed a short pulse supplied to the second input of the second CFD 8. At the first input of the second CFD 8 come short of the reference pulses from the output of the second DFCD 7, formed after dividing the RF signal output from UG 5 of the first ring. In comparison of these two streams of pulses in frequency and phase at the output CPD 8 is formed by the control voltage, which is filtered by the second low-pass filter 9 and via the appropriate keys arrives at the first input or the second YR 11 or the third UG 27, adjusting their frequency up to a phase under the reference signal.

The second switching YR 11 or the third switching UG 27 are switched alternately and simultaneously with the corresponding keys on the input (CL 17 or CL 26) and with buffer amplifiers at the outputs (BU 24, 25 BU or BU 28, BU 29) according to control signals received via the second control bus from MK 23: when off the second YR 11, is the third ANGLE 27 and Vice versa. On the first or second input of the SUM 30 receives an RF signal to or from YR 11 or YR 27 and between the outputs of the device you get a good isolation "prolazu" RF signals.

On the first control bus from MK 23, the control signals into a serial binary code is also provided to the inputs of PDS 32, IRR 33, the OSD 34, RS 35, the first choice is DPCD 6, second DPKG 12, the second CFD 8 and the second DFCD 7 for inclusion in the operating state at a given frequency and mode. The control signals from the MK 23 changing the operation mode of the second CFD 8 current: transient current from the output CPD 8 large, and therefore the bandwidth of the ring IFPC and performance is great; mode synchronism current CFD is small and the bandwidth of the ring is reduced to provide the desired sideband suppression in the spectrum of the output signal CSC.

A second control bus from MK 23 receives the switching signals to the control inputs CL-17, CL 26, 11 UG, UG 27, BU 24, 25 BU, BU 28, BU 29. These signals from the level of the log. "0" or log. "1" allow you to enable or disable the blocks.

Thus, in the proposed CSC not only generated RF signals for PFP and send, but also formed HF and LF signals for quadrature channel angular modulation (which, incidentally, can be used effectively in the same radio frequency and phase modulation signal send), for automatic compensation of amplitude and phase distortions arising from the formation and processing of radio sources which in some cases is unknown (see Automatic compensators amplitude-phase distortion / Popov P.A. and others; Ed. by Paapaa, Voronezh: Voronezh higher school of Ministry of internal Affairs of Russia, 1998. - 200 S.: ill. Quadrature fo Miravalle radio: Monograph / Popov P.A., Sherstyukov S.A. and others edited Poopola. - Voronezh: Voronezh Institute of the Ministry of internal Affairs of Russia, 2001. - 176 S.: ill.).

Known PV of periodic signals or have limited value discrete phase (see phase Shifter periodic signals on the corners 45°, 135°, 225°, 315°. Pat. UM No. 66639 from 27.04.2007, NS /00, NN 7/18 BIPM No. 25 from 10.09. 2007, str) or insufficiently stable and inaccurate installation phase shifts (see Device control the phase of the oscillations. Pat. UM No. 65699, IPC NN 11/00 from 09. 01. 2007).

The proposed device, the PV can generate almost any desired value of phase shifts with high stability and repeatability under control of the MK 23, so that it can also be used in automatic measuring devices and digital radio receiving devices (see Poberezhskiy Y.S. Digital receiving device. - M.: Radio and communication, 1987. P.101-114).

The ability of the proposed device is determined by the fact that the input blocks of the model and can be performed on other well-known circuits. And in a single chip can be one or two independent CSC with integer DPKG (Integer-N or fractional (Fractional-N). For example, chip LMX2470 company National Semiconductor is a dual synthesizer with two separate control loops: one with a fractional DPCD, another integer. Analogichnaia chip ADF4252 of Analog Devices and others. The key device can be performed on the chip MS 14053 company Motorolla. The adder RF signals made by the scheme of the conventional adder resistors. Switched buffer amplifier design amplifier with common-emitter transistors type BFR93A transistor with the key in the emitter circuit. Binary counters-dividers can be performed on other well-known digital circuits CMOS or TTL. For example, chip CREE 11 - four-digit BCD counter with synchronous setting.

The operation blocks CSC is from MK 23 type C8051F220 company Silicon Laboratoies (see, for example, O. Nikolaychuk "h-compatible microcontrollers firm Silicon Laboratoies (Cygnal)". - M.: OOO "ID LEOPARD", 2004, page 50, 311). All microcontrollers firm Silicon Laboratoies have a built-in Flash-program memory-data (up to 8 up to 128K), built-in additional RAM (up to 1 up to 8K), standard number of ports I/o (port 4 - 32 lines I/o) and more. All this allows to significantly extend the functionality of the device and to obtain new and effective solutions.

Thus, in the proposed CSC not only have the opportunity to generate RF signals for PFP and send, but also to create a service and quadrature signals for angular quadrature modulation agent PE is edincik and to generate a signal with a controllable phase shifter with virtually any discrete phase shift for the automatic compensation of various distortion of radio signals, for automatic measuring devices and digital receivers.

Digital frequency synthesizer containing serially connected reference oscillator, a first frequency divider with a fixed division ratio of the first frequency-phase detector, the first lowpass filter, the first controllable oscillator and the first frequency divider with a variable division ratio, the output of which is connected to a second input of the first frequency-phase detector, connected in series, the second frequency divider with a fixed division ratio of second frequency-phase detector, a second lowpass filter, the first key, the second controllable oscillator, the first buffer amplifier, the output of which is connected to the first input of the adder and the input of the second buffer amplifier, the output of which is the first output and the second frequency divider with a variable division ratio, a signal input connected to the output of the adder, and the output connected to the second input of the second frequency-phase detector; a signal input of the second frequency divider with a fixed division factor is connected with the output of the first controlled oscillator; connected in series with the fifth key, the third controllable oscillator and the third buffer amplifier, and the output of the third schedule the aqueous amplifier is connected to the second input of the adder and the input of the fourth buffer amplifier, the output of which is a second output device and the input of the fifth key is connected with the output of the second lowpass filter; the microcontroller, the first control bus which is connected to the control inputs of the first and second frequency divider with a variable division ratio of second frequency-phase detector, the second frequency divider with a fixed division ratio; a second control bus of the microcontroller are connected to control inputs of the first and fifth keys, second and third driven generators, the first, second, third and fourth buffer amplifiers, characterized in that the input buffer connected in series amplifier-shaper pulses, a first counter-divider and second counter-divider, the output of which is a third output; connected in series additional counter-divider and the main counter-divider, the output of which is the fourth output, and the output of buffer amplifier-shaper pulses, in addition, connected to the signal input of the counter-divider, and the output of the first counter-divider, in addition, is connected with the second (signal) input main counter-divider; input buffer amplifier pulse shaper connected to the output of the first controlled gene is atora, and control inputs of the first, second, primary and secondary counters-dividers is connected to the first control bus of the microcontroller.