Frequency synthesizer with acoustic circuit of adaptive frequency and phase auto tuning

FIELD: radio engineering.

SUBSTANCE: invention may be used for generation of stable frequency network with even interval in receiving and transmitting devices and is notable for short tuning time within broad range of operating frequencies. Device includes controlled generator, frequency divider with variable division factor, frequency and phase detector, reference generator, frequency divider with fixed division factor, controlled charging unit, trapping-by-phase rating unit, microcontroller, trapping-by-frequency rating unit and low-frequency filter consisting of two capacitors, two resistors and two switches.

EFFECT: adaptive stabilisation of transfer characteristics for frequency synthesizer frequency-and-phase auto tuning optimises predetermined quality of dynamic and spectral characteristics within the whole range of synthesized oscillations.

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The invention relates to electrical engineering and can be used for meshing stable frequencies with uniform step of transmitting and receiving devices with small time adjustment in a wide range of operating frequencies.

A well-known diagram of the frequency synthesizer comprising a reference oscillator, a frequency divider with a fixed division ratio, a controllable oscillator, a frequency divider with a variable division ratio, the frequency-phase detector and lowpass filter, forming a ring of pulse-phase-locked loop frequency controlled generator (see Levin VA, Malinowski, VN, Romanov, S. Kaliev, frequency Synthesizers with a system of pulse-phase-locked loop. - M.: Radio and communication, 1989, p.32-40).

Known similar diagram of the synthesizer, which uses a frequency-phase detector with three stable States (charge neutral condition, discharge) and the block of generators of charge/discharge (see, for example, Gardner F.M. Charge-Pump Phase-Lock Loops. // IEEE Transactions on Communications. Vol.com-28, No. 11, November, 1980, p.1849-1858, U.S. Pat. US No. 5055803).

Such schemes synths are simple circuit implementation and provide a sufficiently high operating parameters of the output signal. Application of frequency-phase detector together with the unit charge pump simplifies the design of the synthesizer increases oslabljeni the spurious harmonics of the frequency comparison in the spectrum of the output signal and improves the quality of the PLL controlled oscillator. In this scheme synthesizer tuning frequency of the controlled oscillator is accurate to the phase of the reference oscillator, i.e. the system locked loop has astatism phase (see Shahgeldyan CENTURIES, Shoukin AA System phase-locked loop. M: Communications, 1972, str-280). This expands the scope of such a synthesizer in electronic equipment.

However, a significant drawback of the above synths is pretty low performance; as it is defined by constant values of the gain and bandwidth efficient regulation of the rings a static phase-locked loop.

The closest to the physical nature and technical implementation of the proposed synthesizer is frequency synthesizer described in US patent No. 4156855 "Phase-locked loop with variable gain and bandwidth", H03B 3/04, May, 29, 1979, adopted for the prototype.

Functional diagram of the device of the prototype is shown in figure 1, where we have introduced the following notation:

1 - driven generator (UG);

2 - frequency divider with variable division factor (DPCD);

3 - frequency-phase detector (CPD);

4 - reference generator (DG);

5 is a frequency divider with a fixed division factor (DFCD);

6 - unit controlled charge pump (BUSN);

7 is a block for determining capture phase (BASF);

8 - filter signicast (LPF);

8.1, 8.2 first and second capacitors;

8.3, 8.4, the first and second resistors;

8.5 - key.

The frequency synthesizer includes a controllable oscillator (UG) 1, the frequency divider with variable division factor (DPCD) 2, the frequency-phase detector (CPD) 3, reference generator (DG) 4, the frequency divider with a fixed division factor (DFCD) 5, block controlled charge pump (BUSN) 6, block definitions capture phase (BASF) 7 and the low pass filter (LPF) 8. The yield of 1 UG is the output of the high frequency (HF) devices and is connected to the RF input DPCD 2, the output of which is connected with synchronized inputs CFD 3 and BASF 7. Output DPCD 5 is connected with the inputs of the synchronization CFD 3 and BASF 7. Reference input DPCD 5 is connected to the output of the EXHAUST gas 4. The first output CFD 3 is the output of the signal charge and is connected to the switching input of the charge BUSN 6. The second output CFD 3 is the output signal of the discharge and is connected to the switching input of the discharge BUSN 6. This LPF 8 contains the key to 8.5, the capacitor 8.2, connected in series to the first capacitor 8.1, the first resistor 8.3 and the second resistor 8.4, the second terminal of which is connected to a common bus. The first conclusions of the first 8.1 and 8.2 second capacitors connected to the output BUSN 6, and with the control input 1 UG. The second terminal of the second capacitor 8.2 is connected to a common bus. The connection point of the first 8.3 and second tie connected with the first output key 8.5, the second output of which is connected to a common bus. Output ϕ BASF 7 is connected to the input switching current BUSN 6 and the switching input key 8.5.

The device prototype works as follows.

The reference frequency signal from the output of the EXHAUST gas 4 is supplied to the reference input DPCD 5, which is divided in frequency to the desired number of times. When the frequency deviation of the output fluctuations UG 1 from the desired nominal value ω₀corresponding to the capture phase, the outputs CFG 3 receive the pulse signals of the charge or discharge, the duration of which is equal to the time difference of arrival of pulses from DPCD 2 and DPCD 5 inputs CFD 3. This CFD 3 made on the triggers, works on the principle of recording and storing information about the input signals and their outputs generates signals in the form of a three-state digital logic (charge neutral condition, discharge). State CFD 3 called the front edges of the input pulses with DPCD 5 and DPCD 2. When the pulse signals synchronized input CFD 3 ahead of time pulses to the trigger input, the second output CFD 3 receive the pulse signal of the discharge, and if on the contrary behind in time, the first output CFD 3 receive the pulses of the signal charge. In the case of coincidence in time fore fronts of these compare pulse sequentially the TEI CFD 3 is in the neutral state. While the pulses at the outputs of the signal charge and discharge no. In BUSN 6 is also in the passive neutral state. This state corresponds to the capture mode phase ring phase-locked loop (PLL), and the output BASF 7, you receive a corresponding signal "ϕ". BASF 7 is a trigger circuit. The input signals pass through the pre-shaper pulses with a duration of about 10% of the pulse period of the synchronization signal. As pulse shapers are waiting multivibrators. When the time interval between the moments of arrival of the pulses at the inputs BASF 7 exceeding the duration of the pulses at the output of the trigger circuit, a signal "ϕ" level logical "1"and when the time interval falling within 10% of the area signal of logical level "0", which corresponds to the matching phase. To convert the logic States CFD 3 into an analog signal suitable for controlling UG 1, used BUSN 6. BUSN 6 is a device consisting of two series-connected generators charge and discharge [see, for example, Gardner F.M. Charge-Pump Phase-Lock Loops. // IEEE Transactions on Communications. Vol.com-28, No. 11, November, 1980, p.1849-1858, U.S. Pat. US No. 5055803]. The point of connection of these generators is used for connecting the latter to the low-pass filter 8. UE is providing generators current charge/discharge, i.e. translation in the active state is performed by applying appropriate signals to the charge and discharge with CFD 3. The generators are the same, but with the opposite sign of the amount of current that can be changed by using the input switching (in this case, the signal capture phase "ϕ"). BUSN 6 is used to convert the error signal of the compared input signals CFD 3 into an analog signal adjustment UG 1 through the LPF 8, from which parameters strongly depend on the dynamic and static parameters rings FAP. Under the influence of the output signals of the charge or discharge CFD 3 through BUSN 6 voltage adjustment UG 1 on the output of the LPF 8 is changed as long as the frequency UG 1 is the desired nominal value ω₀. The duration of the output pulse signals of the charge or discharge with CFD 3 steady state capture phase ring FAP tends to zero, i.e. CFD 3 passes in a mode neutral state. Use in a closed ring FAP CFD 3 and BUSN 6 allows to obtain zero static phase error, i.e. astatism phase system (type 2) [see, for example, Gardner P.M. Charge-Pump Phase-Lock Loops. // IEEE Transactions on Communications. Vol.com-28, No. 11, November, 1980, p.1849-1858]. In this diagram, synthesizer, during the transition process realignment, ring PLL mode with the increased value of the current charge and discharge BUSN 6 using BASF 7. In addition, the use of low-pass filter 8 with variable bandwidth signal "ϕ" BASF 7: with a wide - at the time of the transition process and narrow in terms of the capture phase using the key 8.5. Using 8.5 key change time constants LPF 8 and hence its bandwidth.

As a result, the ring of FAP depending on the magnitude of the phase error signal capture phase output BASF 7 mode wide band effective regulation with an increased rate to accelerate the transition frequency, and when reaching the capture phase will be switched to the nominal value of the strip of effective regulation and strengthening to achieve acceptable static quality parameters of the output signal of the frequency synthesizer.

A significant drawback of the prototype is that it does not Jive time changes of the values of currents charge and discharge BUSN 6 with values of bandwidth low-pass filter 8. This leads to a sharp surge control voltage UG 1 and, consequently, the buckling ring FAP, and this in turn leads to an anemic nature of the transition frequency.

The objective of the present invention is used in the frequency synthesizer static ring is FAP close-to-optimal performance.

To solve the problem in the frequency synthesizer with a static ring adaptive frequency-phase-locked loop containing a controllable oscillator, a frequency divider with a variable division ratio, the frequency-phase detector, reference oscillator, a frequency divider with a fixed division ratio, the unit is controlled charge pump, the block definition capture phase and a low-pass filter, containing the first key, the first and second capacitors, first and second resistors, and the output of the controlled oscillator, which is the output of the high frequency device is connected to a high frequency input of the frequency divider with a variable division ratio, the output of which is connected to the first synchronized inputs of the frequency-phase detector and block definitions capture phase, the output of the frequency divider with a fixed division factor is connected with the second inputs of the frequency-phase detector and block definitions capture phase, which is also the input synchronization output of the reference oscillator is connected to the reference input of the frequency divider with a fixed division ratio, the first and second outputs of the frequency-phase detector, which are respectively the output signals of the charge and discharge, respectively connected with lane is the first and the second switching unit controlled charge pump, which are respectively the inputs of the charge and discharge, the output unit controlled charge pump is connected with the control input of the controlled oscillator and the first output of the first capacitor, the second terminal of which is connected to the first output of the first resistor and the second findings of the second capacitor and the first key is connected to a common bus according to the invention introduced the microcontroller, the control input of which is a control input of the block definition capture frequency, and the low-pass filter, put the second key, and the first synchronized input unit definition capture frequency is connected to the output of the frequency divider with a variable division ratio, the second input unit definition of seizure frequency, which is a synchronization input connected to the output of the frequency divider with a fixed division ratio, the output of block definitions capture frequency is connected with the first information input of the microcontroller, the output of block definitions capture phase is connected with the second information input of the microcontroller, the first microcontroller is a signal output capture frequency and is connected to the switching input of the second key, the second output of the microcontroller is a signal output of the capture phase and is connected to the switching input of the first is th key the third output of the microcontroller is the output of the reset signal and is connected to inputs of the inputs set the initial state of the frequency divider with variable division factor of the frequency divider with a fixed division ratio, and a frequency-phase detector, the fourth output of the microcontroller, which is a control output connected to inputs of a third input of the controllable charge pump, which is the input switching currents, in addition, the second terminal of the first capacitor is connected with the joint of the first conclusions of the second capacitor, the second resistor and the second key, the second terminal of which is connected to a common bus, the second terminal of the second capacitor is connected with the second output of the first resistor, the second terminal of the second resistor is connected to the first output of the first key.

Graphic materials presented in the application materials:

Figure 1 - functional diagram of the device of the prototype.

2 is a functional diagram of the device.

Figure 3 - timing diagram of the States of the switching signals.

4 is a graph of the transition process when changing frequency.

Functional diagram of the device is shown in figure 2, where we have introduced the following notation:

1 - driven generator (UG);

2 - frequency divider is variable division factor (DPCD);

3 - frequency-phase detector (CPD);

4 - reference generator (DG);

5 is a frequency divider with a fixed division factor (DFCD);

6 - unit controlled charge pump (BUSN);

7 is a block for determining capture phase (BASF);

8 is a lowpass filter (LPF);

8.1, 8.2 first and second capacitors;

8.3, 8.4, the first and second resistors;

8.5, 8.6, the first and second keys;

9 - microcontroller;

10 is a block for determining capture frequency (BOSCH).

The proposed device comprises a controllable oscillator (UG) 1, the frequency divider with variable division factor (DPCD) 2, the frequency-phase detector (CPD) 3, reference generator (DG) 4, the frequency divider with a fixed division factor (DFCD) 5, block controlled charge pump (BUSN) 6, block definitions capture phase (BASF) 7, a lowpass filter (LPF) 8, the microcontroller 9, the control input of which is a control input of the block definition capture frequency (BOSCH) 10. LPF 8 contains the first 8.1 and 8.2 second capacitors, the first 8.3 and 8.4 second resistors and the first 8.5 and 8.6 second keys. However, UG 1, which is the output of the high frequency device is connected to the RF input DPCD 2, the output of which is connected to the first synchronized inputs CPD 3, BASF 7 and BOSCH 10. Output DPCD 5 is connected with the second inputs CPD 3, BASF 7 and BOSCH 10, which are input the AMI synchronization. The output of the EXHAUST gas 4 is connected to the reference input DPCD 5. The first output CPD 3, which is the output signal of the charge, connected to the first input BUSN 6, which is a switching input of the charge, and the second output CPD 3, which is an output signal of a discharge, is connected with the second input BUSN 6, which is a switching input of the discharge. Output BOSCH 10 (exit f) is the output signal of seizure frequency and connected to the first information input of the microcontroller 9, exit BASF 7 (exit "ϕ") is the output signal of the capture phase and is connected with the second information input of the microcontroller 9. The first output of the microcontroller 9 (entrance'f') is the output signal of seizure frequency and is connected to the switching input of the second key 8.6, the second output of the microcontroller 9 (exit "ϕ') is the output signal of the capture phase and is connected to the switching input of the first key 8.5.

The third output of the microcontroller 9 is the output of the reset signal and is connected to the inputs set the initial state DPCD 2, DPCD 5 and CFD 3. The fourth output of the microcontroller 9, which is a control output connected to the input switching current BUSN 6, the output of which is connected with the control input 1 UG. In the low-pass filter 8, the first output of the first capacitor 8.1 combined with the output BUSN 6. The second terminal of the first capacitor 8.2 is connected with first the mi combined the findings of the first 8.3 and 8.4 second resistors, the second capacitor 8.2 and the second key 8.6. The second terminal of the second capacitor 8.2 combined with the second output of the first resistor 8.1 and is connected to a common bus. The second terminal of the second resistor 8.4 is connected to the first output of the first key 8.5, the second terminal of which is connected to a common bus. The second output of the second key 8.6 is also connected to a shared bus.

The proposed device operates as follows.

The reference frequency signal from the output of the EXHAUST gas 4 is supplied to the reference input DPCD 5, which is divided in frequency to the desired number of times. The frequency of the output oscillation ANGLE 1 is equal to the desired nominal value ω₀corresponding to the capture phase of the output signal DPCD 2 with the output signal DPCD 5. When it arrives at the control input of the microcontroller 9 external command ("Change frequency") to install instead of ω₀₁new frequency ω₀₂at time t₀(see figure 3) from the third output of the microcontroller 9 is given a short signal with a logical level "1" (Reset) inputs of the installation to its original state DPCD 2, DPCD 5 and CFD 3. The original state DPCD 2 and DPCD 5, made on the principle of counting the input pulses is reset to the zero state. The original state CFD 3 is the translation of it in the neutral condition. The duration of the reset signal is small, but sufficient to install the PDK is 2, DPCD 5 and CFD 3 in the initial state. After the expiration of the signal reset counters DPCD 2 and DPCD 5 start your account at the same time, and one of the outputs CFG 3 a signal charge or discharge depending on the sign of the error compared to the input signals. Thus, the transition process begins with a zero phase difference at CFD 3 (neutral condition), i.e. to bind the phases on CFD 3 and simultaneous account DPCD 2 and DPCD 5. BASF 7 is a digital filter and produces a logic level received at its output. Output BASF 7 is a signal of logical "0"when the temporary misalignment between the synchronization signal and the synchronized signal is less than 15 NS for five periods of the frequency comparison is equal to the repetition frequency of a pulse signal synchronized with the output DPCD 5 and supplied to the input synchronization CFD 3. Output BASF 7 sets the signal level of the logic "1"when a temporary misalignment of the compared signals is greater than 30 NS within one period of the frequency comparison [see, for example, "Lock detect digital filter comprising a chip LMX2485E company National Semiconductor].

BOSCH 10 may be implemented as a digital filter, and a trigger circuit, a similar pattern definition capture in US patent No. 4156855. Upon reaching massoglia the project for a frequency less than 5-10% at the inputs BOSCH 10, at its output a signal with a logical level "1", and when more substantial mismatch (more than 5-10%) frequency signal of logical level "0". In the starting time t₀with outputs BASF 7 and BOSCH 10 to the microcontroller 9 receives signals from the logic level "0" the absence of seizure frequency and seizure phase. At the same time from the first output of the microcontroller 9 signal capture frequency with logical level "1" is supplied to the switching input of the second key, 8.6, and from the second output of the microcontroller 9 signal capture phase with logical level "1" is supplied to the switching input of the first key 8.5. Under the action of these signals keys 8.5 and 8.6 close, changing the structure and order low-pass filter 8. The logical signal "1" from the fourth control output ("Current") of the microcontroller 9 to the input switching current BUSN the last 6 will be switched to the increased value of current charge and discharge. From the moment of time t₀CFD 3 together with BUSN 6 in the ground (connect to the shared bus, the second output of the first capacitor 8.1 begins to possess the properties of a bistable electronic switch, which has only two stable States for rapid charging or discharging of the second capacitor 8.1.

As a result, the gain in the ring of FAP increases significantly, and fixed the straps LPF 8 is reduced after grounding the second output of the first capacitor 8.1 and the first combined findings of the second capacitor 8.2 and 8.3 first and second 8.4 resistors using the second key, 8.6, which generally leads to an increase in bandwidth efficient regulation of the rings phase-locked loop.

Thus, in the time interval t₀and t₁implemented mode wide band effective regulation with increased gain rings FAP. In the time interval t₀and t₁ring-locked loop loses astatism phase, but retains astatism frequency. When this is achieved the maximum rate of change of voltage at the control input 1 UG. At time t₁achieved equality comparison of frequencies of the output pulse sequences with DPCD 2 and DPCD 5 CPD 3, and therefore output BOSCH 10 to the microcontroller 9 passes the signal capture frequency, and from the first output of the microcontroller 9 for switching the input of the second key 8.6 signal capture with the frequency level of logical "0"which opens the second key 8.6. At time t₁the output signal of the reset 9 appears a short pulse with a logic level "1" to reset DPCD 2 and DPCD 5 and install CFD 3 in the neutral state, i.e. is binding on the phase comparison of the input signals CFD 3 for eliminating unwanted surge control voltage output from the LPF 8 the control input UG 1 at the time of switching of the second key 8.6. The first resistor 8.3 again p is clochette, but it remains shunted by a second resistor 8.4, closed the first key 8.5. BUSN 6 remains in the mode of increased value current charge and discharge. At this time, the effect of damping in the system-locked loop increases with the increased amount of current, charge and discharge BUSN 6. From the moment of time t₁the transition process, the system regains properties astatism phase and seeks to resolve the mismatch in phase, existing at the time of achieving seizure frequency. When restoring astatism phase in the PLL system after some time (about five periods of the frequency comparison)that are required to correct phase mismatch, BASF 7 establishes the fact of state capture phase at time t₂and its output is a signal with a logical level "1"is supplied to the second information input of the microcontroller 9. At time t₂the output signal of the reset 9 appears a short pulse with a logic level "1" for the next reset DPCD 2 and DPCD 5, installation CFD 3 in the neutral state and the binding phase, and from the second output of the microcontroller 9 for switching the input of the first key 8.5 signal capture phase with the logical level "0", which opens the first key 8.5, eliminating the bypass lane is on resistor 8.3 second resistor 8.4. During the time interval t₁and t₂ring the FAP is in the mode of a narrow strip of effective regulation to slow down the speed of the transition process when approaching a steady state. With the same time t₂BUSN 6 will be switched to the rated current value of charge and discharge, as in the fourth, the control output ("Current") of the microcontroller 9 level is set to a logical "0". This effect of damping in the system-locked loop is increased as the resistance value of the first resistor 8.3 significantly greater than the resistance of the second resistor 8.4. Then the system PLL synthesizer very quickly before time t₃produces deregulation for the last few hundred Hertz output frequency 1 UG.

The use of low-pass filter 8, a variable current charge and discharge in BUSN 6, a variable damping in the low-pass filter, a synchronous control DPCD 2 and DPCD 5 enables the system PLL synthesizer to adapt parameters for speed adjustment frequency UG 1 to the new value. The nature of the transition process when changing the frequency tends to the optimum (see curve 2 in figure 4), quickly fades out and has no overshoot (see curve 1 in figure 4).

The novelty of the invention lies in the fact that for the implementation of adaptive mode C the subjects in the control circuit of the controlled oscillator is used LPF with variable structure:

When this low-pass filter has a wide bandwidth, and the ring-locked loop performs the tracking frequency (astatism frequency). Thus, prior to time t₁the PLL system operates in the mode of frequency-locked loop. In this case, no extra hardware cost (for example, when the method of pre-charging by using a digital to analogue Converter) is implemented Express setup UG 1.

From time t₁the PLL system becomes static phase by increasing order low-pass filter 8. Band effective regulation of the ring when it is set below the starting value, and increased the value of the current of the charge pump is maintained. The transition process from time t₁until t₂comes with small damping. The reduction in damping is implemented by shunting the primary of the first resistor 8.3 auxiliary second resistor 8.4.

- At time t₂the transition process is nearly complete, but in order to obtain the required noise performance in the static mode, the frequency synthesizer is optimized bandwidth efficient regulation of the rings with the transition to the optimal value of the current of the charge pump and the damping value of the first resistor 8.3. The time t₃is the beginning of the static mode, the phase is Oh-locked loop. The time interval between t₂and t₃depends on the accuracy of the installation of a new frequency (for example, ±100 Hz, ±1 kHz and so on). When reaching the capture (synchronism) the frequency is reset counters included in DPCD 2 and DPCD 5. This avoids jumps in phase by CVD when switching at time t₁and thereby to avoid oscillatory processes that slow transients.

Thus, in the proposed frequency synthesizer the nature of the transition process when changing the output frequency is substantially improved, and reduced its duration due to changes in specific points in time patterns of the lowpass filter and block parameters controlled charge pump during the time course of the transition process. This results in stabilization of the gear ring characteristic frequency phase-locked loop, which allows to optimize the system for a given dynamic and spectral characteristics in the whole range of the synthesized hesitation.

A frequency synthesizer with a static ring adaptive frequency-phase-locked loop containing a controllable oscillator, a frequency divider with a variable division ratio, the frequency-phase detector, reference oscillator, a frequency divider with a fixed coefficient of the population, the unit is controlled charge pump, the block definition capture phase and a low-pass filter, containing the first key, the first and second capacitors, first and second resistors, and the output of the controlled oscillator, which is the output of the high frequency device is connected to a high frequency input of the frequency divider with a variable division ratio, the output of which is connected to the first synchronized inputs of the frequency-phase detector and block definitions capture phase, the output of the frequency divider with a fixed division factor is connected with the second inputs of the frequency-phase detector and block definitions capture phase, which are also inputs the sync output the reference oscillator is connected to the reference input of the frequency divider with a fixed division ratio, the first and second outputs of the frequency-phase detector, which are respectively the output signals of the charge and discharge, are connected respectively with the first and second switching unit controlled charge pump, which are respectively the inputs of the charge and discharge, the output unit controlled charge pump is connected with the control input of the controlled oscillator and the first output of the first capacitor, the second terminal of which is connected to the first output of the first resistor and the second conclusions W is the second condenser and the first key is connected to a common bus, characterized in that the microcontroller, the control input of which is a control input of the block definition capture frequency, and the low-pass filter, put the second key, and the first synchronized input unit definition capture frequency is connected to the output of the frequency divider with a variable division ratio, the second input unit definition capture frequency, which is a synchronization input connected to the output of the frequency divider with a fixed division ratio, the output of block definitions capture frequency is connected with the first information input of the microcontroller, the output of block definitions capture phase is connected with the second information input of the microcontroller, the first output of the microcontroller is a signal output capture frequency and is connected to the switching input of the second key, the second output of the microcontroller is a signal output of the capture phase and is connected to the switching input of the first key, the third output of the microcontroller is the output of the reset signal and is connected to inputs of the inputs set the initial state of the frequency divider with variable division factor of the frequency divider with a fixed division ratio, and a frequency-phase detector, the fourth output of the microcontroller, which is a UE is Allaudin output, connected with additionally introduced the third input of the controllable charge pump, which is the input switching currents, in addition, the second terminal of the first capacitor is connected with the joint of the first conclusions of the second capacitor, the second resistor and the second key, the second terminal of which is connected to a common bus, the second terminal of the second capacitor is connected with the second output of the first resistor, the second terminal of the second resistor is connected to the first output of the first key.