Frequency synthesiser

FIELD: radio engineering.

SUBSTANCE: frequency synthesiser includes two frequency phase detectors, two low-pass filters, voltage-controlled generator, two dividers with variable division factor, buffer cascade, two synchronism indicators, coincidence circuit, D flip-flop, shaper of control signal and amplifier with controlled amplification factor, two-mode self-oscillator, control unit, key, switch from two directions, storage unit and signal source of reference frequency.

EFFECT: considerable increase of quick action when switching the frequencies together with high purity of spectrum of output signal.

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The present invention relates to electrical engineering and can be used as low-noise fast switching frequency of the local oscillator of the receiver and other devices that require fast frequency at high spectral purity of the output signal.

Known digital frequency synthesizer (CSC), built on the basis of pulse-phase-locked loop (IFPC) with a frequency divider with variable division factor (DPCD) in the feedback circuit (see Shapiro, D.N., Pain A.A. fundamentals of theory of frequency synthesis. - M.: Radio and communication. 1981., page 39, figure 1.7, and Levin, C. A. and other frequency Synthesizers with a system of pulse-phase-locked loop. - M.: Radio and communication. 1989, p. 9, figure 1.1.).

The advantage of such CSC using modern chips is the possibility of the formation of the output of its large number of discrete frequency stability equal to the stability of a single reference crystal oscillator (CRC) with small dimensions and low power consumption DC.

The disadvantage of this adnocarcinoma CSC is that it is impossible to obtain simultaneously high spectral purity of the output frequency (RF) signal during the reconstruction of a wide range of frequencies with a small spacing of the grid frequency and high speed when switching from one frequency to another.

It is known that the system is EMA IFPC CSC is a lowpass filter with respect to noise fluctuations of the reference frequency and the high-pass filter with respect to the noise generator, voltage-controlled (VCO). So, if you want to suppress the noise fluctuations of the reference frequency to the desired value, it is necessary to use a narrow-band loop IFPC. In this case, there will be requirements for performance and are not compensated intrinsic noise VCO, why the need for broadband loop IFPC. On the other hand, if you design a ring IFPC with a relatively wide band of frequencies, as required for high-speed synthesizer, then the noise of the reference oscillator after increasing the frequency by multiplying the proportional coefficient N to the output frequency will define the main noise at the output of the synthesizer.

This is a basic contradiction adnocarcinoma CSC, which prevents high current requirements for high-speed high-frequency and low-noise synthesizer frequency.

Known dvukhkontsevoi CSC with frequency modulation (FM) with the consistent inclusion of the rings IFPC, which functions casttoobjectname divided between the first and second rings, which reduces the above contradictions (see patent GR No. 63996 of 29 December 2006). In this CSC first ring narrowband and is the reference for the second broadband output ring. In the second ring by using a frequency divider with a fractional variable division factor (DPCD) pax is an integer DPKG is possible to obtain high performance, currently it is necessary in communication systems based on fast switching frequency for a given program. However, in this synth even using modern chips CSC with ΣΔ-modulators (see, for example, the chip ADF4252 of Analog Devices) is the so-called "interference fragmentation", which is 10-20 dB degrade the spectral purity of the VCO compared to CSC based on integer DPCD that tested experimentally.

The closest in technical essence to the invention is a frequency synthesizer (see patent RU No. 2329594 C1 H03L 7/18 20. 07. 2008 bull. No. 20), which is taken as a prototype.

The block diagram of the device of the prototype is shown in figure 1, where we have introduced the following notation:

1 - source signal from a reference frequency (ISAC);

2 and 9, the first and second frequency-phase detector (CPD);

3 - the control unit (cu);

4 and 10, the first and the second frequency divider with variable division factor (DPCD);

5 and 8, the first and second low pass filters (LPF);

6 is a voltage controlled oscillator (VCO);

7 - buffer cascade (Bq);

11 - memory block (ZB);

12 - switch from two directions (PD);

13 - dual mode oscillator (YES);

14 - key (KL);

15 is a voltage divider (NAM);

16 - unit time intervals (BVI).

The device prototype contains sequentially connect the i.i.d. source signal from a reference frequency ISAC 1 and buffer cascade BK 7, the first output of which is connected to the first input of the first CPD 2, the output of which through the first low-pass filter 5 is connected with the control input of the VCO 6, the first output of which through the first DPCD 4 is connected to a second input of the first CFD 2.

Thus, on the basis of the VCO 6 is formed by the first ring IFPC.

The second output Bq 7 is connected to the first input of the second CPD 9, the output of which through the second low-pass filter 8 is connected to the input ZB 11 and the first input of the PD 12, the second input connected to the output of the CG 11, and the output of the PD 12 is connected with the control input YES 13, the first output of which through the second DPKG 10 is connected with the second input of the second CFD 9.

Therefore, the second ring IFPC based on dual-mode oscillator YES 13 is in parallel with the first ring.

The second output of the VCO 6 through connected in series DN 15 and CL 14 is connected to RF input YES 13, a second output which is the output device. Managing input device prototype is input BU 3, the output of which is connected to control inputs of the first DPCD 4, the second DPKG 10 and the input of the BVI 16, the output of which is connected to control inputs of PD 12 and CL 14.

The device prototype works as follows.

The management team for inclusion is fed to the input BU 3, the output of which is the command to establish asked (the same, for example, equal to N) ratio Delany is for the first DPCD 4 and the second DPKG 10. The signal from the first output of the VCO 6 through the first DPCD 4 and the signal from the first output YES 13 through the second DPKG 10 serves respectively to the second inputs of the first CFD 2 and the second CPD 9, the input of which the signal from ISAC 1 after division in BK 7 with his first and second outputs, respectively.

In addition, the management team for inclusion through BU 3 served on BVI 16, which generates a signal of duration T₃to control PD 12 and CL 14. This command DD 12 connects the output of the second low-pass filter 8 with a control input YES 13 at time T₃and at the same time opens CL 14. The output voltage from the first CFD 2 through the first low-pass filter 5 is fed to the control input of the VCO 6 and after some time T₃provides entry into synchronism in the first ring IFPC on the basis of the VCO 6, the output of which is formed a given frequency.

At the same time, the output voltage from the second CFD 9 through the second low-pass filter 8 and the PD 12, closed on command from BVI 16, is fed to the control input YES 13. The voltage on the control input YES 13 after some time T₃provides reception outputs YES 13 frequency exactly equal to the reference frequency multiplied by N is the division ratio of the second DPKG 10. Thus, simultaneously with the first works, the second, additional ring IFPC, and in both rings at the output of which is are the same frequency. At the same time, the control voltage output from the second LPF 8 is stored in the CG 11.

After a period of time T₃command output BVI 16 changes and key CL 14 is closed, and the PD 12 disables the control input YES 13 from the second LPF 8 and connects its input to the output of the CG 11. Therefore, the second ring IFPC stops working and YES 13 passes in a mode of self-oscillations at a frequency close to that which was set before disconnecting. At the same time at the RF input YES 13 through a closed CL 14) 15 voltage from the second output of the VCO 6 is seizure frequency oscillations YES 13 oscillations of the VCO 6.

Therefore, the output voltage YES 13 will have a frequency equal to the synthesized VCO 6, which is covered by the ring IFPC, and the noise corresponding to the noise generator YES 13, which operates in the mode of self-oscillations. These noise oscillator without rings IFPC significantly lower than those synths with ring IFPC based on integer DPKG (approximately 20-30 dB according to the data given in the description of the synthesizer prototype on page 2).

Thus, at the output of the prototype is generated RF signal with high spectral purity and low noise stability, is exactly equal to the stability of the VCO covered by the ring IFPC.

The disadvantage of the considered synthesizer prototype is a small performance.

Work and the known device switching frequency occurs in two stages. In the first phase of the VCO 6 and may 13 work, as usual, in the system IFPC and generate on their outputs are the same given frequency. And in fact, the time for establishing synchronism in both rings IFPC substantially less than the predetermined time interval T₃that is determined from the BVI 16 (of course, always with some margin). In other words, already at the first stage, the deterioration of performance due to wait till the end of time interval T₃after the establishment of synchronism in the system IFPC.

In the second phase, the VCO 6 continues to operate in the mode IFPC, and YES 13 operates as an oscillator in the capture mode frequency. When this RF voltage (external excitation F_OStowards YES 13) from the second output of the VCO 6 through the voltage divider DN 15 and closed CL 14 is supplied to the oscillating circuit YES 13. This "noise" in the voltage of the external excitation F_OS(from the VCO 6) will be filtered by the loop oscillator YES 13. To this "noise" in a stationary mode was minimal, provided the divisor DN 15 external RF excitation voltage E_OSfrom the VCO 6. The level of external RF excitation voltage E_OSis from the VCO 6 by using a voltage divider DN 15 a little more than the minimum required for the implementation of seizure frequency in YES 13 fluctuations at the output of the VCO 6. But you know, coglianese setting process (capture) the frequency of the oscillator increases with decreasing values of the voltage of the external excitation F _OS(see the description of the device the prototype page 6).

Therefore, the minimum value of the voltage of the external excitation F_OSin the synthesizer prototype leads to a significant increase in the duration of the setting process (capture) the frequency of the oscillator at the second stage, i.e. to poor performance.

Thus, the performance of the synthesizer prototype is not enough as the first stage switching frequency and at the second stage when the seizure frequency YES 13 from the frequency of the VCO 6.

To eliminate this drawback in the frequency synthesizer containing connected in series source signal from a reference frequency, and a buffer stage, the first output of which is connected to the first input of the first frequency-phase detector, the output of which through the first low pass filter connected with the control input of the oscillator, voltage-controlled first outlet through which the first frequency divider with variable division factor is connected with the second input of the first frequency-phase detector; a second output buffer of the cascade is connected to the first input of the second frequency-phase detector, the output of which through the second low pass filter connected to the input of the storage unit and the first input switch two directions, a second input connected to you who Odom storage unit, and the output of the switch from two directions is connected with the control input of the dual-mode oscillator, a first outlet through which the second frequency divider with variable division factor is connected with the second input of the second frequency-phase detector; the second output of the dual mode oscillator is the output of the device, as well as the key, the output of which is connected to a high frequency input dual mode oscillator, and the control unit, the input of which is the input device, the output control unit connected to control inputs of the first and second frequency divider with variable division factor entered the first and second indicators of synchronism, the logical schema matching, D-trigger the driver of the regulating signal and the amplifier with adjustable gain, and the inputs of the first and second indicators of synchronism are connected respectively to the outputs of the first and second frequency-phase detector, and the outputs of the first and second indicators of synchronism are connected respectively with the first and second inputs of the logic circuit matches the output of which is through E-trigger and driver of the regulatory signal is connected with the control input of the amplifier with an adjustable gain, an input connected to the second generator output, the controlled voltage is eat, and the output to the input key, a control input connected to the output of D-flip-flop and managing input from two directions, while the output control unit is connected with the reset input of D-flip-flop.

The block diagram of the proposed device is shown in figure 2, where we have introduced the following notation:

1 - source signal from a reference frequency (ISAC);

2 and 9, the first and second frequency-phase detector (CPD);

3 - the control unit (cu);

4 and 10, the first and the second frequency divider with variable division factor (DPCD);

5 and 8, the first and second low pass filters (LPF);

6 is a voltage controlled oscillator (VCO);

7 - buffer cascade (Bq);

11 - memory block (ZB);

12 - switch from two directions (PD);

13 - dual mode oscillator (YES);

14 - key (KL);

17 and 18, the first and second indicators of synchronism (IP);

19 is a logic diagram matches (SS);

20 - D-trigger (DT);

21 - shaper regulatory signal (FRS);

22 - amplifier with adjustable gain (RU).

The proposed device has connected in series source signal from a reference frequency ISAC 1 and buffer cascade BK 7, the first output of which is connected to the first input of the first CPD 2, the output of which through the first low-pass filter 5 is connected with the control input of the VCO 6, the first output of which through the PE the new DPKG 4 is connected to a second input of the first CPD 2, the output of which, in addition, connected to the input of the first indicator of synchronism IP 17, the output of which is connected to the first input of logic circuit matches SS 19. On the basis of the VCO 6 is formed first ring IFPC.

The second output Bq 7 is connected to the first input of the second CPD 9, the output of which through the second low-pass filter 8 is connected to the input ZB 11 and the first input of the PD 12, the second input connected to the output of the CG 11. With the PD 12 is connected with the control input YES 13, the first output of which through the second DPKG 10 is connected with the second input of the second CPD 9, the output of which, in addition, is connected to the input of the second indicator synchronism IP 18, the output of which is connected with the second input of the logic circuit matches SS 19. Based on the dual mode oscillator YES 13 formed by the second ring IFPC.

The second output of the VCO 6 through connected in series amplifier with adjustable gain ROUX 22 and CL 14 is connected to RF input YES 13, a second output which is the output device. Managing entrance of the proposed device is the input BU 3, the output of which is connected to control inputs of the first DPCD 4, the second DPKG 10 and the reset input of D-flip-flop DF 20. The DT output 20 is connected to control inputs CL 14 and the PD 12, and through the FRS 21 is connected with the control input PN 22.

Amplifier with variable gain ROUX 22 has an adjustable e is atterney negative feedback. Moreover, the control signal at its control input, which is formed at the exit of the FRS 21, is designed to exponential changes of the gain of the input signal.

The proposed device operates as follows.

The management command to activate the target frequency midrange comes from BU 3 control inputs of the first DPCD 4 and the second DPKG 10, setting them in the same ratios N and also to the reset input DT 20, setting its output to the command level Log.0. This command DD 12 connects the output of the second low-pass filter 8 with a control input YES 13, and the key CL 14 disconnects the output of the amplifier RU 22 RF input YES 13. The output voltage from the first CFD 2 through the first low-pass filter 5 is fed to the control input of the VCO 6. The result is a process of entering into synchronism in the first ring and the output of the first IP 17, included after the first CPD 2, is formed level Log.1, which is supplied to the first input of the SS 19. At the same time, the output voltage from the second CFD 9 through the second low-pass filter 8 and the PD 12, closed on command from DT 20, is fed to the control input YES 13. The result is a process of entering into synchronism with the second ring IFPC and the output of the second IP 18, inclusive after the second CPD 9, is formed level Log.1, which is supplied to the second input of the SS 19. At the same time the control voltage output from storaging 8 is stored in the CG 11.

Once the first and second inputs SS 19 receive the same levels Log.1, the output SS 19 is formed level Log.1 that comes to D-input of D-flip-flop DF 20, setting its output signal level Log.1.

This signal PD 12 disconnects the output of the second low-pass filter 8 with a control input YES 13 (i.e. the second ring IFPC opened), and the key CL 14 connects the output of the amplifier RU 22 RF input YES 13. At the same time the control voltage output from the CG 11 via the PD 12 is supplied to the control input YES 13. In addition, the level Log.1 comes from the output of DF 20 to the input of the shaper regulating signal FRS 21, the output of which a signal is generated that is designed to exponential changes of the gain of the amplifier with adjustable gain ROUX 22 (see timing diagrams of the signal for the exponential change of gain ROUX 22 figa, b, C).

Amplifier with adjustable gain is in the emitter circuit of a variable resistor, whose value may change from external control voltage. Using a variable resistor in the emitter circuit of the amplifier PN 22, is negative feedback. From the value of this variable resistor determines the gain of RU 22. As the variable resistor is used field is ransistor. When the control voltage on the gate field-effect transistor increases, the value of the variable resistor is reduced, and therefore, decreases negative feedback and reinforcement RU 22 increases. Thus increasing the RF voltage of the external excitation F_OSRF input YES 13. Conversely, when the control voltage is reduced, consequently reducing the amplification RU 22 and the level of external excitation F_OS.

The voltage drop from Log.0 to Log.1 (i.e. short pulse) output DT 20 (see figa) is fed to the input of FRS 21, the output of which is formed "jump" control voltage (figb), significantly exceeding the minimum size needed to obtain at the output of PN 22 voltage of the external excitation F_OSin the stationary (steady-state) mode. This "leap" with a minimum width at the beginning and then exponentially decays to a steady minimum value sufficient to protect the process of seizure frequency in YES 13 and which provides a minimum level of "noise". In other words, a short pulse from the output of DF 20 causes an exponential process in the FRS 21, and the duration of this process will depend on the magnitude of its input capacitance. This "leap" control voltage significantly reduces the time of seizure frequency YES ot oscillations of the VCO 6, i.e. seizure frequency in YES 13 occurs at a higher speed than in the mid - prototype.

The advantage of the proposed technical solutions that introduced new elements arranged corresponding connections with other nodes of the schema is the ability to significantly improve the performance of the synthesizer as the first stage in the mode of occurrence in synchronism and at the second stage in the capture mode frequency YES 13 from the external excitation and simultaneously obtain high spectral purity of the output signal.

Proof of the ability of the proposed device is that the input blocks of the model and can be performed on the well known circuits. Digital synthesizers running on ICS CSC with IFPC different companies. At the same time in a single chip can be one or two independent CSC with integer DPKG (Integer-N or fractional (Fractional-N). For example, chip LMX2364, LMX2470 company National Semiconductor, IC ADF4252 of Analog Devices are dual synthesizer with two separate control loops: one with a fractional DPKG (DPKG), the other with integer DPCD. Chip ADF4001 of Analog Devices has only one integer DPCD, precision CFD and ultra-low phase noise. Indicators of synchronism are usually part of these chips on the ode CFD and are of two types: digital and analog. Digital IP works so that if three (or five) consecutive measuring cycles, the phase mismatch between pulses of two streams of pulses at the inputs CFD less than 15 NSEC, there is a synchronism in the ring IFPC and the output of a digital IC is formed level Log.1. If the phase error is greater than 25 NS in one cycle of measurement, there is no synchronism and the output of a digital IC is formed level Log.0. The logical scheme matching for the two inputs can be performed on the chip 564 LA7, D-trigger - on-a-chip 564 TM2, shaper regulatory signal at the operational amplifier AD822AR of Analog Devices, an amplifier with adjustable gain ROUX 22 on the basis of the transistor type BFR 93A Philips. As a controlled resistance in the emitter circuit of the transistor BFR 93A used field-effect transistor on the basis of which is formed adjustable emitter negative feedback. If we change the value of the resistance in the emitter circuit of the amplifier RU 22 changes its gain.

Thus, in the proposed frequency synthesizer resolved the controversial issue of simultaneously obtaining high spectral purity of the output signal and high-speed switching frequency.

This allows the use of the proposed frequency synthesizer in modern radio communication systems with fast is the jump frequency for a given program.

The frequency synthesizer containing connected in series source signal from a reference frequency, and a buffer stage, the first output of which is connected to the first input of the first frequency-phase detector, the output of which through the first low pass filter connected with the control input of the oscillator, voltage-controlled first outlet through which the first frequency divider with variable division factor is connected with the second input of the first frequency-phase detector, the second output buffer of the cascade is connected to the first input of the second frequency-phase detector, the output of which through the second low pass filter connected to the input of the storage unit and the first input of the switch from two directions, the second input which is connected to the output of the storage unit, and the output of the switch from two directions is connected with the control input of the dual-mode oscillator, a first outlet through which the second frequency divider with variable division factor is connected with the second input of the second frequency-phase detector, while the second output of the dual mode oscillator is the output of the device, as well as the key, the output of which is connected to a high frequency input dual mode oscillator, and the control unit, the input of which is the input device, the output control unit connected to control the influencers inputs of the first and second frequency divider with variable division factor, characterized in that the input of the first and second indicators matching, schema matching, D-trigger shaper regulating signal and an amplifier with an adjustable gain, and the inputs of the first and second indicators of synchronism are connected respectively to the outputs of the first and second frequency-phase detector, and the outputs of the first and second indicators of synchronism are connected respectively with the first and second inputs of the circuit matches the output of which is through E-trigger and driver of the regulatory signal is connected with the control input of the amplifier with an adjustable gain, an input connected to the second output of the generator, voltage-controlled, and the exit - entrance key, a control input connected to the output of D-flip-flop and managing input from two directions, while the output control unit is connected with the reset input of D-flip-flop.