Digital frequency synthesiser

FIELD: physics.

SUBSTANCE: digital frequency synthesiser has a reference generator, two dividers with fixed division factor, an inverting adder, an inverter, two dividers with variable division factor, three low-pass filters, two controlled generators, two frequency-phase detectors and a microcontroller, as well as a digital potentiometer (31), and a voltage follower (32), a synchronism indicator (33), a switch (34), a first (35) and a second (36) voltage comparator.

EFFECT: high resolution and wider range when forming a fine frequency grid inside a given grid while retaining high speed of operation and purity of the spectrum of the output signal.

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The invention relates to electrical engineering and can be used in the transceiver and test equipment.

Widely known digital frequency synthesizer (CSC)based on ring-pulsed phase-locked loop (IFPC) with a frequency divider with variable division factor (DPCD) in the feedback circuit (see, for example, Governors and I. Sokolov, Y. Digital frequency synthesizers radio systems. M.: "Energy", 1973).

The disadvantage of these schemes synths is that in adenocarcinom CSC with integer DPKG impossible to choose the frequency comparison F_cpvistapanel step grid frequency F_Wthat significantly limits the performance of the synthesizer when switching frequencies, especially at small step.

Also known digital frequency synthesizer (see USSR author's certificate No. 1510080 from 23.09.1989 year), based on two parallel rings IFPC with total controlled generator (UG).

In this CSC in parallel with the main (narrowband) ring-locked loop includes additional (broadband) ring-locked loop. Additional ring on the basis of the phase detector (PD) type "sample store operates at a frequency comparison of the F_CPn times longer than the specified time step, the grid frequency F_Wand in the main ring using the receiving digital frequency-phase detector (CPD) frequency comparison F _CPnot more than a specified grid spacing frequency F_W. Control signals from outputs of PD and CPD after filtering arrive at the corresponding inputs of the adder weighted summation, the output of which is formed the signal arrives at the control input UG.

The disadvantage of this CSC is that it performance is limited due to the use of different detectors: CFD and FD type "sample store.

The closest in technical essence to the present invention is dvukhkontsevoi CSC with frequency modulation for patent 85769 adopted for the prototype.

The block diagram of the device of the prototype is shown in figure 1, where we have introduced the following notation:

1 - reference generator (DG);

2 and 7, the first and the second frequency divider with a fixed division factor (DFCD);

3 and 8, the first and second frequency-phase detector (CPD);

4, 9 and 26 of the first, second and third low pass filters (LPF);

5 and 11, the first and second driven generators (UT);

6 and 12, the first and the second frequency divider with variable division factor (DPCD);

23 - microcontroller (MC);

24 - inverting adder (SUM);

25 - inverter (INV).

The device prototype contains serially connected reference generator EXHAUST gas 1, the first DFCD 2, the first CFD 3, the first low-pass filter 4, an inverting adder SUM 24, the inverter INV 25, the third is LF 26, the first controllable oscillator UG 5 and the first DPCD 6, the output of which is connected to a second input of the first CFD 3; connected in series to the second DFCD 7, the second CPD 8, the second low-pass filter 9, the second YR 11 and the second DPKG 12, the output of which is connected with the second input of the second CFD 8; in addition, the output of the second YR 11 is an output device, the output of the first LU 5 is connected to the input of the second DFCD 7, and the microcontroller MK 23, the control bus which is connected to the control inputs of the second DFCD 7, the second CPD 8, the first DPCD 6 and second DPKG 12.

Inverting adder 24 (see figure 2) is a power-adder, which contains the operational amplifier 27, the first 28 and second 29 and 30 third resistors.

The device prototype works as follows.

In CCC there are two series-connected rings IFPC. The output of the first circuit forming a frequency that is the reference for the second ring. In the second ring are synthesized output frequency CSC in a given range and with a given spacing of the grid frequency.

In the first ring IFAP at the first input of SUM 24 goes well filtered reference voltage U_FLequal to or slightly less than half of the maximum control voltage at the control input 5 UG, i.e. U_FL≤0.5 U_Panel. To the second input of SUM 24 with the output of the first CFD 3 through first the second low-pass filter 4 receives a corresponding control voltage U ₂which is formed in the process of entering into synchronism in the first ring IFPC.

While the total control voltage from the output SUM 24 through INV 25 and the third low-pass filter 26 is supplied to the control input UG 5 and is equal to a weighted sum of the control voltages from the outputs of the first low-pass filter 4 and the source of reference voltage U_FL

The weighting factor n is selected from the following considerations.

The gain of the multiple-input amplifier-adder (built on the basis of the operational amplifier 27 with grounded reinvestiruet input, see figure 2) is determined for each of the j input as

where R_octhe resistance of the feedback operational amplifier,

R_jthe resistance of the corresponding resistor.

Using resistors included in the input circuit of amplifier-adder, you can implement the weighting coefficients for each of the components of stress, if we accept that the first resistor 28 is equal to the third resistor 30 (feedback), and the second resistor 29 is equal to R₂=n R₁,

where R₂the resistance of the second resistor 29,

R₁- resistance of the first resistor 28.

Each value of the total control voltage U_Σthe control input 5 UG corresponds to a certain frequency at its output.

The EU is to choose the frequency of the reference pulses (i.e. the frequency comparison F_cpin the first ring n times longer than the specified time step, the fine grid frequency when switching the division factor of the first DPCD 6 per unit voltage at the output CFD 3 will be n times greater than in the case if the frequency comparison was equal step fine grid frequency. Then after the first period of regulation in the first ring control output voltage CFD 3 will change to the value of ΔU₂=nΔU₁where ΔU₁- change the control voltage that is output CPD 3, if the frequency comparison would be equal small step grid frequency. Then after the first period of regulation total control voltage UG 5 will be equal to

i.e. change the value of ΔU₁as required for a given small increment of frequency Δf (step fine grid frequency).

In other words, how many times have increased the frequency comparison F_cpin the first ring (i.e. n times), as many times increased control voltage U₂after the first low-pass filter 4 by switching the division ratio of the first DPCD 6 per unit. While at the same time decreased the voltage after inverting adder SUMS 24 as part of the total control voltage, which through INV 25 and the fourth low-pass filter 26 is supplied to the control input 5 UG. The third LPF 26 red is dim for additional filtering of the total control voltage.

Here the fixed voltage U_FLplays the role of a "stand"against which there is a change in the control voltage with a small step that leads to more fine-tuning of the nominal value of the output frequency of 5 UG.

Thus, in the first ring IFPC obtained gain in performance due to the fact that the tuning control voltage is n times more often than if the frequency comparison F_cpwas equal to the frequency of small step. At the same time adjusting the output frequency of the first ring is fine-pitch in the vicinity of its nominal value. In addition, since the output of the inverting adder SUM 24 control voltage decreases n times n times reduced level of interference with the frequency comparison output CFD 4. This makes it possible to reduce the filtering on the output of the first LPF 4 and thereby further improve performance.

Output 5 UG reference frequency is fed to the input of the second DFCD 7 for forming the reference frequency comparison in the second ring CSC. As a result, the output of the second YR 11 are formed output frequency CSC in a given range and with a given spacing of the grid frequency, minimal frequency shift within a given grid.

The drawbacks of the prototype are as follows.

In the synthesizer prototype because of the need for the STI to have a fine tuning step frequency in the first ring turns a small range of overlap on the control voltage at the input 5 UG. For example, if you take the weight ratio of n=20 and the maximum differential control voltage at the output CFD 3 ΔU_CFD≤10 V, the maximum range of the control input voltage UG is ΔU_UG=10V:20=0.5 V or together with constant voltage U_FLthe total control voltage at the control input 5 UG will ΔU_UG=U_FLto +0.5 C. the minimum tuning step at the output of the first circuit when the frequency comparison F_CP=12.5 kHz and n=20 is F_W=12.5 kHz:20=of 0.625 kHz, and for n=100 the minimum step will be F_W=12.5 kHz:100=0,125 kHz. From these comparisons it can be seen that the larger n, the more resolution in frequency (i.e. smaller step) and the smaller the range of the control voltage at the input 5 UG. With a very small range of overlap and adverse working conditions CSC ring IFPC can be out of synchronism. To avoid this, you need to increase the range of the control voltage at the input 5 UG. But in this case, the resolution in frequency will be insufficient, i.e. to obtain the necessary small step will be difficult.

The task that sent the proposed device is a device with a higher resolution in frequency, with a simultaneous increase in range overlap in h is the frequency.

To solve the problem in a digital frequency synthesizer containing serially connected reference oscillator, a first frequency divider with a fixed division ratio of the first frequency-phase detector, the first low pass filter, an inverting adder, inverter, a third low pass filter, the first controllable oscillator and the first frequency divider with a variable division ratio, the output of which is connected to a second input of the first frequency-phase detector, connected in series, the second frequency divider with a fixed division ratio of second frequency-phase detector, a second lowpass filter, the second controllable oscillator and the second frequency divider with variable division factor whose output is connected to the second input of the second frequency-phase detector, the output of the second controlled oscillator is the output device, the output of the first controlled oscillator connected to the input of the second frequency divider with a fixed division ratio, and the microcontroller, the output of which is the control bus connected to the control inputs of the second frequency divider with a fixed division ratio of second frequency-phase detector, the first and second frequency divider with variable division factor, according to the invention centuries is found consistently connected digital potentiometer and the voltage follower, the output of which is connected with the second inverting input of the adder, and connected in series indicator of synchronism and the key, the output of which is connected to the inputs of the first and second Comparators whose outputs are connected to respective inputs of the microcontroller, the output of which is the control bus is connected with the control input of the digital potentiometer, signal input which is the input reference voltage, in addition, the input indicator of synchronism is connected with the second output of the first frequency-phase detector signal input key is connected to the output of the first lowpass filter.

The block diagram of the proposed device is shown in figure 3, where we have introduced the following notation:

1 - reference generator (DG);

2 and 7, the first and the second frequency divider with a fixed division factor (DFCD);

3 and 8, the first and second frequency-phase detector (CPD);

4, 9 and 26 of the first, second and third low pass filters (LPF);

5 and 11, the first and second driven generators (UG);

6 and 12, the first and the second frequency divider with variable division factor (DPCD);

23 - microcontroller (MC);

24 - inverting adder (SUM);

25 - inverter (INV);

31 is a digital potentiometer (CPU);

32 is a voltage follower (MO);

33 indicator of synchronism (IP);

34 - key (KL);

35 - the first Communist is tor (Ohms);

36 - second comparator (Com).

The proposed device comprises a first ring IFPC on the basis of series-connected: OG 1, the first DFCD 2, the first CFD 3, the first low-pass filter 4, the SUM OF 24, INV 25, the third low-pass filter 26, the first ANGLE 5 and the first DPCD 6, the output of which is connected to a second input of the first CFD 3; the second ring IFPC on the basis of series-connected: the second DFCD 7, the second CPD 8, the second low-pass filter 9, the second YR 11 and the second DPKG 12, the output of which is connected with the second input of the second CPD 8, and connected in series CPU 31 and MON 32, the output of which is connected with the second input SOUM 24, connected in series indicator synchronism IP 33 CL 34, the output of which is connected to the inputs of the first Kom 35, the second Kω 36 whose outputs are connected to respective inputs of the microcontroller MK 23, the output of which is the control bus connected to the control inputs of the second DFCD 7, the second CPD 8, the first DPCD 6, the second DPKG 12 and the CPU 31. Thus the output of the first LU 5 is connected to the input of the second DFCD 7, and the output of the second YR 11 is an output device. The entrance of the CPU 31 is the input reference voltage U_FL. Input IP 33 is connected with the second output of the first CFD 3. Signal input CL 34 is connected with the second output of the first low-pass filter.

The control bus output MK 23 is a standard three-wire interface where the three wires come in p is coherent pulse code signals: 1) clock pulses (TI); 2) information signal (INF); 3) pulse recording resolution (OF) the information transmitted in each of the blocks: DPKG 12, DPCD 6, CPD 8, DFCD 7, the CPU 31. And for all units common wires are TI and DETAILS, and the momentum resolution of passing information supplied by each individual wire in each managed unit.

Inverting adder SUM 24 (see figure 2) is identical to the SUM of 24 in the prototype and contains operational amplifier 27, the first 28 and second 29 and 30 third resistors.

Digital potentiometer CPU 31 on a single chip AD8400 of Analog Devices is a (see figure 4) device for decoding an input data expressed in binary code, corresponding values of the resistors in the output. Digital potentiometer chip AD8400 can be performed in the equipment of different functions, including the function of a conventional variable resistance or potentiometer, the output of which you can get 256 discrete values of voltages from a single reference source U_FL. Nominal values of the resistance circuits AD8400 can be 1 kω, 10 kω, 50 kω and 100 kω. The output of the CPU 31 can be set to 256 programmable discrete values of nominal resistance. This output variable resistance R_CPUdigital potentiometer can be in this case a part of the input impedance operational is silicula (figure 2), on the basis of which the adder weighted summation. Because the gain of the operational amplifier (op-amp) can be represented as follows

where R₁- resistance to the first input of the adder,

R_CPU- AC resistance of the digital potentiometer.

From (4) it is seen that changing R_CPUthe output of the CPU changes the gain of the shelter and is broken in this case, the correct operation of the adder weighted summation. To avoid this, after the CPU 31 is enabled the voltage follower MO 32 with a very high input impedance and very low stable output resistance R_MO<<R₁. In this regard, R_MOyou need to take into account the gain of the shelter can be represented, as before, the expression

The voltage follower MO 32 can be made on the basis of an emitter follower or on the basis of the operational amplifier.

The proposed device operates as follows.

In the proposed CSC there are two series-connected rings IFPC. The output of the first circuit forming a frequency that is the reference for the second ring. With this frequency, if necessary, may have a fixed offset in the vicinity of the nominal znacheniya the second ring are synthesized output frequency CSC in a given range and with a given spacing of the grid frequency, and within this step, you can get the offset from the nominal frequency with a small step.

To do this in the first ring IFAP at the first input of the inverting adder SUM 24 connected in series through the CPU 31 and MO 32 receives 256 switchable discrete equal and stable gradation reference voltage, i.e. a variable reference voltage can be changed from U_{LANEEB 1}=U_FL/256 to U_{LANETHIS 256}=U_FLincrements (gradation) m. To the second input of SUM 24 with the output of the first low-pass filter 4 receives a corresponding control voltage U₂which is formed in the process of entering into synchronism in the first ring IFPC.

While the total control voltage U_Σoutput SUM 24 through INV 25 and the third low-pass filter 26 is supplied to the control input UG 5 and is equal to a weighted sum of the control voltages from the outputs of the first low-pass filter 4 and a variable reference voltage output MO 32

The weighting factor n in inverting the adder SUMS 24, which is a weighted summation of the two input signals is selected as described in the prototype.

Here the alternating voltage U_FL/m plays the role of a "stand"against which there is a change in the control voltage in the first ring IFPC small step that leads to more subtle is Odstrani nominal output frequency 5 UG.

At the beginning of the control signal from the MK 23 is set to the voltage "stand" in the middle of the U_FLand is equal to U_FL/128, and the control input of the first 5 UG after the third low-pass filter 26 receives the total control voltage

In this case, is formed by the nominal value of the frequency at the output 5 UG. At the same time at the output of IP 33 a signal of the presence of synchronism in the first ring IFPC level "Log.1", which is supplied to the control input of the CL 34 and allows the mode of synchronism passing through CL 34 of the output signal of the first low-pass filter 4 to the inputs of the first Kom 35 and second 36 Kω. On both of the comparator receives the same signal. First Kω 35 compares the input signal with the reference voltage U_{OP TOP}so that it will be "Log.1"when the input signal exceeds U_{OP TOP}. Second Kω 36 included inverted compares the input signal with the reference voltage U_{OP MIN}so that it will be "Log.1"when the input signal is less than U_{OP MIN}. In other words, the scheme with two Comparators are able to feel the moment when the input signal goes out of the predetermined permissible range (working window). When the input signal is in the permissible range, the outputs of the first Kom 35 and second 36 Kω signals are "Log.0". The signal "Log.0" o the Yes first Kω 35 is supplied to the first input of the MK 23, and the signal "Log.0" with the release of the first Kom 36 is supplied to the second input of MK 23. When both inputs MK 23 receives signals from the level "Log.0", this means that the control voltage U₂from the output of the first low-pass filter 4 is in the permissible range and the upper limit U_{OP TOP}and lower limit U_{OP MIN}control voltages after the first low-pass filter 4 is still installed stock.

If there is a need to separate from the nominal frequency in the first ring on a certain discrete value by a corresponding change in division ratio in the first DPCD 6, the control voltage at the output of the first low-pass filter 4 will change accordingly from the nominal value while maintaining the same voltage values stand U_FL/128. If you continue to adjust the frequency of 5 UG voltage from the first input of the LPF 4 is greater than U_{OP TOP}or less U_{OP MIN}at the output of the corresponding comparator, a signal will appear "Log.1" and will appear in your log MK 23. As a result, the output MK 23 on the management bus signal in binary code on the control input, the CPU 31 from which the CPU 31 switches one step voltage (gradation) up or down from the nominal value. Already with this new "stand" ring IFPC will quickly adapt and you will be able to sync the mechanism on the new frequency, rebuilt from the nominal.

Therefore, using these automatically switchable "stand" can continue to build up in frequency from the nominal value up or down, i.e. the tuning range of frequencies with a fine grid in the first ring expands significantly.

One discrete gradation "stand" value must be less than the maximum overlap on the control voltage U₂/n on input UG 5 of the first ring IFPC.

From the total control voltage U_Σis formed at the output of the first 5 UG frequency, which as a reference is supplied to the second ring on the input of the second DFCD 7. In the second ring on the signals from the MK 23 on the control bus to control inputs of the second DFCD 7, the second CFD 8 and the second DPKG 12, the output of LU 11 are formed is output from the frequency synthesizer in a given range with a given step, with the possibility of fine tuning within a given step in a wide range. In the transition mode, the current output of the second CFD 8 increases sharply by control signals from the MK 23, to improve performance when switching frequencies. Mode matching current CFD 8 again is reduced to a minimum for improved sideband suppression in the output signal CSC.

The ability of the proposed device is determined by the fact that the led of the blocks of the model and can be performed on the well known circuits. Digital synthesizers running on ICS CSC with IFPC different companies. At the same time in a single chip can be one or two independent CSC with integer DPKG (Integer-N or fractional (Fractional-N). For example, chip LMX2364, LMX 2470 company National Semiconductor represent a double synthesizer with two separate control loops: one with a fractional DPKG (DPKG), the other is normal. Similarly, chip ADF4252, ADF4001 of Analog Devices and others. Indicators of synchronism IP are usually part of these circuits, and the output signal of the IP generated from the information received from the second output CFD. These IP are of two types: digital and analog. Digital IP works so that if three (or five) consecutive measuring cycles, the phase mismatch between pulses of two streams of pulses at the inputs CFD less than 15 NSEC, there is a synchronism in the ring PLL and the output of a digital IC is formed level Log.1. If the phase error is greater than 25 NS in one cycle of measurement, there is no synchronism, and the output of a digital IC is formed level Log.0. As an inverting adder and inverter can be used in low-noise operational amplifiers, for example, type PR 27 Analog Devices. Digital potentiometer can be performed on the chip AD8400 Analog Devices. The voltage follower can be made on the basis of few who mashego emitter follower or on the basis of the voltage follower operational amplifier type PR 27 Analog Devices. The voltage Comparators can be performed, for example, in the domestic chip 521 SO. The key device can be performed on the chip MS IN company Motorolla. As the microcontroller MC 23 can be used chip C8051F220 company Silicon Laboratories (CYGNAL).

Thus, in the proposed CSC adjustment range of frequencies with a fine grid in the first ring expands significantly due to the fact that many strains of "coasters" automatically switches over a wide range, which also increases the reliability of synchronization.

In addition, due to the high frequency of the comparison in the first ring, which is formed without the use of fractional DPCD with known interference fragmentation, there is a possibility to get a higher spectral purity of the output signal while maintaining high performance.

Digital frequency synthesizer containing serially connected reference oscillator, a first frequency divider with a fixed division ratio of the first frequency-phase detector, the first low pass filter, an inverting adder, inverter, a third low pass filter, the first controllable oscillator and the first frequency divider with a variable division ratio, the output of which is connected to a second input of the first frequency-phase detector, connected in series, the second divider is often the s with a fixed division ratio, the second frequency-phase detector, a second lowpass filter, the second controllable oscillator and the second frequency divider with a variable division ratio, the output of which is connected with the second input of the second frequency-phase detector, the output of the second controlled oscillator is the output device, the output of the first controlled oscillator connected to the input of the second frequency divider with a fixed division ratio, and the microcontroller, the output of which is the control bus connected to the control inputs of the second frequency divider with a fixed division ratio of second frequency-phase detector, the first and second frequency divider with variable division factor, wherein entered serially connected digital potentiometer and the voltage follower, the output of which is connected with the second inverting input of the adder, and connected in series indicator of synchronism and the key, the output of which is connected to the inputs of the first and second Comparators whose outputs are connected to respective inputs of the microcontroller, the output of which is the control bus is connected with the control input of the digital potentiometer, signal input which is the input reference voltage, in addition, the input indicator of synchronism is connected with the second output is the I can pay tithing frequency-phase detector, signal input key is connected to the output of the first lowpass filter.