Digital quadrature-output computing synthesizer |
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IPC classes for russian patent Digital quadrature-output computing synthesizer (RU 2294054):
            
 Digital computing synthesizer / 2286645
Digital computing synthesizer contains standard generator, delay block, digital accumulator, digital-analog converter, low frequencies filter, band filter, permanent memory block, divider with variable division coefficient, waiting multi-vibrator, two memory registers, reverse frequency counter, impulse generator, codes transformer and device for displaying frequency of output signal.
 Digital signals synthesizer / 2257669
Device has standard support generator, delay block, first memory register, first digital accumulator, second digital accumulator, third digital accumulator, codes converter, analog-digital converter, low frequency filter, second memory register, divider with variable division coefficient, delay multi-vibrator.
 Digital signal synthesizer / 2250560
Proposed digital signal synthesizer has first and second delay circuits, low-pass filter, and three parallel channels, each incorporating pulse counter, memory unit, digital-to-analog converter, analog switch, analog adder, and delay circuit.
Digital signal synthesizer / 2250560
Proposed digital signal synthesizer has first and second delay circuits, low-pass filter, and three parallel channels, each incorporating pulse counter, memory unit, digital-to-analog converter, analog switch, analog adder, and delay circuit.
Digital signals synthesizer / 2257669
Device has standard support generator, delay block, first memory register, first digital accumulator, second digital accumulator, third digital accumulator, codes converter, analog-digital converter, low frequency filter, second memory register, divider with variable division coefficient, delay multi-vibrator.
Digital computing synthesizer / 2286645
Digital computing synthesizer contains standard generator, delay block, digital accumulator, digital-analog converter, low frequencies filter, band filter, permanent memory block, divider with variable division coefficient, waiting multi-vibrator, two memory registers, reverse frequency counter, impulse generator, codes transformer and device for displaying frequency of output signal.
 Digital quadrature-output computing synthesizer / 2294054
Proposed device has standard generator, delay unit, two memory registers, two digital storage devices, variable-ratio divider, two code converters, two digital-to-analog converters, two low-pass filters, and inverter.
 Frequency synthesizer / 2329594
Invention is referred to radio communication and may be used in radio receiving and radio transmitting devices for radio signal generation, modulation and frequency conversion. Synthesizer includes signal source of reference frequency, two frequency and phase detectors, control unit, two dividers with variable division factor, two low-frequency filters, voltage controlled generator, buffer amplifier, storage unit, switch from two directions, two-mode auto generator, alignment plug and temporary interval unit.
 Frequency synthesizer / 2329595
Invention is referred to radio communication and may be used in radio receiving and radio transmitting devices for radio signal generation, modulation and frequency conversion. Synthesizer includes signal source of reference frequency, frequency and phase detector, control unit, divider with variable division factor, two low-frequency filters, voltage controlled generator, direct current amplifier, interfacing circuit, two-mode auto generator.
 Frequency synthesizer with acoustic circuit of adaptive frequency and phase auto tuning / 2329596
Invention may be used for generation of stable frequency network with even interval in receiving and transmitting devices and is notable for short tuning time within broad range of operating frequencies. Device includes controlled generator, frequency divider with variable division factor, frequency and phase detector, reference generator, frequency divider with fixed division factor, controlled charging unit, trapping-by-phase rating unit, microcontroller, trapping-by-frequency rating unit and low-frequency filter consisting of two capacitors, two resistors and two switches.
 Time-and-frequency synchronisation device / 2341892
Proposed device comprises a reference generator, two variable-ratio dividers, a phase detector, control generator, two digital-to-analogue converters, computer, mode selection unit, device for determining temporary position of the input pulse, index zone generator and a frequency divider.
 Digital synthesiser of frequency and phase modulated signals / 2358384
Present invention pertains to electronics and computer technology, meant for synthesising frequency and phase modulated signals and can be used in radar, navigation and adaptive communication systems. The digital synthesiser of frequency modulated and phase modulated signals contains a reference generator, delay unit, first memory register, first digital accumulator, second memory register, second digital accumulator, adder, code converter, digital-to-analogue converter, low pass filter, third memory register, frequency divider with varying division factor, fourth memory register and a third digital accumulator.
 Frequency synthesiser / 2394367
Frequency synthesiser includes two frequency phase detectors, two low-pass filters, voltage-controlled generator, two dividers with variable division factor, buffer cascade, two synchronism indicators, coincidence circuit, D flip-flop, shaper of control signal and amplifier with controlled amplification factor, two-mode self-oscillator, control unit, key, switch from two directions, storage unit and signal source of reference frequency.
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FIELD: computer and radio engineering; radar, navigation, and adaptive communication systems. SUBSTANCE: proposed device has standard generator, delay unit, two memory registers, two digital storage devices, variable-ratio divider, two code converters, two digital-to-analog converters, two low-pass filters, and inverter. EFFECT: ability of synthesizing frequency-modulated quadrature signals. 1 cl, 3 dwg
The invention relates to electronic computing and engineering is intended for the synthesis of coherent quadrature frequency-modulated signals and can be used in radar, navigation systems and adaptive communication systems. Known digital frequency synthesizers containing a generator of clock pulses, the delay block, two blocks of constant memory, preset counters, two memory registers, two digital drive, the code Converter, digital to analog Converter, a low pass filter and pulse shaper [1]. The closest technical solution (prototype) to the proposed digital frequency synthesizer containing serially connected clock and the delay unit, connected in series, the first block of continuous memory and preset counters, connected in series, the second block of continuous memory, the second register memory, the second digital memory, the first memory register, the first digital storage device, the code Converter, digital to analog Converter, a low pass filter whose output is the output of a digital frequency synthesizer, and the inputs are the address inputs of the first and second blocks of constant memory [2]. However, famous in the x digital frequency synthesizers, there is no possibility of obtaining coherent quadrature signals. The invention allows to extend the functionality of the digital synthesizer, and gives you the ability to synthesize coherent quadrature frequency-modulated signals. The positive effect of providing opportunities for the synthesis of coherent quadrature frequency-modulated signals is achieved by the fact that in digital computing synthesizer containing serially connected reference generator and the delay unit; two memory register; two digital drive; a divider with variable division factor; connected in series to the second digital storage device, the first code Converter, the first digital to analog Converter and the first low pass filter whose output is an analog output of the device; the outputs of the delay block is connected to a clock input of the divider with a variable division ratio of the second digital memory and the first digital-to-analog Converter; the output of the divider with variable division factor connected to the input of the serial transfer of the first digital drive, and the new is that in digital computing synthesizer entered inverter connected in series with the second code Converter, the second digital to analog Converter, a second low pass filter whose output is W is the ring analog output digital synthesizer and its inputs are the inputs of the first and second memory registers; the output of the first memory register connected to the input of the first digital drive, the yield of the latter is connected to the input of the second digital drive, senior output discharge which is connected to the control input of the first inversion of the code Converter and the inverter, the output of which is connected to the control input of the inversion of the second code Converter; the output of the second memory register connected to the input of the divider with variable division factor; the output of the second digital memory connected to the input of the second code Converter; the output of the delay block is connected to the clock input of the second d / a Converter. In figure 1 the block diagram of digital computer synthesizer, figure 2 - graphs of the output signals DCS. Digital synthesizer (figure 1) contains a reference (reference) generator 1, the delay unit 2, the first memory register 3, the first digital memory 4, the second digital memory 5, the first code Converter 6, the first d / a Converter 7, the first low pass filter 8, a second memory register 9, the divider with a variable division ratio of 10, an inverter 11, a second code Converter 12, the second d / a Converter 13, a second low pass filter 14. Digital is th computing synthesizer operates as follows. The input of the first memory register 3 receives the code start frequencyiand at the input of the second memory register 9 code Dkthat defines the division factor of the divider 10 and the rate of change of frequency of the digital computer synthesizer. The reference generator 1 outputs a signal of the reference frequency sine wave which is fed to the input of the delay block 2 forming spaced in time sequence of rectangular pulses of the form "meander", which is fed to the input of the divider with a variable division ratio of 10, the inputs of the first and second digital drives 4 and 5, the inputs of the first and second digital to analog converters 7 and 13, and serve to synchronize the operation of the digital computer keyboard. With the first clock pulse at time t1(2) code start frequencyifrom the first memory register 3 is written in the first digital memory 4, and code division ratio of Dkfrom the second memory register 9 is recorded in the divider with a variable division ratio of 10. Then with each clock pulse code And the output of the first digital drive 4 will change as follows:
This code And fed to the input of the second digital memory 5, the summation of which will vary according to the formula: Senior category code amount SSGNis iconic and is supplied to the control input of the inversion of the first code Converter 6 and to the input of the inverter 11. With the inverter output signal SSGNis fed to the input of the second code Converter 12, the rest of the N high-order bits (where N - bit DAC) through the first and second converters codes 6 and 12 is supplied to the information inputs of the first and second DAC 7 and 13, respectively. If SSGN=0, the first DAC 7 comes straight binary code amount, and the second DAC 13 - reverse binary code amount. If SSGN=1, the first DAC 7 is fed back code amount, and the second DAC 13 - direct code amount. On the DAC outputs 7 and 13 are formed stepwise signals "triangular" shape shifted in phase by 180°. The low pass filters 8 and 14 have the cutoff frequency fcp<fm/2, where fm- clock frequency. Thus, the low pass filters 8 and 14 pass only the first harmonic of the synthesized signals. If we accept that ω0=Ci- primary circular frequency; 0.5 ω`=1/Dk- the rate of change of cyclic frequencies; Δt=T - the duration of the clock interval, then the outputs of the LPF 8 and 14 will be the chirp signals, the amplitude of which varies according to the formula:
where Umthe amplitude of the signal. Thus, in the digital computer keyboard are formed two coherent quadrature chirp signal. Literature 1. Patent No. 2149503 of the Russian Federation, MKI N 03 In 19/00, the Digital frequency synthesizer / Ryabov I. Ryabov, VI - Appl. 13.04.1999. Publ. 20.05.2000. Bull. No. 14. 2. Patent No. 2058659 of the Russian Federation, MKI N 03 In 19/00, the Digital frequency synthesizer / Ryabov I., fishchenko P.A. - Appl. 23.09.1993. Publ. 20.04.1996 bull. No. 11 (prototype). Digital synthesizer with quadrature outputs containing serially connected reference generator and the delay unit; two memory register; digital drive; a divider with variable division factor; connected in series to the second digital storage device, the first code Converter, the first digital to analog Converter and the first low pass filter whose output is an analog output of the device; the outputs of the delay block is connected to a clock input of the divider with a variable division ratio of the second digital memory and the first digital to analog Converter; the output of the divider with variable division factor connected to the input of the serial transfer of the first digital memory, wherein the digital computing synthesizer put the inverter; the latter is therefore United the second code Converter, the second digital to analog Converter, a second low pass filter whose output is the second analog output digital synthesizer, and its inputs are the inputs of the first and second memory registers; the output of the first memory register connected to the input of the first digital drive, the yield of the latter is connected to the input of the second digital drive, senior output discharge which is connected to the control input of the first inversion of the code Converter and the inverter, the output of which is connected to the control input of the inversion of the second code Converter; the output of the second memory register connected to the input of the divider with variable division factor; the output of the second digital memory connected to the input of the second Converter codes; the output of the delay block is connected to the clock input of the second d / a Converter.
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