Frequency synthesizer

FIELD: radio engineering.

SUBSTANCE: invention is referred to radio communication and may be used in radio receiving and radio transmitting devices for radio signal generation, modulation and frequency conversion. Synthesizer includes signal source of reference frequency, two frequency and phase detectors, control unit, two dividers with variable division factor, two low-frequency filters, voltage controlled generator, buffer amplifier, storage unit, switch from two directions, two-mode auto generator, alignment plug and temporary interval unit.

EFFECT: decrease of noise level in output signal.

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The present invention relates to radio communications and can be used in receiving and transmitting devices designed to generate radio signals, modulation and frequency conversion.

For transmission and reception of signals are used generators of sinusoidal oscillations, the basic requirements which are frequency stability and spectral purity of the output signal, in suppressing it includes the parasitic oscillations of different types.

Frequency synthesizers based on phase lock loop (PLL), is widely known in the technical literature[1], [2], [3], [4] and other Synths allow you to obtain a sinusoidal oscillation with a given frequency step, and the frequency stability is determined by a precision quartz oscillator. However, frequency synthesizers based on phase lock loop frequency, are part of the output voltage of a significant amount of side components and noise of various types.

Functional diagram synths two types shown in RIS str in the book [1].

In the first synthesizer at the first input of the frequency-phase detector (CPD) connects the reference generator (more precisely after the divider by 4), and to the second input CFD - output voltage from generator voltage-controlled (VCO). Output CFD through a lowpass filter (LPF) control the em frequency of the VCO so she takes a value that is exactly equal to the reference oscillator frequency multiplied by the division factor of the divider with variable division factor (DPCD). The second synthesizer differs only in that the reference oscillation therein is formed of harmonic oscillations of the reference oscillator, which is fed to the first input CFD, and to the second input CFD served harmonic voltage to the VCO. Output CFD through the low-pass filter controls the frequency of the VCO in such a way that it accepts a value that is exactly equal to the frequency of harmonic oscillations, generated from the oscillations of the reference oscillator. Both of these frequency synthesizer represent a static system of automatic regulation. It is known that the ring of such a system is the integrator. Implemented integrator, as a low-pass filter with transfer factor (1+f/f_CF), where f_CFthe cutoff frequency of LPF. LPF constant component of the error and filter (suppresses) the output voltage with the frequency of the reference oscillator, with the frequency of the VCO, the last division in DPKG, and various parasitic interferences and noises. Fundamentally impossible to improve filtering, applying a low-pass filter of a higher order, for example with ratio (1+f/f_CF)². For this reason, noise filtering and various interference arising DPCD and CFD, according to the law (1+f/f_CFand, therefore, granichen.

In the book [4]. their level defined in the region of 100 dB in the frequency band 10 Hz or 75 dB in the frequency range 3 kHz. Ibid, p.87 the dependences of the "noise"caused by the phase-locked loop circuit is, which shows that at offset 10 kHz from the synthesized frequency attenuation "noise" is (90-110) dB in the band of 1 Hz, and band 3 kHz (55-75) dB. In [3] only the level of suppression of separation is evaluated in (80-120) dB. Similar figures are found in many other sources.

This suppression of noise and interference in the output voltage of the synthesizer to the current conditions of loading frequency is insufficient.

In the literature [4] it is shown that the noise oscillator, not covered by the ring PLL (VCO special case of the oscillator), is much smaller. According to p.85 they are (155-161) dB. In the literature [6] and [7] analyzed the nature of noise oscillators and their dependence on various factors, attenuation of the noise in the composition of the output voltage of the oscillator. As can be seen from these data, the resulting suppression of noise in oscillators on (20-30 dB more than in the synths. However, the oscillators do not have the required stability of the output frequency, comparable to the stability of synthesizers. With the exception of quartz oscillators, but they are virtually rebuilt in frequency. So what Braz, the oscillators are not an alternative to frequency synthesizers.

Therefore, the known frequency synthesizers are inefficient in terms of suppression of the "noise" in the output voltage.

The closest in technical essence to the proposed device can be considered as a frequency synthesizer with a digital PLL shown in (figure 1.15) p.33 in [2], adopted for the prototype, with a few clarifications: "the source of the reference signal frequency is designated as a block and not the arrow, the updated name "phase detector" on "frequency-phase detector and control circuit" on the "control unit".

Functional diagram of the device of the prototype is presented in figure 1, where we have introduced the following notation:

1 - source signal from a reference frequency (ISAC);

2 - frequency-phase detector (CPD);

3 - the control unit (cu);

4 - divider with variable division factor (DPCD);

5 - lowpass filter (LPF);

6 is a voltage controlled oscillator (VCO).

The device prototype contains connected in series source signal from a reference frequency (ISAC) 1, the frequency-phase detector (CPD) 2 and a lowpass filter (LPF) 5, the output of which is connected with the control input of the oscillator, voltage-controlled (VCO) 6, a second output which is the output of the device, and the first output of the VCO 6 through the divider with a variable coeff what they fission (DPCD) 4 is connected with the second input CPD 2, control input DPKG 4 is connected to the output of the control unit (BU) 3, the entrance of which is a control input device.

The device prototype works as follows.

Output voltage ISEC 1 is supplied to the first input CPD 2, the second input is through DPCD 4 is fed the output voltage of the VCO 6. Will be understood DPCD not only the digital unit of the frequency division, and any block that provides a conversion, frequency conversion VCO to the frequency of the comparison to the reference frequency. The error signal from the output CFD 2 through the low-pass filter 5 is fed to the control input of the VCO 6, the frequency of which changes up until divided in a given number of times in DPCD 4, it will not be equal to the frequency ISAC 1. In this case, the output voltage at the output CFD 2 will cease to change, and the output frequency of the VCO 6 will be equal to the frequency ISAC 1, multiplied by the division factor DPKG 4. Thus, a ring PLL. And output BU 3 control input DPKG 4 signal that establishes the desired division ratio, i.e. the output frequency of the device. Consequently, at the output device, the second output of the VCO 6 - will be sustained oscillation at a given frequency and the second output is the output of the device, i.e. it is connected to an external load.

Given the above, a drawback of the prototype is weak the nd filter "noise" in the output.

To eliminate this drawback in the frequency synthesizer containing a source signal from a reference frequency, the control unit, the inlet of which is a control input device, connected in series, the first frequency-phase detector, the first low pass filter, a voltage controlled oscillator and the first divider with a variable division ratio, the output of which is connected to a second input of the first frequency-phase detector and the control input of the first divider with variable division factor is connected to the output of the control unit according to the invention introduced a buffer stage, the unit time intervals, connected in series voltage divider, key, dual-mode oscillator, the second divider with a variable the division ratio of second frequency-phase detector, a second lowpass filter, a storage unit and the switch from two directions, with the output of a source signal from a reference frequency connected to the input buffer of the cascade, the first and second outputs of which are connected with the first inputs respectively of the first and second frequency-phase detector, the second output of the generator, voltage controlled, is connected to the input of the voltage divider, in addition, the output of the second lowpass filter connected to the first input of the switch from two directions, exit to the th is connected with the control input of the dual-mode oscillator, the second output which is the output device, the output control unit connected with the control input of the second divider with a variable division ratio, and through the block of time intervals with control inputs switch from two directions and key.

Functional diagram of the device is presented in figure 2, where we have introduced the following notation:

1 - source signal from a reference frequency (ISAC);

2 and 9, the first and second frequency-phase detector (CPD);

3 - the control unit (cu);

4 and 10, the first and second divider with variable division factor (DPCD);

5 and 8, the first and second low pass filters (LPF);

6 is a voltage controlled oscillator (VCO);

7 - buffer cascade (Bq);

11 - memory block (ZB);

12 - switch from two directions (PD);

13 - dual mode oscillator (YES);

14 - key;

15 is a voltage divider (NAM);

16 - unit time intervals (BVI).

The proposed device has connected in series source signal from a reference frequency (ISAC) 1 and buffer cascade (BC) 7, the first output of which is connected to the first input of the first frequency-phase detector (CPD) 2, the output of which through the first low pass filter (LPF) 5 is connected with the control input of the oscillator, voltage-controlled (VCO) 6, a first outlet through which the first share is ü with variable division factor (DPCD) 4 is connected to a second input of the first CFD 2.

The second output Bq 7 is connected to the first input of the second CPD 9, the output of which through the second low-pass filter 8 is connected to the input storage block (ZB) 11 and the first input of the switch from two directions (PD) 12, a second input connected to the output of the CG 11, and the output of the PD 12 is connected with the control input of the dual-mode oscillator (YES) 13, a first outlet through which the second DPKG 10 is connected with the second input of the second CFD 9.

The second output of the VCO 6 connected in series through a voltage divider (DN) 15 and the key 14 is connected with a radio frequency (RF) input YES 13, a second output which is the output device.

Managing input device is the input of the control unit (BU) 3, the output of which is connected to control inputs of the first DPCD 4, the second DPKG 10 and the input of unit time intervals (BVI) 16, the output of which is connected with the control inputs of the PD 12 and the key 14.

The proposed device operates as follows.

The management team for inclusion is fed to the input BU 3, the output of which is the command to establish asked (the same, for example equal to N) of the division ratio of the first 4 and the second 10 DPCD. The signal from the first output of the VCO 6 through the first DPCD 4 and the signal from the first output YES 13 through the second DPKG 10 are, respectively, the second inputs of the first CFD 2 and the second CPD 9, the input of which the signal from ISAC 1 after division in BK 7, with his first and second outputs, respectively. BK 7 is applied to eliminate the mutual influence of blocks 1, 2 and 9.

In addition, the management team for inclusion through BU 3 served on BVI 16, which generates a signal of duration T_Cto control the PD 12 and the key 14. BVI 16 may be performed, for example, on the chip ADM696, which is negative edge produces a pulse with a predetermined duration. Negative slope is the end of the first pulse in the pulse sequence control command with BU 3. This command DD 12 connects the output of the second low-pass filter 8 with a control input YES 13 at time T_Cand at the same time unlocks the key 14.

The output voltage from the first CFD 2 through the first low-pass filter 5 is fed to the control input of the VCO 6, that after some time T_Censures receiving the outputs of the VCO 6 frequency exactly equal to the reference frequency multiplied by N is the division ratio of the first DPCD 4. Thus works the first ring PATCH.

At the same time, the output voltage from the second CFD 9 through the second low-pass filter 8 and the PD 12, closed on command from BVI 16, is fed to the control input YES 13. The voltage on the control input YES 13 after some time T_Cprovides reception outputs YES 13 frequency exactly equal to the reference frequency multiplied by N - factor case the Oia second DPKG 10. Thus, simultaneously with the first, work second, additional ring PLL. At the same time, the low-frequency voltage output from the second LPF 8 is stored in the CG 11.

Therefore, during a given time interval T_Cnecessary to establish the frequency of the actuation ring phase-locked loop), at the outputs of VCO 6 and may 13 is formed by a frequency equal to the reference multiplied by the division factor N.

After a period of time T_Ccommand output BVI 16 is changed, and the key 14 is closed, and the PD 12 disables the control input YES 13 from the second LPF 8 and connects this input to output ZB 11. Therefore, the second ring PLL stops working and YES 13 passes in a mode of self-oscillations at a frequency close to the frequency ISAC 1 multiplied by N is the division ratio of the second DPKG 10. However, at the RF input YES 13 through the closed key 14 and the voltage divider DN 15 is energized from the second output of the VCO 6, and seizure frequency oscillations YES 13 oscillations of the VCO 6, which continues to operate in the mode of generation frequency of the actuation ring phase-locked loop), is exactly equal to the reference frequency multiplied by N is the division ratio of the first DPCD 4. Therefore, the output voltage YES 13 will have a frequency equal to the synthesized VCO 6, which is covered by the PLL circuit, and the noise - relevant noise generators, the Torah, YES 13, working in the self-oscillation mode.

Thus, the operation of the device occurs in two stages. In the first phase of the VCO 6 and may 13 operate normally when the PLL and generate on their outputs are the same given frequency. In the second phase, the VCO 6 continues to operate in the mode of the PLL, and YES 13 operates as an oscillator in the capture mode, and the additional PLL circuit is opened, and controls the frequency YES 13 voltage is stored and continues to maintain oscillations YES 13 at a frequency nearly equal to that produced in the first stage, with an RF voltage (external excitation towards YES 13) from the second output of the VCO 6 through DN 15 and closed key 14 is supplied to the oscillating circuit YES 13. Therefore, the frequency of the synthesized signal at the outputs YES 13 (and the second output YES is the output device, i.e. it is connected to the load) will be determined by the frequency of the VCO 6, encircled by the ring of the PLL, and the noise will be determined by the noise YES 13, which is significantly lower than the frequency synthesizers with ring PLL similar to the one adopted for the prototype.

Description dual-mode oscillator is given in reference [5], [6] and [8]. In particular, in [6] discussed in detail the principle of capture and the capture bandwidth, and the functional (1) principal (2) schema dual mode oscillator.

For understanding the operation before aguinaga device will look at the properties YES 13 in capture mode frequency. In the textbook [8] on CTR is the ratio of (9.66)between the capture bandwidth of the oscillator with the offset of the external excitation, the q of the circuit and the ratio of the magnitude of the amplitude of self-oscillations to the amplitude of the external effects:

,

where ω_Withthe frequency of the external voltage capture;

ω₀- frequency self-oscillations of the generator;

the swath;

E - voltage self-oscillations;

E_OC- voltage external excitation;

Q is the quality factor of the oscillator circuit.

For our purposes, this formula can be converted to a more convenient form:

where Ω - generalized detuning, Ω_max- generalized swath.

;

ω₀/2Q - bandwidth circuit of the oscillator. Thus, to capture the frequency of the oscillator, in particular, YES 13, it is necessary that at a given value of E_OC/E offset was less than the maximum, Ω< Ω_max.

Pay attention to the fact that the value of Ω_maxshows how many times the detuning frequency of the external voltage of capture, and frequency of self-oscillations of the generator is less than the bandwidth of the oscillator circuit.

Friend the words from the relation (1) follows, the voltage of the external excitation F_OCnecessary to capture the frequency of the oscillator in the swath may be less than the voltage of self-oscillations during so many times, how many times the offset frequencyless than the bandwidth of the loop oscillator. In order to provide the desired voltage value of the external excitation F_OC, An RF voltage from the second output of the VCO 6 is input to YES 13 through DN 15. In this case, the duration of the setting process (capture) increases with decreasing values of E_OC.

In [5] and [6] a more accurate expression for the General case without a large number of approximations introduced by the author [8], obtained by other methods, and tested experimentally. In particular it is shown that within the swath Ω≤ Ω_maxin the capture mode time constant equal to the time constant of the oscillating circuit of the oscillator, multiplied by the ratio of:

Thus, when the Ω_max<<1 time constant in the capture mode increases and the bandwidth of the loop oscillator (YES 13) to the excitation voltage E_OCdecreases intime.

From this it follows that "noise" in the voltage of the external excitation is filtered by the loop band Q/ Ω_max. In the example, when Q=60 and Ω_max=1%, band Q/ Ω_max=6000. Suppression of noise from the external excitation by 10 dB will occur when the offset is greater than 1/30 of the bandwidth of the loop oscillator excitation by 20 dB will occur when the offset is greater than 1/15 of the bandwidth of the loop oscillator. When the output frequency of oscillator 30 MHz this will amount to 8.3 kHz and 16.7 kHz, respectively.

Therefore, when capturing dual mode oscillator (YES 13) external RF signal from the VCO 6 (with a much larger amount of "noise"), the frequency of its output will be equal to the frequency of the VCO 6, and "noises" YES 13 will define its own "noise" YEAH 13, which is significantly lower than the VCO 6 is covered by the ring PLL, except in extremely narrow region of frequencies in which the noise will be equal to the noise VCO 6.

Consequently, at the output device produces a voltage whose frequency is determined by a stable frequency source of reference frequency (ISAC), and "noise" is determined by the oscillator, which provides a significant reduction of "noise" in the output.

Thus, the proposed solution allows you to generate stable voltage in the frequency range with a specified frequency step with a low noise level.

Sources of information

1. Bobkov A.M. the Real selectivity of receiver paths in the one jamming environment. - St. Petersburg 2001, str.

2. Manasevich Century. frequency Synthesizers. Theory and design. Translation from English Vaulserre, edited Ashlina. - M.: Communication, 1979

3. Romanov, S. Kaliev, I.A. Markov Definition of interference fragmentation in frequency synthesizers with PLL using Delta-Sigma modulators in fractional frequency dividers. // theory and technique of radio communication. Scientific-technical collection, JSC "Concern "Sozvezdie", , Voronezh, 2006, No. 1, p.97-102.

4. System phase sync // Akimov V.N., Belyustina L.N., White NR. and others; Ed. by Val, Linebyline - M.: Radio and communication, 1982

5. BRCS OF the Effect of external vibrations on the oscillator on the differential cascade, p.102-108 // theory and technique of radio communication. Scientific-technical collection, VNIIS, Voronezh, 2002, No. 2.

6. BRCS OF Theory effects on oscillator noise and external vibrations. // theory and technique of radio communication. Scientific-technical collection, JSC "Concern "Sozvezdie", Voronezh, 2006, No. 1, p.106-112.

7. BRCS OF, Slipko SV Noise oscillator on the differential cascade. // theory and technique of radio communication. Scientific and technical proceedings, 2003, No. 2.

8. Gonorovski I.S. Radio circuits and signals. - M.: Soviet radio, 1977

The frequency synthesizer containing a source signal from a reference frequency, the control unit, the input of which is managing the speed of the device, connected in series to the first frequency-phase detector, the first low pass filter, a voltage controlled oscillator and the first divider with a variable division ratio, the output of which is connected to a second input of the first frequency-phase detector and the control input of the first divider with variable division factor is connected to the output of the control unit, characterized in that the input buffer stage, the unit time intervals, connected in series voltage divider, key, dual-mode oscillator, the second divider with a variable division ratio of second frequency-phase detector, a second lowpass filter, a storage unit and the switch from two directions, thus the output of a source signal from a reference frequency connected to the input buffer of the cascade, the first and second outputs of which are connected with the first inputs respectively of the first and second frequency-phase detector, the second output of the generator, voltage controlled, is connected to the input of the voltage divider, in addition, the output of the second lowpass filter connected to the first input of the switch from two directions, the output of which is connected with the control input of the dual-mode oscillator, a second output which is the output device, the output control unit connected with the control input of the second cases the indicator with a variable division ratio, and through the block of time intervals with control inputs switch from two directions and key.