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Digital signal synthesizer

Digital signal synthesizer
IPC classes for russian patent Digital signal synthesizer (RU 2250560):
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FIELD: radio engineering; frequency spectrum synthesizing and digital data signal shaping.

SUBSTANCE: proposed digital signal synthesizer has first and second delay circuits, low-pass filter, and three parallel channels, each incorporating pulse counter, memory unit, digital-to-analog converter, analog switch, analog adder, and delay circuit.

EFFECT: enhanced output frequency at same precision of signal shaping.

1 cl, 2 dwg

 

The invention relates to electrical engineering and can be used in transmitting, receiving and measuring devices for the synthesis of the grid frequency and a signal-transmission of discrete information.

It is known device described in the book Gnatek YU Reference digital-analog and analog-to-digital converters. M.: Radio and communication, 1982, s-260 containing serially connected counter, block memory, digital to analog Converter (DAC). The disadvantages of the device are reduced output frequency and accuracy formation of the output signals.

It is also known device copyright certificate (AC) No. 1501245, N 03 In 19/00, SU, containing the adder codes, DAC and M channels connected to respective inputs of the adder and to the main entrance, containing serially connected delay elements, counters, and memory blocks. The disadvantages of this device are reduced output frequency and accuracy of the signal, which is determined by the performance of target devices: adder codes and DAC. I.e. increasing the clock frequency achieved by summation of shifted in time channels is limited by the speed of the terminal device. These terminals have the speed (clock frequency and time of on-off) comparable ileage less than the devices in each channel.

The closest analogue is the device by the AC No. 1501245, N 03 In 19/00, SU.

To increase the output frequency while maintaining precision signal conditioning, a digital synthesizer signals, comprising: a first channel formation, consisting of series-connected counter, block memory, digital-to-analog Converter, as well as two series-connected delay elements and two channel formation connected in parallel to the first, each of which consists of series-connected counter and block memory, and the input of the first delay element is connected to the counter input of the first channel and the direct outputs of the first and second delay elements connected to the inputs of the counters of the second and third parallel channels, respectively, characterized in that it put a lowpass filter in the first channel forming a first analog switch, the input of which is connected to the output of the digital to analog Converter, connected in series to the first analog adder and the third delay element whose output is connected to the control input of the first analog switch and to the first input of the analog adder filed proinvestirovany input signal and the second input is connected to an inverted output of the first delay element, in the second and third channels forming sequentially connected to analog Converter and an analog switch, moreover, the inputs of digital to analog converters connected to the outputs of the memory blocks of the respective channels, and serially connected second and third analog adders and the fourth and fifth delay elements whose outputs are connected to the control input analog switch of the corresponding channel, and the first input of the second analog adder is connected to the inverse output of the first delay element and the second input to direct output of the second delay element, the first input of the third analog adder is connected to the inverse output of the second delay element, and the second input to the direct input of the digital synthesizer signal, and outputs the analog switches of all channels combined and connected to the input of the lowpass filter, the output which is the output device.

Figure 1 shows a diagram of the device. Figure 2 timing diagrams of the operation.

Figure 1 shows:

1, 2, 3 - first, second and third counters, respectively,

4, 5, 6 - the first, second and third blocks of memory (storage device), respectively,

7, 8, 9 - the first, second and third DACS, respectively,

10, 11, 12 first, second and third analog switches, respectively,

13, 14, 15, 16, 17 - first, second, third, fourth and fifth delay elements, respectively,

18, 19, 20 - first, second and third analog is the adders, respectively,

21 - low pass filter (LPF).

The digital synthesizer signal contains three counters 1, 2, 3, three blocks of memory 4, 5, 6, three DAC 7, 8, 9, three analog switch 10, 11, 12, five delay elements 13, 14, 15, 16, 17, two of them (13 and 14) with direct and inverse outputs three analog adder 18, 19, 20 and LPF 21.

The synthesizer signal is as follows.

For simplicity, we assume that all digital devices have the same performance (on and off) and are used at the maximum clock frequency. Therefore, the inputs (direct and inverse) of the synthesizer signal received signals, the pulse duration of which is equal to the pause time, i.e. in the form of a meander (diagrams a and b in figure 2). The delay elements 13 and 14 delay the input signal by approximately one third of the period (chart C, d, and e, f in figure 2), and the output of the analog adders 18, 19, 20 are formed shorter pulses, the duration of which is less than the speed of digital devices. They go through the delay elements 15, 16, 17 are fed to the analog keys 10, 11, 12, a speed which is considerably higher performance digital devices and using them is formed a stepped function of the output signal. Counters 1, 2, 3 produce address code, under the influence of which the code reading of the amplitude of the generated signal and the blocks of the memory 4, 5, 6. DAC 7, 8, 9 make the transition from code to an analog signal value, and the analog switches 10, 11, 12 are cut from the signals of the DAC 7, 8, 9 pulses with an amplitude corresponding to the output signal at the given points. Since the pulses from the outputs of the analog switches are separated in time at the input of LPF 21 is formed a stepped function, corresponding to the output waveform, and the output low-pass filter 21 is peeled from the interference signal. The delay elements 15, 16, 17 serve to compensate for delays that accumulate in the series connected counters, storage devices and DACS, each of the channels.

Shown in figure 1 synth allows you to get three times more points in the period of the generated signal, or three times to increase the output frequency while maintaining the accuracy of the generated signal.

Thus, at the same speed digital devices claimed the device allows three times to increase the output frequency in comparison with the equivalent.

All the elements of the device can be implemented on standard hardware components, and do not have any special features.

The digital synthesizer signal containing the first channel formation, consisting of series-connected first pulse counter, the first block of memory, the first digital to analogue Converter, and you'll find the positive connected first and second delay elements and the second and third channels of the formation, connected in parallel to the first, each of which consists of series-connected second pulse counter and the second memory block, the third pulse counter and the third memory block, respectively, and the input of the first delay element connected to the input of the first pulse counter, and direct outputs of the first and second delay elements connected to the inputs of the second and third pulse counters, respectively,characterized in that it introduced a low-pass filter, and a first channel formation of the first analog switch, the input of which is connected to the output of the first d / a Converter, and connected in series to the first analog adder and the third delay element whose output is connected to the control input of the first analog switch and to the first input of the first analog adder filed proinvestirovany input signal and the second input is connected to an inverted output of the first delay elements, the second and third channels forming entered serially connected second digital to analog Converter and the second analog switch, the third d / a Converter and the third analog switch, respectively,and the inputs of digital to analog converters connected to the outputs of the memory blocks of the respective channels, and sledovatelno United second analog adder and the fourth delay element, connected in series, the third analog adder, the fifth delay element, and outputs of the delay elements are connected to control inputs analog switches of the corresponding channel, the first input of the second analog adder is connected to the inverse output of the first delay element and the second input to direct output of the second delay element, the first input of the third analog adder is connected to the inverse output of the second delay element, and the second input to the direct input of the digital synthesizer signal, and outputs the analog switches of all channels combined and connected to the input of the lowpass filter whose output is the output device.

 

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