Digital signals synthesizer |
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IPC classes for russian patent Digital signals synthesizer (RU 2257669):
              
 Digital signal synthesizer / 2250560
Proposed digital signal synthesizer has first and second delay circuits, low-pass filter, and three parallel channels, each incorporating pulse counter, memory unit, digital-to-analog converter, analog switch, analog adder, and delay circuit.
Digital signal synthesizer / 2250560
Proposed digital signal synthesizer has first and second delay circuits, low-pass filter, and three parallel channels, each incorporating pulse counter, memory unit, digital-to-analog converter, analog switch, analog adder, and delay circuit.
 Digital signals synthesizer / 2257669
Device has standard support generator, delay block, first memory register, first digital accumulator, second digital accumulator, third digital accumulator, codes converter, analog-digital converter, low frequency filter, second memory register, divider with variable division coefficient, delay multi-vibrator.
 Digital computing synthesizer / 2286645
Digital computing synthesizer contains standard generator, delay block, digital accumulator, digital-analog converter, low frequencies filter, band filter, permanent memory block, divider with variable division coefficient, waiting multi-vibrator, two memory registers, reverse frequency counter, impulse generator, codes transformer and device for displaying frequency of output signal.
 Digital quadrature-output computing synthesizer / 2294054
Proposed device has standard generator, delay unit, two memory registers, two digital storage devices, variable-ratio divider, two code converters, two digital-to-analog converters, two low-pass filters, and inverter.
 Frequency synthesizer / 2329594
Invention is referred to radio communication and may be used in radio receiving and radio transmitting devices for radio signal generation, modulation and frequency conversion. Synthesizer includes signal source of reference frequency, two frequency and phase detectors, control unit, two dividers with variable division factor, two low-frequency filters, voltage controlled generator, buffer amplifier, storage unit, switch from two directions, two-mode auto generator, alignment plug and temporary interval unit.
 Frequency synthesizer / 2329595
Invention is referred to radio communication and may be used in radio receiving and radio transmitting devices for radio signal generation, modulation and frequency conversion. Synthesizer includes signal source of reference frequency, frequency and phase detector, control unit, divider with variable division factor, two low-frequency filters, voltage controlled generator, direct current amplifier, interfacing circuit, two-mode auto generator.
 Frequency synthesizer with acoustic circuit of adaptive frequency and phase auto tuning / 2329596
Invention may be used for generation of stable frequency network with even interval in receiving and transmitting devices and is notable for short tuning time within broad range of operating frequencies. Device includes controlled generator, frequency divider with variable division factor, frequency and phase detector, reference generator, frequency divider with fixed division factor, controlled charging unit, trapping-by-phase rating unit, microcontroller, trapping-by-frequency rating unit and low-frequency filter consisting of two capacitors, two resistors and two switches.
 Time-and-frequency synchronisation device / 2341892
Proposed device comprises a reference generator, two variable-ratio dividers, a phase detector, control generator, two digital-to-analogue converters, computer, mode selection unit, device for determining temporary position of the input pulse, index zone generator and a frequency divider.
 Digital synthesiser of frequency and phase modulated signals / 2358384
Present invention pertains to electronics and computer technology, meant for synthesising frequency and phase modulated signals and can be used in radar, navigation and adaptive communication systems. The digital synthesiser of frequency modulated and phase modulated signals contains a reference generator, delay unit, first memory register, first digital accumulator, second memory register, second digital accumulator, adder, code converter, digital-to-analogue converter, low pass filter, third memory register, frequency divider with varying division factor, fourth memory register and a third digital accumulator.
 Frequency synthesiser / 2394367
Frequency synthesiser includes two frequency phase detectors, two low-pass filters, voltage-controlled generator, two dividers with variable division factor, buffer cascade, two synchronism indicators, coincidence circuit, D flip-flop, shaper of control signal and amplifier with controlled amplification factor, two-mode self-oscillator, control unit, key, switch from two directions, storage unit and signal source of reference frequency.
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FIELD: computer science. SUBSTANCE: device has standard support generator, delay block, first memory register, first digital accumulator, second digital accumulator, third digital accumulator, codes converter, analog-digital converter, low frequency filter, second memory register, divider with variable division coefficient, delay multi-vibrator. EFFECT: broader functional capabilities, higher efficiency. 2 dwg
The invention relates to electronic computing, designed for the synthesis of signals with frequency modulation, according to the square law, and may be used in radar, navigation systems and sensing systems in different environments. Known digital frequency synthesizers containing a clock and a delay block, two blocks of constant memory, preset counters, two memory registers, two digital drive, the code Converter, digital to analog Converter, a low pass filter whose output is the output of a digital frequency synthesizer, and the inputs are the address inputs of the first and second blocks of constant memory [1]. The closest technical solution (prototype) to offer is a digital synthesizer is frequency-modulated signals containing serially connected reference generator and the delay unit, connected in series block of continuous memory, reverse preset counters (frequency counter)digital drive (transmitter phase), the code Converter, digital to analog Converter, a low pass filter whose output is an analog output of the synthesizer waiting multivibrator, the output of which is connected to the inputs of the reverse secondary market is ka, digital drive, divider with variable division factor; memory register, the output of which is connected to information inputs of the divider with a variable division ratio, the yield of the latter is connected to the clock input of a reversible counter, a comparison circuit, the first inputs of which are connected to the outputs of the unit's permanent memory, the second inputs to the outputs of the reversible counter, and the output connected to the control input of the invoice reversible counter, the outputs of the delay block is connected to the clock inputs of the register memory divider with a variable division ratio, digital memory, digital to analog Converter, while the digital inputs of the synthesizer are the address inputs of a block of continuous memory, input memory register and the input of the start standby multivibrator [2]. However, in the known frequency synthesizers there is no possibility of forming a signal with a quadratic law of frequency changes. The invention allows to extend the functionality of the digital synthesizer and provides the required law of frequency modulation of the synthesized signal. Positive effect - the possibility of the synthesis signal with a quadratic frequency modulation is achieved by the fact that in the digital synthesizer signal as a frequency counter instead of a reversal is on the counter with preset used two series-connected digital drive. In the digital synthesizer signal with a quadratic law change frequencies containing serially connected clock and the delay unit, connected in series, the third digital drive, the code Converter, digital to analog Converter and a low pass filter, connected in series, the first memory register and a divider with a variable division factor; standby multivibrator, the output of which is connected to the input set of the divider with a variable division ratio, the outputs of the delay block is connected to the clock inputs of the second register memory divider with a variable division ratio, digital to analogue Converter, the third digital drive, senior output discharge amount which is connected to the control input of the inverting Converter codes; the input of the second memory register and the input of the start standby multivibrator are digital inputs, and the output of the lowpass filter analog output of the digital synthesizer signal, and the new is the fact that additionally introduced sequentially connected first memory register, the first and second digital drives; the output of the second digital memory connected to the third input of the digital memory, the standby output of the multivibrator is connected to the input set of the first qi the world drive to the clock input of the latter is connected to the output of the divider with variable division factor; the outputs of the delay block is connected to the clock inputs of the first memory register and the second digital memory and the input of the first memory register is a digital input of the synthesizer signal. Figure 1 shows the structural diagram of the digital synthesizer signal with a quadratic law change frequencies, figure 2 - diagram of the operation of the device. The digital synthesizer signal (figure 1) contains a reference (reference) generator 1, the delay unit 2, the first memory register 3, the first digital memory 4, the second digital memory 5, the third digital memory 6, the code Converter 7, a d / a Converter 8, the low pass filter 9, the second register memory 10, the divider with a variable division ratio of 11 waiting multivibrator 12. Digital synthesizer (figure 1) contains serially connected reference generator 1 and the delay unit 2; sequentially connected first memory register 3, the first and second digital drives 4 and 5 (frequency counter), the third digital drive 6 (the transmitter phase), the code Converter 7, a d / a Converter 8, the low pass filter 9 whose output is an analog output synthesizer; serially connected second memory register 10 and the divider with variable the m division factor 11; waiting multivibrator 12, the output of which is connected simultaneously to the inputs of the installation of the first digital memory 4 and divider with variable division factor 11; the outputs of the delay unit 2 is connected to the clock inputs of the first and second memory registers 3 and 10, a divider with a variable division ratio of 11, second and third digital drives 5 and 6, and also to the clock input of a digital to analogue Converter 8; output high-order bit of the sum of the third digital memory 6 connected to the control input of the inversion of the code Converter 7, and the output of the divider with a variable division ratio of 11 is connected to a clock input of the first digital drive 4, the inputs of the first and second memory registers 3 and 10 and the input set standby multivibrator 12 are digital inputs of the device. The digital synthesizer signal is as follows. The reference generator 1 outputs a signal of the reference frequency sine wave which is fed to the input of the delay block 2 forming spaced in time sequence of rectangular pulses of the form "meander" (figa)received at the clock inputs of the first and second memory registers 3 and 10, a divider with a variable division ratio of 11, second and third digital drives 5 and 6, the digital-analog Converter 8 and used for the synchronization the purpose of the operation of the synthesizer. Let at time t0(figb) input standby multivibrator 12 comes triggering pulse uC(t), the output of which is formed a pulse setup umouth(t) of negative polarity (pigv). Then in the time of arrival of the positive edge of the pulse clock frequency t1(2 g) in the first memory register 3 write code start frequencyiand code division ratio of Dkis written to the second memory register 10. At time t2code start frequency Cirecorded in the first digital memory 4, and the code Dkfrom memory register 10 in the divider 11. At time t3at the end of the pulse setup (figure 2) write code Withifrom the first digital memory 4 in the second digital memory 5. Then with each subsequent clock pulse tnthe code amount in the first digital storage device 4 will vary according to the formula:
where T=1, 2, 3, 4,... - the number of the clock pulse. In the second digital memory 5 code amount will change as follows:
Then the output of the third digital drive 6 code amount will vary according to the following formula:
If we assume that f0=Ci/2π - initial frequency, f'=1/Dk- the speed of the change of the frequency, a Δt=T, the phase of the synthesized signal will vary according to the formula:
Senior level SGN code amount S is fed to the control input of the inversion of the code Converter 7, and the remaining N high-order bits of code amounts through the code Converter 7 receives information inputs digital to analogue Converter 8 (where N is the number of bits of the DAC). If SGN=0, the d / a Converter 8 is supplied straight binary code amount, and if SGN=1 then - return code amount S. Output digital-to-analog Converter is formed by an analog signal "triangular" form, which is supplied to the lowpass filter 9, which transmits the output of the synthesizer only the first harmonic of the synthesized signal, the amplitude of which will vary according to the formula:
where Umthe amplitude of the signal. Therefore, the synthesizer is generated FM signal with a quadratic law of frequency changes. Literature 1. Patent No. 2058659 Russian Federation MKI N 03 In 19/00, the Digital frequency synthesizer / Ryabov I., fishchenko P.A. - Appl. 23.09.1993. Publ. 20.04.1996. Bulletin no.11. 2. Patent No. 2204197 Russian Federation IPC H 03 L 7/18, Digital frequency synthesizer / Ryabov I. Ryabov, VI - Appl. 06.04.2001. Publ. 10.05.2003. Bull. No. 13 (prototype). The digital synthesizer signal containing sequence is correctly connected to the generator of clock pulses and the delay unit, connected in series, the third digital drive, the code Converter, digital to analog Converter and a low pass filter, connected in series, the first memory register and a divider with a variable division factor; standby multivibrator, the output of which is connected to the input set of the divider with a variable division ratio, the outputs of the delay block is connected to the clock inputs of the second register memory divider with a variable division ratio, digital to analogue Converter, the third digital drive, senior output discharge amount which is connected to the control input of the inversion of the code Converter; the input of the second memory register and the input of the start standby multivibrator are digital inputs, and the output of the lowpass filter analog the output of the digital synthesizer signal, characterized in that additionally introduced sequentially connected first memory register, the first and second digital drives, and the output of the second digital memory connected to the third input of the digital memory, the standby output of the multivibrator is connected to the input of the installation of the first digital drive, to the clock input of the latter is connected to the output of the divider with a variable division ratio, the outputs of the delay block is connected to the clock inputs of the first is egistra memory and the second digital memory, and the input of the first memory register is a digital input of the synthesizer signal.
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