Frequency synthesiser

FIELD: radio engineering.

SUBSTANCE: frequency synthesiser, having a control unit, a first intermediate frequency synthesiser, a second intermediate frequency synthesiser, characterised by that it has a second intermediate frequency phase-locked-loop frequency control (PLLFC) synthesiser, which synthesises a fixed reference frequency, a DDS synthesiser with frequency tuned in the given range, a low-pass filter of the DDS synthesiser, a mixer of the PLLFC synthesiser reference frequency and a DDS synthesiser, whose output frequency is equal to the sum of the reference frequency of the PLLFC synthesiser and frequency of the DDS synthesiser, a band-pass filter for filtering the output frequency of the mixer.

EFFECT: high accuracy of setting the frequency of the receiver and reduced phase noise in the output signal.

5 cl, 2 dwg

The frequency synthesizer relates to electrical engineering and can be used in systems with double frequency conversion, providing a frequency within wide limits in increments determined by the resolution of the used chip direct digital synthesis DDS.

A known device for synthesizing frequencies, including chip direct digital synthesis DDS, a filter for the signal from the DDS, designed to filter the main signal from the harmonic components, the divider reference signal, a phase detector for detecting phase difference (phase shift) between the specified reference signal and a feedback signal and to provide a corresponding error signal, a loop filter (integrator) for receipt of the error signal, noise filtering in the specified error signal and using the filtered error signal as a control signal, the VCO oscillator, voltage controlled errors that used for the generation of finite frequency, a divider for dividing the output signal frequency by N to provide the specified feedback signal according to the frequency of the output signal frequency divided by N. (Patent US 4.965.533 from 23.10.1990, IPC H03L 7/18.) This invention is used as a prototype.

The disadvantage of the invention is the high level of spurious noise output is astate frequency synthesizer. The formula of the final (output) frequency F_Konlooks like this:

F=N·F=N·F synthesizer DDS/M=(N/M)·Fdds

Stage divide-by-M" fixed divider that selects a specific frequency range, while the DDS provides accurate frequency resolution within this range. The Spur level (spurious signals) DDS will be reduced at the stage of "divide-by-M, but then increased by N in the output frequency F (as usually F is always greater than the frequency of the clocking - in our case, Fdds, the division factor N is always greater than the coefficient M

N=F/Fcpa

that is, all spurious noise from the DDS synthesizer will first be reduced to M times the frequency of the comparison of the synthesizer PLL, and then increased N times at an output frequency of F).

The purpose of the claimed invention is to achieve a discrete frequency changes in increments of 0.1 Hz in a wide range of frequencies to accurately set frequency receiver, the improvement of the purity of the output signal from spurious signals synthesizer DDS and, accordingly, improving the phase noise of the output signal, reducing the energy consumption in the work and cost of the device during production.

The technical result is achieved in that the frequency synthesizer containing a control unit, synthesizer first intermediate frequency, sintasath the p second intermediate frequency, differs in that it contains in the synthesizer of the second intermediate frequency synthesizer phase-locked loop frequency synthesizing a fixed reference frequency, DDS synthesizer with tunable within the specified frequency range, the filter DDS frequency synthesizer, a mixer, a reference frequency synthesizer PLL and DDS synthesizer, the output frequency is equal to the sum of the reference frequency synthesizer PLL and DDS frequency synthesizer band-pass filter for filtering the output frequency of the mixer, and also contains for the first intermediate frequency VCO with switching sub-bands within the operating frequency by using a polarized relay, which consumes current only in the dynamics (when switching).

In the drawings shows

Figure 1 - block diagram, mixer containing the first intermediate frequency (PC) and the second mixer intermediate frequency (PC).

Presents synthesizer combines the methods of direct digital synthesis DDS and frequency synthesis phase-locked loop PLL. This synthesizer can be used in systems with double frequency conversion and to provide a frequency within wide limits in increments determined by the resolution of the used chip direct digital synthesis DDS. It consists of two independent frequency synthesizers. To ensure perestroika the frequency within a wide range with a small step and to simplify the circuitry of the synthesizer method with two tunable intermediate frequency (hereinafter, FC). The method lies in the fact that at the input of the first mixer as a local oscillator signal synthesizer in full frequency range with step adjustment 10 kHz, and the input of the second mixer lo signal synthesizer with a frequency equal to the frequency PC and variable ranging from 0 to 9,9999 kHz with step adjustment of the order of 0.1 Hz (determined by step adjustment used chip direct digital synthesis DDS) - 1. In the discrete frequency changes by 1 FC in increments of 10 kHz and 2 if in increments of 0.1 Hz is achieved the possibility of frequency tuning in a wide range of frequencies defined by the synthesizer 1 of the inverter, and with a step defined by the synthesizer 2 FC.

Due to the fact that the frequency of the local oscillator 1 if frequencies above the frequency of the input signal, the transformation 1 FC is the signal inversion. A second inverter to invert the signal, so the bandpass filter after 2 if you want to highlight the inverted lower sideband.

Abbreviations: F 1 - frequency synthesizer 1 lo (66.5-95 MHz),

F1 - frequency 1st if

F2 - frequency 2nd if

F 2 - frequency synthesizer 2 lo (59.990-60 MHz),

F - frequency received signal.

(2) insert (1). F2=F 1-F 2-F or signal F=F 1-F 2-F2.

Knowing the frequency of the settings F and frequency F2, set the frequency synthesizer 1 FC F 1 with a step of 10 kHz, and the frequency synthesizer PC F 2 in increments of 0.1 Hz.

Figure 2 - block diagram of the synthesizer of the first intermediate frequency and the synthesizer of the second intermediate frequency, which contains the synthesizer 1 frequency PLL for the second intermediate frequency (PC), the integrator 2, a generator 3, a voltage controlled (GUNS), for PC, the mixer 4, the buffer amplifier 5, DDS synthesizer 6 on the basis of the DDS IC, filter, low frequency 7 (LPF), two band-pass filter 8, connected in series, the buffer amplifiers 9 frequency coming from the output of the band pass filter 8, the control unit 10, the synthesizer 11 frequency PLL for the first intermediate frequency (PC), the integrator 12, the generator 13, a voltage controlled, for PC, buffer amplifier 14.

The synthesizer for the first intermediate frequency is a conventional frequency synthesizer phase-locked loop (PLL) - 2. Code frequency in the chip frequency synthesizer PLL 11 is recorded by the control block 10. The control signal Maricopa to capture frequency is integrated by the integrator 12 and is supplied to the generator 13, a voltage controlled (VCO). From the output of the signal generator 13 is fed to buffer amplifier 14, which serve to strengthen and decoupling of the output signal. Further, amplified to the level required for the work is as heterodyne, the signal is fed to the mixer PC - 1. The VCO 13 is a wideband generator with switchable customizability elements. Each frequency control element overlaps a certain subrange of frequencies. The generator is used 7 sub-bands, which overlap the frequency range from 66.5 to 95 MHz. As the switching frequency control elements taken the variable capacitors, changing the capacity of which can be tuned frequency in each sub-band. The commutation capacitor is polarized relay, which in the static mode does not consume energy. The management of these relays depending on the frequency performs the control unit 10. The installation of the exact frequency in each sub-band performs varicap controlled PLL synthesizer 11.

Synth 2 FC consists of synthesizer 1 frequencies with PLL, which is controlled by the control block 10. In this synthesizer, the control unit 10 writes a fixed frequency F 58.990 MHz. The control signal after the integrator 2 is supplied to varicap generator 3 is controlled by a voltage. VCO 3 is made in the usual way capacitive treatacne. The signal generator 3 is supplied to the mixer 4 as lo. The signal at the mixer 4 through a filter 7 low frequency cutoff frequency of 1.2 MHz receive frequency of the order of 1 M is C with restructuring in the range of 10 kHz from the DDS synthesizer 6. The frequency of the DDS chip sets unit 10 controls. After the mixer 4 signal to couple the high-frequency band quartz filter 8 with a bandwidth of 20 kHz at a frequency of 59.995 MHz. In the result after the filters 8 remains one lateral frequency 59.995 MHz offset from center frequency ±5 kHz depending on the tuning frequency DDS synthesizer 6. Another converted in the mixer 4 side frequency 57.990 MHz is attenuated bandpass filters 8 to about 70 dB.

After bandpass filters 8 signal is applied to buffer amplifier 9, which serve to strengthen and decoupling signal. Further beefed-up is required to work as a heterodyne signal of the mixer PC is supplied to the unit PC - 1.

All chips synths 1, 6, 11 aktiruyte from one high-stability reference oscillator.

The inclusion of the DDS chip at a low frequency with subsequent conversion to a high frequency using a signal stand from synth 1 PLL due to the fact that higher frequencies require more high-speed, expensive and consume more power DDS chip, which leads to higher device and increase its power. This device is simpler and cheaper chip DDS synthesizer 6.

In accordance with the claimed invention were manufactured the go frequency synthesizers, in which the frequency synthesizer SC generates a frequency in the range 59,990-60 MHz with step adjustment up to 0.01 Hz is determined by the resolution on the frequency used by the DDS chip synthesizer 6. Functionally MF consists of synthesizer 1 PLL at a fixed frequency in the mixer 4 is formed with the DDS frequency synthesizer 6. Then the filters 8 highlights one sideband conversion (top) and after amplification in the buffer amplifier 9 is supplied to heterodyne the input of the mixer PC - 1.

Synth 1 fixed frequency 58.990 MHz is a chip PLL is running. The control signal Maricopa to capture the frequency of the VCO 3 is integrated in the integrator 2. Further, the fixed frequency signal is supplied to the mixer 4. As the local oscillator for the mixer 4 receives the signal from the DDS synthesizer 6. The frequencies selected in the range of 1-1,009999,9 MHz with step adjustment in 0.1 Hz.

To filter spurious harmonics of the lo signal is additionally filtered in the filter 7 low frequency cutoff frequency of 1.2 MHz. Frequency synthesizers 1 and 6 are recorded by the control unit 10 (microprocessor). The reference frequency synthesizers comes from a highly stable thermostatic oscillator. The buffer amplifier 5 serves to strengthen the sinusoidal signal op is nuclear biological chemical (NBC frequency to a level necessary for DDS synthesizer 6 to DDS chip. At the output of the mixer 4, resulting in two frequency 59,990-59,999999 MHz and 57,990-57,999999 MHz. The upper side frequency 59,990-59.999999 MHz passes through the narrowband quartz bandpass filters 8 and all the extra frequencies are suppressed these filters to the level of not less than 70-80 dB. The filtered signal frequency 59,990-59,999999 MHz is fed to buffer amplifier 9, where after amplification to the level required to work as a heterodyne signal of the mixer is fed to the inputs PC respectively of the first and second receiver channels.

The claimed invention completely solves the problem. The principle of restructuring the local oscillators of the two inverter enables accurate setting of the frequency of the receiver. This diagram of the frequency synthesizer provides a low level of spurious components from the DDS synthesizer 6 through the use of DDS chips in a very narrow band of frequencies with subsequent filtering of the signal in the filter 7 low frequency band quartz filters 8 when using highly stable elements allows to obtain the phase noise in the band 300-3400 Hz no worse than 95 dB (deterioration of the sensitivity by 2 times) when the parasitic frequency deviation (SMOS) not more than 0.1 Hz. The inclusion of the DDS synthesizer at a low frequency eliminates costly high-frequency DDS chips and reduced the t of the cost of the device, and also reduces the energy consumption, as is the use of polarized relay, consuming power only when switching.

1. The frequency synthesizer containing a control unit, synthesizer first intermediate frequency, the synthesizer of the second intermediate frequency, characterized in that it contains in the synthesizer of the second intermediate frequency synthesizer phase-locked loop (PLL)synthesizing a fixed reference frequency, DDS synthesizer with tunable within the specified frequency range, the filter low frequency DDS synthesizer, mixer reference frequency synthesizer PLL and DDS frequency synthesizer input to the mixer through the filter of low frequencies, the output frequency of the mixer is equal to the sum of the reference frequency synthesizer PLL and DDS frequency synthesizer band-pass filter for filtering the output frequency of the mixer, high-stability reference the generator, which aktiruyte chip frequency synthesizer PLL for the second intermediate frequency, DDS synthesizer frequency synthesizer PLL for the first intermediate frequency.

2. The frequency synthesizer according to claim 1, characterized in that the synthesizer first intermediate frequency contains a VCO with switching sub-bands within the operating frequency by using a polarized relay, which consumes current only in the dynamics (when switching).

3. Synth Castoro to claim 1, characterized in that it contains the buffer amplifiers frequency coming from the output of bandpass filter.

4. The frequency synthesizer according to claim 1, characterized in that the bandpass filter is made in the form of two band-pass filters connected in series.

5. The frequency synthesizer according to claim 1, characterized in that the DDS synthesizer contains a chip direct digital synthesizer DDS with step adjustment of 0.1 Hz.