Device for transforming angular movement of antenna of radiolocation station

FIELD: control systems.

SUBSTANCE: device has sensors block, block for forming signals of azimuth binary code, two adders, strobes forming block, control block, rotation imitator, correction code detector, clock pulse generator, binary counter, multiplexer, operative and constant memory devices, static register.

EFFECT: higher speed of operation.

4 dwg

 

The invention relates to systems of control and regulation of non-electrical quantities, namely the conversion of non-electrical quantities into electrical signals.

The device may find application in radar, space technology and communication systems where the task of converting the angular displacement of the antenna into a digital code.

A known system for converting angular movement of the radar antenna containing a sensor unit with an input for connection of the shaft of the antenna and connected in series simulator rotation, the inverter angular information and the set of gates, and the output of the sensor unit is connected to a second input of the inverter angular information.

This system has higher accuracy compared with the previous, since no intermediate repeater rotation, however, this system does not allow you quickly and easily carry out the operation of orientation, because it is inherent disadvantage of the previous system, namely the need for mechanical rotation sensors.

Known devices for converting the angular displacement of the radar antenna the closest in technical essence to the present invention is a device for converting angular movement of the radar antenna that contains one United block mitchiko is, the signal azimuth binary adder and block the formation of the gates, as well as simulator of rotation, which is connected with the second input of the processing unit azimuthal binary code sensor code, which is connected with the second input of the adder, and a control unit, which is connected to the output of the adder.

Sensor unit converts angular displacement into digital information in the form of a unitary codes received at a first input signal azimuthal binary code. To the second input of this block with the simulator rotation do the same unitary codes required to work in simulation mode antenna rotation. The signal azimuth binary code generates the binary code of the azimuth, which is supplied to the first input of the adder. To the second input of the adder with sensor code is supplied binary code amendments. The output signals of the adder is coming to the block forming gates and the control unit.

An advantage of the device of the prototype is its orientation with minimal time due to operational input binary code amendments and, in addition, the high accuracy of the transformation angle. However, recent valuable quality can be realized under the condition of stability of the rotation speed of the antenna. The fact that the azimuth is the information in the radar must be detained at the time of acquisition and processing of signals in the radar receiver. Therefore, the code of azimuth introduces additional angular correction corresponding to the known time delay. In practice, this is reflected in the fact that during the operation of the orientation code generated by the conversion device, reduce in size

β3=wt3,

where β3the delay in the corner,

ω - the angular velocity of rotation of the antenna,

t3the time delay of the signal in the receiver.

If the rotation speed of the antenna is unstable, then

β30t3±Δωt3,

where ω0- average speed,

Δω - change speed.

Because some radar value Δω can reach 10%, the same procedure will speed error code azimuth. This is a significant drawback of the prototype.

The technical result of the proposed invention is to improve the accuracy of conversion of angular displacement by eliminating high-speed conversion error.

The technical result is achieved in that in a device for converting angular movement of the radar antenna containing serially connected sensor unit, the signal azimuth binary code and the adder, the combined input block for the formation of the gates, and the control unit, the simulator rotations the tion, connected to a second input signal azimuthal binary code, and the sensor code connected to a second input of the adder, according to the invention connected in series introduced a generator of clock pulses, a binary counter, a second adder, multiplexer, random access memory and static register, the output of which is connected to the input of the processing unit gates, a persistent storage device, coupled to the second input of the second adder, the first input is additionally connected to the second multiplexer input.

The novelty of the invention follows from the fact that in the descriptions of the known devices do not contain information about the elimination or compensation speed error code angle.

Analysis of the known technical solutions showed that the introduced elements known in themselves, but their combined use allows to obtain a new technical result, and this gives grounds to conclude that the proposed solution meets the criteria of the invention "inventive step".

The causal connection between the set of essential features of the claimed invention and achievable technical result is due to the fact that the replacement of the angular delay azimuthal information on the time delay led to increasing the tell-precision conversion of angular displacement unstable when the speed of rotation of the antenna.

The invention is illustrated in the following description and graphic materials. Figure 1 and 2 show respectively a device for converting the angular displacement of the prototype and the proposed device converting the angular displacement, where indicated:

1 is a block sensors;

2 - signal azimuthal binary code;

3 - adder;

4 - block the formation of the gate;

5 - control unit;

6 - simulator rotation;

7 - gauge code;

8 is a generator of clock pulses;

9 is a binary counter;

10 - the second adder;

11 - multiplexer;

12 - random access memory;

13 - the static case;

14 is a permanent storage device.

Figure 3 shows a variant of scheme control unit, where indicated:

DD1- binary code Converter in the signal segment of code

DD2-DD5digital indicators code.

4 shows a variant of the scheme of the sensor code where indicated:

DD1generator logical units

DD2generator logic zero,

S1-S12switch bits of code.

The proposed device has connected in series sensor unit 1, the signal azimuth binary code 2 and the first adder 3, the combined input of the processing unit when Robow 4, and the control unit 5, the simulator of rotation 6, connected to a second input signal azimuthal binary code 2, and the sensor code 7 connected to a second clock input 8 binary counter 9, a second adder 10, a multiplexer 11, a random access memory 12 and the static register 13, the output of which is connected to the input of the block forming gate 4, a persistent storage device 14, connected with the second input of the second adder 10, the first input is additionally connected to a second input of the multiplexer 11.

Option scheme of the control unit shown in figure 3, contains a binary code Converter in the signal segment of code with inputs for connection of binary and digital indicators code DD2-DD5whose inputs are connected to the outputs of the Converter DD1.

Option schemes sensor code shown in figure 4, comprises a generator of logical units, generators, logic zero at the IC performs the function NOT, and switches the bits of the binary code, the switching signals a logical zero and a logical unit.

The proposed device operates as follows.

Sensor unit 1 converts the angular displacement of the antenna (figures not shown) in the discrete information in the form of pulse signals, which are received at the first input of BL is the AC signal, received on the first input signal azimuthal binary code 2. To the second input of this block with the simulator of rotation 6 do the same pulse signals required to work in simulation mode antenna rotation. The signal azimuth binary code 2 generates a binary code of azimuth, which is supplied to the first input of the adder 3. To the second input of the adder 3 with sensor code 7 is supplied binary code amendments for reference azimuth information to the true North. From the output of the adder 3 azimuthal code is supplied to the operational storage device 12 (RAM), where it is stored for time t3. Recording and reading of information RAM 12 is controlled by signals from the multiplexer 11. Code address of record supplied to the multiplexer 11, and the binary counter 9, the input of which receives pulses from the clock 8. Code read address to the multiplexer 11 is supplied from the second adder 10, which produces the sum of the current code counter 9 with the code recorded in the ROM 14 (ROM). ROM code is a digital equivalent to the delay time t3.

Thus, the azimuthal information, read out from the RAM 12, is delayed by a time t3in relation to information from the output of the adder 3. Static the y register 13 stores the azimuth information in the intervals between the code reading from the RAM 12. Code azimuth from the static output of the register 13 is supplied to block the formation of the gate 4 and the control unit 5.

Such a scheme of construction of the NAT device and eliminates the need to introduce incremental code information to account for delays azimuth information at the time of acquisition and processing of the signal in the path of the radar receiver and, consequently, to improve the accuracy of conversion of the angular displacement of the antenna at unstable speed of its rotation.

The technical result of the invention is to improve the accuracy of conversion of angular displacement by eliminating the high-speed binary error code angle.

A device for converting the angular displacement of the antenna of the radar station, containing serially connected sensor unit, the signal azimuth binary code and the adder, the combined input unit forming a gate and a control unit, a simulator of rotation connected to a second input signal azimuthal binary code, and the sensor code amendments connected to a second input of the adder, characterized in that the device is entered serially connected clock generator pulses, a binary counter, a second adder, multiplexer, memory device is in, on which the adder is supplied azimuthal code, and static register, the output of which is connected to the input of the processing unit gates, a persistent storage device, coupled to the second input of the second adder, the first input is additionally connected to the second multiplexer input.



 

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