Backup double-channel analog-to-digital converter

FIELD: computer engineering.

SUBSTANCE: proposed device that can be used in high-reliability computer-aided monitoring, data processing and acquisition systems has two analog-to-digital converters, two switching units, two sensors, and control unit. This device is characterized in low failure probability, reliability of conversion when implementing structure of analog-to-digital computer capable of operation in two modes of parallel and/or serial polling of sensors, and in ability of its on-line reconfiguration in the event of failure by self-check results of each analog-to-digital converter.

EFFECT: enlarged functional capabilities, extended mean time between failures, reduced maintenance charges.

4 cl, 6 dwg

 

The invention relates to computer technology and can be used in automatic control, collection and processing of information with improved reliability.

Known analog-to-digital Converter - ADC (ed. St. USSR №1529454, CL N 03 To 1/48, 1987), containing three comparator, a reversible counter, a code Converter in voltage, elements, AND, EXCLUSIVE OR, a switch, a pulse generator, a trigger, a source of reference voltages.

The disadvantages of the ADC are low accuracy and speed of conversion, a large number of Comparators, and the impossibility of normal operation under failure of some of its nodes.

A device analog-to-digital conversion (ed. St. USSR №809554, CL N 03 To 13/17, 1979), contains two comparator register, the bit node switches, two resistive matrix R-2R, elements, AND, OR, delay, two triggers, switches, pulse generator, a distributor of clock cycles, the logic block.

The drawbacks are the low accuracy of the transformation, a large amount of the control means, the low speed control, and the impossibility of normal operation under failure of individual nodes and elements.

A device analog-to-digital conversion (RF patent No. 2020751, CL H 03 M 1/46, 191), contains a successive approximation register, dwolatzky code Converter in voltage, the pulse generator, the elements AND, OR, NOT, triggers, delay elements, the sources of the reference voltages.

The drawbacks are the reconfiguration of the device only when the failures in equipment related to the low order device, and assuming that the difference between the compensating and measuring voltages greater than LSB or less double the size of the Junior category, as well as the inability to function under failure in other places, except the youngest, for example, failure of the comparator.

The closest to the technical nature of the present device is a redundant analog-to-digital Converter - ADC (ed. St. USSR №1510084, CL H 03 M 1/46, 1986), contains two ADCS, the block forming the output code (switch), two differential amplifier, two Comparators and item I.

The disadvantages of redundant ADC are a large amount of precision elements: differential amplifiers, Comparators, the inability of each ADC with two sensors with the same accuracy, the inability to switch to the reserve in case of failure of elements of one's overall self-control, lack of self-control of each ADC in the process of its functionality is the formation, the inability to work the device in case of failure of the two Comparators of the ADC at the same time.

The objective of the proposed device is to increase fault tolerance and, consequently, increasing the reliability and validity of the proposed conversion of the ADC, which is to expand the functionality converts voltage into the code when working in the modes of parallel and / or serial polling of the two sensors and allows you to quickly reconfigure the device in case of failure on the self-monitoring results in the process of functioning of each ADC.

The problem is solved in that in the proposed dual-redundant ADC containing the first and second ADCS, is made identical with the means of self-control with output bus "unfit", the first analog inputs two ADC respectively connected to the outputs of the first and second sensors input signals, the outputs of the two ADCS are respectively connected to first and second input of the first switch, the outputs of which are output buses, the first and second control inputs of the ADC respectively connected to input tire "reset" and "start converting"entered the second switch, identical to the first control unit, the first and the second inputs of which are respectively connected to input tire "reset" and "h is a principle of transformation", the third, fourth, fifth and sixth inputs of the control unit respectively connected to the output tyres zero, the unit outputs two triggers memory faults in sequential mode, the first and second ADC", seventh and eighth inputs of the control unit respectively connected to the output tires "not available-1" and "unfit-2" of the first and second ADCS and second inputs respectively of the first and second switches, the first control unit is connected with the third control input of the ADC and switches, the second output control unit connected to the fourth control input of the first ADC and the second switch, the third output the control unit is connected with the fourth control input of the second ADC and the first switch, the outputs of the first and second ADC respectively connected to the fifth input of the second and first switches and the second analog inputs of the first, second ADC respectively connected to the outputs of the second and first sensors input signals.

The control unit in the proposed ADC includes first and second elements And the first inputs of which are connected to the input bus "start conversion", the second inputs respectively connected to the unit and zero outputs of the first flip-flop, the output of the first element And connected to the first input of the third element And the first input of the first element OR the first input is AMI fourth, the fifth element And the output of the second element And is connected to a single input of the first flip-flop and the first input of the second element OR the second input is connected to the output of the third element And the second and third inputs of which are respectively connected to the zero outputs of the second and third triggers, isolated outputs which are respectively connected to output bus "serial " mode 1", "serial mode No. 2", the output of the second element OR is connected to a single input of the fourth flip-flop, single output of which is connected to the output bus "parallel mode", the second input of the first element OR is connected to the input bus "reset", with zero inputs of the second, third and triggers the first input of the third element OR the second input is connected to the single input of the second trigger and the output of the fourth element, And the third input of the third element OR is connected to a single input of the third trigger, and with the release of the fifth element And the output of the third element OR connected to the zero input of the fourth flip-flop, a second input of the fourth and fifth elements And respectively connected to input tyres zero outputs of the triggers of memory failure of successive regimes of the first and second ADC", the third inputs of the fourth and fifth elements And respectively connected to the outputs fourth, patagioenas OR the first inputs are connected to the output of the sixth element And the first input of the seventh element And second inputs respectively connected to input tire "unfit-1", "not available-2", the first, second inputs of the sixth element, And the second and third inputs of the seventh element And respectively connected to input tire single outputs of triggers memory failure of successive regimes of the first and second ADC, and the output of the seventh element And is connected to the output bus failure.

The first ADC contains four comparator, the input of which pairs respectively connected to first and second input buses, the second inputs of the first and second Comparators connected to the output of the first m-bit resistive matrix R-2R, (m+1)-th resistor 2R which is connected to a source of reference voltage of positive polarity, the second inputs of the second and fourth Comparators connected to the output of the second m-bit resistive matrix R-2R, (m+1)-th resistor 2R which is connected to a source of reference voltage of negative polarity, the input m-bit resistive matrices R-2R from the first to the m through electronic switches connected to the outputs of successive approximations register with first through n, and inputs the switching of electronic switches respectively connected to the Cabinet bus and the source of reference voltage of polozhitelneishie, the outputs of the four Comparators respectively connected with the first inputs of the first four elements And the second inputs of the first and second elements And is connected to the input bus of the "parallel mode", the second inputs of the third and fourth elements And is connected to the input bus "serial " mode 1", the outputs of the second and fourth elements And respectively connected to corresponding inputs of the first element OR the output of which is connected to the first input of the fifth element And through the first element, NOT to the first input of the second element OR the second and third inputs of which are respectively connected to the outputs of the first and third elements And the output of the second element OR connected to the second input of the fifth element And to the first inputs of the sixth and seventh elements, And through the second element is NOT connected to the first input of the third element OR the second inputs of the sixth and seventh elements And respectively connected to the second inputs of the first, second, third, fourth element And the third inputs of the sixth and seventh elements And is connected to the output of the delay element, the input of which is connected to the n-output of the successive approximations register, whose input is connected to the output of the pulse generator, the D input to the output of the fifth element And the inputto the Cabinet bus, a the entrance to the zero output of the first trigger unit whose input is connected to the output of the eighth element And the first input of which is connected to the input bus "start conversion", the second input to the zero output of the second trigger, the first inputs of the ninth group of elements And an output bus "zero trigger output memory fault serial mode No. 1", the output of the sixth element And connected to the second input of the third element OR a single input of the third trigger, the output of the seventh element And connected to a single input of the second trigger and a third input of the third element OR the output of which is connected to the zero input the first trigger input bus reset is connected to the zero inputs of the second and third triggers, isolated inputs which are respectively connected with the output tires "single trigger output memory fault serial mode No. 1", "not available-1", the second inputs of the ninth group of elements And is connected to the zero output of the second trigger, the third inputs connected respectively to the outputs of successive approximations register with first through n, and the outputs of the ninth group of elements are the outputs of the ADC.

The first switch is made on the item is NOT, the group of n elements OR two groups of n elements each, where n is the number of bits of the ADC, the input elements of the first group connected to the first input bus unit, a second bus which is not good-1" through the element is NOT connected to the second inputs of elements And the first group, the third inputs of which are connected with the third bus unit, the output from the first inputs of n elements OR, the second inputs of which are connected to the outputs of n elements And a second group whose inputs are respectively connected with the second, fourth and fifth tyre unit, and outputs n elements OR are output by the bus device.

The essence of the invention is illustrated by drawings.

Figure 1 shows the block diagram of the device dual redundant analog-to-digital conversion, figure 2 - diagram of the ADC, figure 3 - diagram of the control unit 4 is a diagram of the first switch 5 is a diagram of the second switch 6 is a diagram of the m-bit resistive matrix R-2R.

Figure 1-5 shows:

1, 2 - the first, the second sensor input signals,

3 is a control block

4 - the first ADC,

5 is a first switch,

6 - second ADC,

7 - second switch

8...11 - blocks comparison,

12 - the first m-bit resistive matrix R-2R,

13 is a source of reference voltage of positive polarity,

14 - second m-bit resistive matrix R-2R,

15 is a source of reference voltage of negative polarity,

16...19 - items

20 analog electronic key,

21 - items

the 22 - item,OR

23 - g is nerator pulses,

24 - successive approximations register,

25 - item,

the 26 - item is NOT,

27 - element OR,

28 - delay element,

29, 30 elements,And

31 - the item is NOT,

32...34 - triggers

35 - element OR,

36 - item,

37..39 - items

40..43 - triggers

44, 45 elements,OR

46...50 items

51, 52 elements OR,

53 - the first group of n elements And,

54 - group of n elements,OR

55 - the item is NOT,

56 - the second group of n elements And,

57 - the third group of n elements And,

58 is a group of n elements,OR

59 - the item is NOT,

60 - the fourth group of n elements I.

The device (1) contains the measured signals 1, 2, control unit 3, the first ADC 4, the first switch 5, the second ADC 6, the second switch 7.

The first and second ADCS are made identical (figure 2), each of them contains blocks comparison 8...11, the first m-bit resistive matrix R-2R 12, a source of reference voltage of positive polarity 13, the second m-bit resistive matrix R-2R 14, a source of reference voltage of negative polarity 15, elements, And 16..19, analog electronic key 20, the And gate 21, the element OR 22, the pulse generator 23, the successive approximations register 24, the And gate 25, item NO 26, item 27, a delay element 28, the elements 29, 30, NO element 31, the trigger 32..34, item 35, item 36. Resistive the matrix R-2R 12 and 14 are identical, and their scheme is shown in Fig.6.

The control unit (figure 3) contains elements And 37...39, triggers 40...43, items, OR 44, 45, elements, And 46...50 items OR 51, 52.

The first switch (figure 4) contains the first group of n elements And 53, the group of n elements OR 54, NO element 55, a second group of n elements And 56.

The second switch (figure 5) contains the first group of n elements And 57, the group of n elements OR 58, NO element 59, a second group of n elements And 60.

The device operates as follows. The signal "reset"is generated when the power device is set to "0" triggers, units 3, 4 and 6. The signal "start conversion" (NP), arriving at the inputs of blocks 3, 4 and 6, sets the parallel poll sensors 1, 2 (when the blocks 4, 6 at the same time produce the encoding voltage respectively from the sensors 1, 2), and in blocks 4 and 6 begins the process of converting the measured signal into a binary code with a reduced cycle coding and self-control. Blocks 4 and 6 form the signal "end of conversion"as soon as the difference between the enclosure and the measured signal is less than the voltage of the LSB. Upon completion of the conversion codes of the blocks 4, 6 through the respective switches 5, 7 are received at the output device and stored in buffer registers two external devices (WU), which is s in figure 1 is not shown. If the conversion process, for example, in unit 4 will be formed signal "no good" (NG-1), which is formed in the case of withdrawal within the specified tolerance of the measured signal, i.e. when UISM<Ucomp-UMLRor UISM>Ucomp+UMLRwhere UISM- the voltage of the measured signal, Ucompthe voltage compensating signal, and UMLR- voltage LSB, then this signal will set in block 3 of the trigger 42 in the state "1". This signal unit 6 switches the sequential polling of the sensor 1 second ADC (PCR 2). In each ADC serial mode running time is always after the parallel mode (Prr). As the signal of a single trigger output (TP1-1) 33 in block 4 block signal TM, the signal from the sensor 1 will go to the second input of U WH unit 6. After converting this signal into the code it is written through the switch 5 in the buffer register VO. The block 6 has already made the conversion signal from the sensor 2 in the code in the parallel mode, and it's stuck in the buffer register BV2. Similarly operates in sequential mode, poll sensor 2 unit 4 when forming unit 6 signal "no good" (NG-2). Then the unit 4 moves in the sequential polling of the sensor 2, the first ADC (PSR), while block 4 is made of mo the Finance of the signal from the sensor 1 to the code in parallel mode and it's stuck in the buffer register WU 1.

Consider the work of one block of 4, a block diagram is shown in figure 2. The signal "reset"from the unit 4 sets the trigger 33, 34 in the state "0"and the signal of NP through the element 36 sets the trigger 32 in the state "1". From block 3 to block 4 receives an enable signal mode Prr At level "0" at the inputs of the register 24andthe trigger register 24 is set in the initial state and inputs 1...m is the code 0111..1. The operation of the register 24 will be supplied from the blocks 9, 10 items 16, 17, 22, 24, 25, 26 and 27. As soon as the second input element 25 is formed level "0", the conversion process will end, and the trigger 32 through the elements 31 and 35 are set to "0". Level "0" at the output of the element 27 is formed under the condition Ucomp-UMLR<UISM<Ucomp+UMLR. The output code is removed from the register 24 and through the elements 21 and the respective blocks 5, 7 arrives at a given WU.

If the conversion process balancing the measured signal compensating did not, the element 29 at the n-th stage with the required time delay, determined by the element 28, generates a signal " no good" (NG-1 and NG-2), which will set the trigger 34 in the state "1", and the trigger 32 in the state "0". With block 3 mode Prr removed, and established the W mode PSR 2. In unit 4 permit levels are fed to the inputs of the elements 8, 11, and the inputs of the elements 9, 10 - prohibiting the level "0". The operation unit 4 will be from units 8, 11, items 18, 19, 22, 25, 26 and 27 is similar to mode Prr if in this mode of operation, the balancing of the measured signal compensating did not, the element 30 at the n-th stage with the necessary delay defined by the element 28 will set the trigger 33 is in the state "1". When this signal with a single trigger output 33 (TPO1-1) enters the unit 3 to control the operation of the device. When operable unit 4 sequentially output code is removed from the register 24 through the elements 21 and enters the external device.

The block diagram of the control unit 3 is shown in figure 3. The signal "reset"is entered in block 3, sets the trigger 40.....43 in the state "0"and the signal of TMS (the first pulse with a delay relative to the signal "reset" through the element 39 will set the trigger 43 to "1"state, a trigger 40 through the elements 38, 44 will be set in "1"state, i.e. in the mode Prr Second pulse signal NP sets the trigger 41 or 42 in the mode PSR or PSR 2 depending on the refusal of the block 4 or 6 mode Prr generation in unit 4 signal NG-1, provided that in the block 6, the trigger 33 is in the state "0", the block 4 is set to the mode PSR 2. In the case of the forms of the simulation in section 6 signal NG-2 provided in block 4, the trigger 33 is in the state "0"in block 3 is set to the mode PSR. In case of failure of one of the blocks 4 or 6 mode PSR 1 or PSR 2 one of the functional blocks of 4 or 6 continues to operate, the signal FAILURE is generated, subject to the availability of all signals NG-1, NG-2, TPO1-1, TPO2-1(meaning that trigger a memory fault 33 of the second ADC is in the state "1").

Block diagram of two identical digital switches 5 and 7 are shown in figure 4, 5. Consider the one - block 5 in figure 4. Mode Prr output code from block of 4 (CODE 1) is supplied to the elements 53 ( their number is determined by the bit output code m, and ADC m is equal to the bit output register n). In this scheme n elements 53 are represented as one element 53 that is associated with a code bus (the /character). In the presence of permissive levels " 1" to the second inputs of the elements 53 (when no signal NG-1 and the presence of signal PRN) CODE-1 through the elements 53, 54 enters the buffer register VO. Mode PSR 2 when forming unit 4 signal NG-1 elements 56 will act to permit the levels "1" (in the presence of signals NG-1 and PCR 2). CODE-2 from block 6, is proportional to the analog signal from the sensor 1 through the elements 56, 54 enters the buffer register VO. Similarly operates the second switch 7.

Thus, by offering the first ADC is a fault-tolerant, allows to increase the reliability and validity of the conversion due to the ADC work in two modes: parallel and serial and prompt them to change the results of the self-control of each ADC. The structure of the proposed ADC is based on the substitution of any one unhealthy ADC is operable according to the results of self-monitoring (during operation) with the corresponding transition from a survey of the sensor in parallel to the survey sensor in a sequential mode in case of failure of another parallel channel. For example, if the first ADC in parallel will form the signal "NG-1", this signal of the second ADC switches to serial poll the sensor D1 (when saving survey in parallel mode, sensor 2). If, for example, the second ADC in parallel will form the signal "NG-2", on this signal, the first ADC switches to serial poll the sensor D2 (when saving survey in the parallel channel sensor 1). If you refuse two ADCS in parallel, then in serial modes, the first ADC will convert the information from the sensor 2 and the second ADC - sensor D1. When the above reconfiguration does not decrease the accuracy of the conversion, the gain in the use of equipment will be approximately 1.5 times higher h is m in the method duplication ADC (taking into account the complexity of the ADC due to the introduction of two additional Comparators, four schemes And the trigger and injection control unit).

For example, for the worst case, when 10-bit ADC is performed on the functional elements in accordance with figure 2, 3 (excluding integrated chipsets) and given that two of the shaping unit of the output block duplicate ADC ADC ( D) the composition of the elements are approximately equal to two switches dual redundant ADC (ADC-R), the number of cells in 4 ADC-D is 39×4=156, and 2 ADC-R 44×2=88 (given that 4-th comparator are placed in one housing, for example, chip SA), and the number of elements of the control unit equal to 16 elements, then win () to use equipment from the use of this device in comparison with a method of duplicating the ADC will be:

In=156/88+16=1,5.

Each ADC in both parallel and serial modes have the self-control of operation of the ADC, which is combined with the conversion process, and is not an additional operation after converting the signals into the code in the main unit of self-control for the two ADC as in the prototype. In addition, regardless of the fault code from each ADC is always supplied through the switch in its "own" the buffer register. At the same time when the majority of the reservation on the principle of voting "n" failure occurs when K-1 operable ADC.

Implemented the e of the proposed ADC in various electronic systems will significantly (approximately twofold) increase mean time between failures and reduce maintenance costs.

1. Dual redundant analog-to-digital Converter comprising first and second ADCS, are made identical, the first analog inputs two ADC respectively connected to the outputs of the first and second sensors input signals, the output of the first ADC connected to the first input of the first switch, the outputs of which are output buses, the first and second control inputs of the two ADCS are respectively connected to input tire “reset” and “start conversion”, characterized in that it introduced the second switch and the control unit, the first and second inputs of which are respectively connected to input tire “reset” and “start conversion”the third and fourth inputs of the control unit respectively connected to the zero and single output buses of the first ADC, fifth and sixth inputs of the control unit respectively connected to the zero and single output buses of the second ADC, the seventh input of the control unit is connected to the output bus is not available-1” of the first ADC, the eighth input of the control unit is connected to the output bus “unfit-2” of the second ADC, also referred bus is connected with the second inputs respectively of the first and second switches, the first control unit is connected with the third control inputs of both ADC and switches, the second output control unit connected to the fourth is passed control inputs of the first ADC and the second switch, the third output control unit connected to the fourth control inputs of the second ADC and the first switch, the output of the second ADC is connected to the first input of the second switch and the fifth input of the first switch, the output of the first ADC, coupled to the first input of the first switch, is connected to the fifth input of the second switch, the outputs of which are output by the tire, the second analog inputs of the first and second ADC respectively connected to the outputs of the second and first sensors input signals.

2. The Converter according to claim 1, characterized in that the control unit contains the first and second elements And the first inputs of which are connected to the input bus “start conversion”, the second inputs respectively connected to the unit and zero outputs of the first flip-flop, the output of the first element And connected to the first input of the third element And the first input of the first element OR the first inputs of the fourth and fifth elements And the output of the second element And is connected to a single input of the first flip-flop and the first input of the second element OR the second input is connected to the output of the third element And the second and third inputs of which respectively connected to the zero outputs of the second and third triggers, isolated outputs which are respectively connected to output bus “serial " mode 1”, “sequence is entrusted mode No. 2”, the output of the second element OR is connected to a single input of the fourth flip-flop, single output of which is connected to the output bus “parallel mode”, the second input of the first element OR is connected to the input bus reset, with zero inputs of the second, third and triggers the first input of the third element OR the second input is connected to the single input of the second trigger and the output of the fourth element, And the third input of the third element OR is connected to a single input of the third trigger, and with the release of the fifth element And the output of the third element OR connected to the zero input of the fourth flip-flop, a second input of the fourth, fifth elements And respectively connected to input tyres zero outputs of the triggers of memory failure of successive regimes of the first and second ADC”, the third inputs of the fourth and fifth elements And respectively connected to the outputs of the fourth and fifth elements OR, the input of which is connected to the output of the sixth element And the first input of the seventh element And second inputs respectively connected to input tire “unfit-1”, “not available-2”, the first, second inputs of the sixth element, And the second and third inputs of the seventh element And connected to the respective input buses single outputs of triggers memory the failure of successive regimes of the first and second is th ADC”, and the output of the seventh element And is connected to the output bus failure.

3. The Converter according to claim 1 characterized in that the first ADC contains four comparator, the input of which pairs respectively connected to first and second input buses, the second inputs of the first and second Comparators connected to the output of the first m-bit resistive matrix R-2R, (m+1)-th resistor 2R which is connected to a source of reference voltage of positive polarity, the second inputs of the second and fourth Comparators connected to the output of the second m-bit resistor matrix R-2R, (m+1)-th resistor 2R which is connected to a source of reference voltage of negative polarity, the input m-bit resistive matrix R-2R from the first to the m through electronic switches connected to the outputs of successive approximations register with first through n, and inputs the switching of electronic switches respectively connected to the Cabinet bus and the source of reference voltage of positive polarity, the outputs of the four Comparators respectively connected with the first inputs of the first four elements And the second inputs of the first and second elements And is connected to the input bus of the “parallel mode”, the second inputs of the third and fourth elements And is connected to the input bus “serial " mode 1”, the outputs of the second and fourth items respectively connected to the corresponding inputs of the first element OR the output of which is connected to the first input of the fifth element And through the first element, NOT to the first input of the second element OR the second and third inputs of which are respectively connected to the outputs of the first and third elements And the output of the second element OR connected to the second input of the fifth element And to the first inputs of the sixth and seventh elements, And through the second element is NOT connected to the first input of the third element OR the second inputs of the sixth and seventh elements And respectively connected to the second inputs of the first, second, third, fourth element And the third inputs of the sixth and seventh elements And connected to the output of the delay element, the input of which is connected to the n-output of the successive approximations register, whose input is connected to the output of the pulse generator, the D input to the output of the fifth element And the entranceto the Cabinet bus, athe entrance to the zero output of the first trigger unit whose input is connected to the output of the eighth element And the first input of which is connected to the input bus “start conversion”, the second input to the zero output of the second trigger, the first inputs of the ninth group of elements And an output bus “zero trigger output memory fault serial mode No. 1”, the output of the sixth element And PADCO is dinen to the second input of the third element OR a single input of the third trigger, the output of the seventh element And connected to a single input of the second trigger and a third input of the third element OR the output of which is connected to the zero input of the first trigger input bus reset is connected to the zero inputs of the second and third triggers, isolated outputs which are respectively connected with the output tires “single trigger output memory fault serial mode No. 1” and “unfit-1, the second input of the ninth group of elements And is connected to the zero output of the second trigger, the third inputs connected respectively to the outputs of successive approximations register with first through n, and the outputs of the ninth group of elements And are the outputs of the ADC.

4. The Converter according to claim 1, characterized in that the first switch is made on the item is NOT, the group of n elements OR two groups of n elements each, the input elements And the first group is connected to the first input bus unit, a second bus which is not good-1” through the element is NOT connected to the second inputs of elements And the first group, the third inputs of which are connected with the third bus unit, the output from the first inputs of n elements OR, the second inputs of which are connected to the outputs of n elements And a second group whose inputs are respectively connected with the second, fourth and fifth tyre unit, and outputs n elements OR are output to the other device.



 

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1 cl, 2 dwg

FIELD: electronic engineering.

SUBSTANCE: device has a setoff transducers kinematically connected to gantry shaft, angular information transformer, code transducer, adder, control unit, clock pulse oscillator, delay circuit, binary pulse counter, two static registers, digital comparator line and RAM unit.

EFFECT: high transformation accuracy.

3 dwg

FIELD: electronic engineering.

SUBSTANCE: device has coordinate scale having raster and code path of which the first one is represented as a chain of windows forming regular raster and the second one is represented as a chain of code windows, reading unit having illumination unit, analyzing raster mask, raster path photodetectors, and multi-element raster path photodetector. The raster path photodetectors, and multi-element raster path photodetector are connected to recording and analyzing unit, respectively. The reading unit has analyzing code mask being two window paths arranged so that succession period is a multiple of code step and window width is equal to the code step. The windows on the paths are shifted by a value equal to half code step.

EFFECT: eliminated ambiguity in reading coordinate code; high performance and accuracy.

3 cl, 6 dwg

FIELD: computer engineering; data processing devices.

SUBSTANCE: proposed angle-of-turn-to-code converter has synchro resolver sensors, switching unit, inverter, two adding amplifiers, two integrators, functional voltage-to-code converter, threshold elements, 4NAND gate, integrator triggering and stopping unit, and counter.

EFFECT: enhanced precision characteristics of converter.

1 cl, 1 dwg

FIELD: computer engineering.

SUBSTANCE: proposed device that can be used in high-reliability computer-aided monitoring, data processing and acquisition systems has two analog-to-digital converters, two switching units, two sensors, and control unit. This device is characterized in low failure probability, reliability of conversion when implementing structure of analog-to-digital computer capable of operation in two modes of parallel and/or serial polling of sensors, and in ability of its on-line reconfiguration in the event of failure by self-check results of each analog-to-digital converter.

EFFECT: enlarged functional capabilities, extended mean time between failures, reduced maintenance charges.

4 cl, 6 dwg

FIELD: computer science.

SUBSTANCE: method includes forming of two supporting harmonic oscillations and where t - time of production from supporting oscillation of harmonic oscillation and from harmonic oscillation - oscillation and determining multiplication result integral for these oscillations: where Tu - integration interval.

EFFECT: higher precision, higher speed of operation.

2 dwg

FIELD: control systems.

SUBSTANCE: device has sensors block, block for forming signals of azimuth binary code, two adders, strobes forming block, control block, rotation imitator, correction code detector, clock pulse generator, binary counter, multiplexer, operative and constant memory devices, static register.

EFFECT: higher speed of operation.

4 dwg

FIELD: computer engineering; angle-of-turn-to-code converters and data processing systems.

SUBSTANCE: proposed converter has synchro resolver transducers, switching unit, four integrators, voltage-to-code ratio functional converter, threshold elements, 4AND-NOT gate, integrator start and stop unit, counter, two inverters, two selector switches, and NOT gate.

EFFECT: enhanced speed of converter.

1 cl, 2 dwg

FIELD: measuring equipment for information controlling of predetermined tillage depth.

SUBSTANCE: apparatus has primary information sensor with two sensitive members connected to different circuits of digital RC-generator of rectangular pulse connected in series with frequency divider and with frequency meter, control unit, reference signal generator, two differential amplifiers, demodulator, comparison circuits and two actuating mechanisms. Control unit is connected to RC-generator, frequency meter and reference signal generator. Actuating mechanism is connected through comparison circuit to demodulator whose inputs are connected through differential amplifier to frequency divider and reference signal generator. Output signal is determined from formula.

EFFECT: increased precision and wider operational capabilities of automatic controlling of predetermined tillage depth.

1 dwg

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