Successive-action analog-to-digital converter

FIELD: digital technology; conversion of analog voltage to digital code.

SUBSTANCE: proposed converter has differential amplifiers, comparator, dc amplifier, analog memory device, control device, serial-to-parallel code converter, modulo M counter, switches, inverter, and input stage for determining polarity and inverting negative voltages.

EFFECT: enhanced bit capacity at high speed and simple architecture of converter.

1 cl, 2 dwg

 

The device relates to the field of digital technology, in particular to devices convert the analog voltage into a digital code.

In the process of digital processing various kinds of signals the first is the task of converting an analog signal such as voltage in digital form.

There are a large number of different schemes (see, e.g., 1-8) analog-to-digital converters (ADC). Their main characteristics are speed (conversion rate) and the bit width conversion (attainable number of bits in the output digital code) with sound economic criteria.

Known direct conversion ADC [6-7], in which the input analog signal is compared in (2N-1) Comparators with the same number of reference voltages that differ by an integer number of steps equal to the price LSB of output code. They offer the best performance. Their disadvantage is the complexity and high cost of manufacture, rapidly growing with increasing number of digits. Their width does not exceed 8 ([3], pp. 3, 9).

Known for integrating ADC ([3], page 4, 9, [5]), in which the input signal is integrated for a fixed period of time, and then desintegrated reference voltage; the result is obtained as the ratio of the interval decomposition to intervals in the y integration. They can provide a sufficiently high capacity of integration and good economic efficiency, but their main disadvantage is the low speed.

Known Sigma-Delta ADC ([3], pages 5, 9, [4]), which is based on Sigma-Delta modulators and accounts of clock pulses, following with a very high frequency, followed by digital filtering and decimation (decimate) counts obtained the required digital sampling. These ADCS offer the high bit depth conversion (24 or more bits); disadvantages of poor performance, only slightly exceeding the performance of the integrating ADC, and the complexity of the architecture that entails high demands on the technology of production and consequently higher cost.

Known ADC with bitwise weighing, also known as successive approximation ADC ([3], pages 3, 9, [2]), containing the successive approximations register (PSC), digital to analog Converter (DAC), a comparator, and a control circuit which sequentially formed in the upper grades PSC code using the DAC is converted into an analog value, which comparator compares the input signal and the sign of the output voltage of the comparator control circuit generates a signal (the log. 1 or 0) for entries in the following category PSC. These ADCS provide discharge the awn conversion 10-12 digits and high performance with good economic performance. However, a further increase in capacity and performance in ADC of this type is associated with very large production difficulties, leading to a sharp increase in their value.

Known pipeline (pipeline) ADC ([3], pages 5, 9), containing several series-connected stages, the last stage is loaded on accurate ADC. Each stage contains a 4-bit ADC, the code output of which is fed to logic correction and calibration and to the DAC, which converts the code to an analog signal which is subtracted from the input analog signal, and the remainder is fed to the amplifier with a fixed gain, the output of which is connected to the input of the next stage. The exact output of the DAC is also served on the schema correction and calibration, which are used for correction codes from the previous stages on the codes later and accurate ADC. The output of this logic circuit through the driver gives a complete code sample. According to [3], this ADC has a speed exceeding the speed of the ADC, successive approximation, and the bit output code from 12 to 16 bits. The disadvantage of this ADC is the complexity of the architecture and the ensuing problems of manufacture.

Known ADC [1], adopted for the prototype refers to the chain (conveyor) ADC, and comprises N serially connected tnotification by the number of bits of the output code and the source reference (reference) voltage U 0(IAN), the sign of which coincides with the sign of the input voltage. Each of the N stages includes a differential (operational) amplifier (DN) with a gain of 2, the comparator (COM) and two keys, the control input of the first stage is the input of the ADC, the output DN of the N-th cascade is an analog output of the ADC serving to build a chain of analog-to-digital conversion, and direct entry DN is connected to the direct input KOHM, inputs KΩ connected with IAN, output COM, which is also a digital output of the ADC is connected with the control input of the first key and through the inverter with the control input of the second key. The input of the first key is connected with IAN, the input of the second key is connected to a common bus (ground), and outputs the keys are interconnected and connected to the inverting input of the remote control. This ADC has a high speed, but its main disadvantage is its high requirements for the process (very high precision adjustment component), resulting in lower economic performance.

The essence of the proposed device is to create adequate modern technology ADC, providing the highest achievement potential indicator of the criterion of “complexity - cost - effectiveness”, i.e. providing maximum efficiency with minimum cost and complexity of production is DSTV. The main technical result of the proposed device is increased by the bit analog-to-digital conversion while maintaining a sufficiently high performance and simplifying its architecture by eliminating from the prototype chain of similar cascades (only one left) and the introduction of analog storage devices (ABC), the DC amplifier (UPT), control unit (CU), Converter serial code in parallel (FCIS) and counter modulo M (CM), where M is the number of bits of the conversion; the entered input cascade determine the sign of the input signal and inverting the latter when it is negative.

The technical result is achieved as follows.

ADC successive steps (PD) contains one cascade chain ADC, including differential (operational) amplifier (DN) with a gain of 2, the comparator (COM), two keys and IAN, direct entry DN, which is the ADC input is connected to the direct input KOHM, inputs KΩ connected to the input of the first key and IAN, output COM, which is also a digital (bit) ADC output connected with the control output of the first key and through the inverter with the control output of the second key, the input of which is connected to the shared bus (earth), the key outputs are connected to the inverting input of the remote control. With the purpose of is especiany health ADC when removing chains of similar cascades it introduced three additional key two switched ABC, SU, FCIS, CM and UPT gain of the voltage is equal to the unit, and direct inputs of the remote control and COM are connected to the input of the first ABC and through the third and fourth keys from the input source and output UPT accordingly, the output DN is connected via the fifth key from the input of the second ABC and entrance UPT, information input FCIS connected to the output of WHOM, the first output of the SU is connected with the control output of the third key, the second output of the SU is connected with the control output of the fourth key, the third output of the SU is connected with the control output of the fifth key, a clock input FCIS and with a counter input CM, the fourth output of the SU is connected to the input of the reset CM, and the output of the overflow CM connected with the control input of the SU.

General block diagram of the ADC PD is shown in figure 1, figure 2 illustrates his work.

ADC PD contains: 1, 2, 3, 4, 5 - keys; 6 - differential amplifier (DN) with a gain of 2; 7, a comparator (COM); 8 - a DC amplifier (UPT) with a gain of 1; 9 - inverter; 10, 11 - analog storage device (ABC); 12 - the control unit (CU); 13 - Converter serial code in parallel (FCIS); 14 - counter modulo M (CM); input cascade determine the sign and invert the negative voltage.

The operation of the device is illustrated by diagrams of the output signals of the SU.

Devices which works as follows (figure 2).

In the initial state SU 12 is not running, the potentials at the outputs unchanged, with the first and third outputs are equal to one on the second to zero. Under the action of these potentials 3 third and fifth 5 will be permanently closed (open), and the fourth 4 - open (closed). The input analog signal is fed to the input of the first ABC 10, in which it is stored, and direct inputs DN 6 and COM 7, which compares the voltage of this signal with the reference voltage U0; the last value is chosen equal to the price of big-endian (for example, half of the maximum value of the input voltage). If the input voltage exceeds U0at the exit KΩ 7 appears logical (log.) 1, which will reveal the key 1 and (via inverter 9) closes the key 2; thus, the inverting input DN 6 will be submitted to the reference voltage U0. If the input voltage is less than U0at the exit KΩ 7 will log. 0, which will close the key 1 and open up key 2: inverting input remote control 6 in this case will be filed with the voltage equal to 0. Thus, at the output of WHOM 7 appears the value of the first (senior) level of the output code, and remote control 6 will produce a subtraction filed its inverse input voltage (U0or 0) from the input and will increase in 2 times the voltage difference on forward and inverse input; in any case this difference is largest on agesa less rates of discharge (in the limiting case, equal). Output voltage control 6 is fed through a public key 5 to the input of the second ABC 11, where it is stored and fed to the input of the UPT 8.

Thus, the claimed ADC distinguished by the simplicity of the architecture. Its structure does not depend on the number of bits of the output code and contains the smallest in comparison with the known ADC number of adjustable elements. It is consistent (bitwise) processing the input signal, as in ADC with bitwise weights, hence the claimed ADC will have the same performance. Obviously, as ABC advisable to use capacitors of appropriate capacity. An additional advantage of the inventive ADC is that it does not require any additional external devices sample-and-hold.

SOURCES of INFORMATION

I. the Prototype and analogues:

1. Certificate of utility model No. 18330, IPC H 03 M 1/00, publ. 10.06.2001: BIPM, 2001, No. 16, s (prototype).

2. AS the USSR №1677872, IPC H 03 M 1/18, publ. 20.08.99: BI No. 23, 1999, s-339 (similar).

II. Additional sources of prior art:

3. Pipeline ADCs come of age. Maxim Engineering Journal, 1999, vol. 33.

4. RF application No. 98101746 IPC H 03 M 3/00, 3/04, publ. 20.11.99: BI, 1999, No. 32, p.63.

5. Pat. Of the Russian Federation No. 2101859 IPC H 03 M 1/48, publ. 10.01.98: BI, 1998, No. 1, s.

6. Pat. Of the Russian Federation No. 2110886 IPC H 03 M 1/34, publ. 10.05.98: BI, 1998, No. 13, s.

7. Pat. Of the Russian Federation No. 2107388 IPC H 03 M 1/10, publ. 20.03.98: BI, 1998, No. 8, p.50.

8. RF application No. 96101790 IPC H 03 M 1/34, publ. 20.03.98: BI, 1998, No. 8, s-177.

Analog-to-digital Converter (ADC) serial operation (PD)containing a differential amplifier (DU), a comparator (COM), two key, the inverter, the source of reference voltage (IAN), direct inputs K and DN is connected to the input source, output COM, which is a bit ADC output connected with the control output of the first key and through the inverter with the control output of the second key, the first key and the inverting input KΩ connected to IAN, the input of the second key is connected with ground wire (earth), the outputs of keys connected to the inverting input DU, characterized in that it additionally introduced three keys, a DC amplifier (UPT) with a gain of 1, two analog storage device (ABC), the control unit (CU), counter digits modulo M (CM), where M is the number of digits conversion and Converter serial code in parallel (FCIS), and the third key is included between the input source and direct inputs DN and C which are connected to the input of the first ABC and the output of the fourth key, the output control, the gain is equal to 2, is connected with the entrance of the fifth key, the output of which is connected to the input of the second ABC and the input of the UPT, the yield of the latter is connected to the input of chetvert what about the key, the first and second outputs of the SU are connected respectively with the control pins of the third and fourth keys, the third output of the SU is connected with the control output of the fifth key with a counter input CM and a clock input FCIS, an information input connected to the output of the COM, the fourth output of the SU is connected to the input of the reset CM, and the output of the overflow of the latter is connected to the control input of the SU.



 

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