High-speed analogue-to-digital converter with differential input

IPC classes for russian patent High-speed analogue-to-digital converter with differential input (RU 2513716):

H03M1/36 - CODING, DECODING OR CODE CONVERSION, IN GENERAL (using fluidic means F15C0004000000; optical analogue/digital converters G02F0007000000; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

Another patents in same IPC classes:

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High-speed analogue-digital-analogue converter with non-clock bitwise balancing / 2491715

Device includes an input signal source, adders, a buffer amplifier, relay elements, n proportional links, n switch elements, a reference digital code source, a code subtracting device, n-1 dynamic D flip-flops, a monovibrator and a code comparing device.

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FIELD: radio engineering, communication.

SUBSTANCE: unlike the existing high-speed analogue-to-digital converter with a differential input, in the present invention a first input voltage source is connected to the input of a first additional buffer amplifier, the output of which is connected to first inputs of each voltage comparator through corresponding balancing capacitors of a first group, and the second input antiphase voltage source is connected to the input of a second additional buffer amplifier, the output of which is connected to second inputs of each voltage comparator through corresponding balancing capacitors of a second group.

EFFECT: multifold expansion of the frequency range of processed input signals of an analogue-to-digital converter by reducing the transmission error of input differential voltages from sources to voltage comparator inputs.

2 cl, 8 dwg

The present invention relates to the field of measurement and computer engineering, radio engineering, communications and can be used in the structure of different processing devices analog information, measuring instruments, systems, telecommunications, etc.

In the modern technology have found an extensive use of parallel analog-to-digital converters (ADCS) with differential input, providing the highest conversion speed analog signals (u_Idigital signals [1-9]. With increasing frequency of the input voltage u_Iin such microelectronic ADC substantial conversion error due to the influence of parasitic capacitors formed by the containers on a substrate of active and passive components [8-9]. A further increase in speed parallel ADC is one of the problems of modern information and measuring equipment, which will enable the practical implementation of new communication and telecommunication systems with higher quality characteristics.

Closest to the technical nature of the claimed device is parallel ADC, described in the patent firm of IHP (Germany) DE 10 2009 002 062 fig.1, fig.2. Analysis of the limiting frequency range (f_vmagthe input signals, and also attempts to increase the f_vmagdue to the opt is minimize the absolute values of the resistance of the reference resistors articles [8-9], including co-author of this application [9].

ADC prototype figure 1 contains the first 1, the input buffer amplifier, the input of which is connected with the first 2 input source voltage, and the output connected with the first 3 reference current through the first group of N series-connected reference resistors, including the first (4.1) of the reference resistor, the second (4.2) of the reference resistor and the N-th (4.N) of the reference resistor, the second 5, the input buffer amplifier, the input of which is connected with the second 6 source phase with the input voltage, and the output associated with the second 7 reference current through the second group of N series-connected reference resistors, including the first (8.1) of the reference resistor, the second (8.2) of the reference resistor and the N-th (8.N) of the reference resistor, the first 9 of the voltage comparator, the first 10 input connected to the output of the first 1, the buffer amplifier and the second input 11 is connected to the common node of the second 7 reference current and the N-th (8.N) of the reference resistor of the second group, 12 second voltage comparator, the first 13 an input connected to a common node of the first (4.1) and second (4.2) of the reference resistors of the first group and the second input 14 is connected to the common node of the N-th (8.N) and second (8.2) of the reference resistors of the second group, the third 15 a voltage comparator, the first 16 input connected to a common node of the second (4.2) and the N-th (4.N) this is ones of the resistors of the first group, and the second input 17 is connected to the common node of the second (8.2) and the first (8.1) of the reference resistors of the second group, the N-th 18 the voltage comparator, the first 19 whose input is connected to a common node of the first 3 of the reference current and the N-th (4.N) of the reference resistor of the first group and the second input 20 is connected to the output 5 second buffer amplifier, the parasitic capacitors associated with the inputs of each of the voltage Comparators 9, 12, 15, 18.

A significant disadvantage of the ADC prototype (figure 1) is that it limits the frequency range conversion analog input signals to digital (even when implemented on microwave transistors with f_max=200 GHz process SGB25H1, IHP, Germany [8,9]) is limited due to decrease at high frequencies the gain of the signal with the ADC inputs 2 and 6 to the inputs of voltage Comparators 9, 12, 15, 18.

The main objective of the proposed invention is to increase several times the limit of the frequency range of the processed input signals of the ADC by reducing the errors of the transmission input differential voltages from sources 2, 6 to the inputs of voltage Comparators 9, 12, 15, 18.

This object is achieved in that the analog-to-digital Converter 1, 1 containing the first input buffer amplifier, the input of which is connected with the first 2 input source voltage,and the output connected with the first 3 reference current through the first group of N series-connected reference resistors, including the first (4.1) of the reference resistor, the second (4.2) of the reference resistor and the N-th (4.N) of the reference resistor, the second 5, the input buffer amplifier, the input of which is connected with the second 6 source phase with the input voltage, and the output associated with the second 7 reference current through the second group of N series-connected reference resistors, including the first (8.1) of the reference resistor, the second (8.2) of the reference resistor and the N-th (8.N) of the reference resistor, the first 9 of the voltage comparator, the first 10 input connected to the output of the first buffer 1 amplifier and the second input 11 is connected to the common node of the second 7 reference current and the N-th (8.N) of the reference resistor of the second group, 12 second voltage comparator, the first 13 an input connected to a common node of the first (4.1) and second (4.2) of the reference resistors of the first group and the second input 14 is connected to the common node of the N-th (8.N) and second (8.2) of the reference resistors of the second group, the third 15 a voltage comparator, the first 16 input connected to a common node of the second (4.2) and N (4.N) reference resistors of the first group and the second input 17 is connected to the common node of the second (8.2) and the first (8.1) of the reference resistors of the second group, the N-th 18 the voltage comparator, the first 19 whose input is connected to a common node of the first 3 of the reference current and the N-th (4.N) of the reference resistor of the first group and the second input is 20 connected to the second output 5 of the buffer amplifier, the parasitic capacitors associated with the inputs of each of the voltage Comparators 9, 12, 15, 18, there are new elements and connections of the first 2 source of input voltage connected to the input of the first 21 additional buffer amplifier, the output of which is connected with the first 10,13.16,19 inputs of each of the voltage Comparators 9, 12, 15, 18 through appropriate corrective capacitors of the first group 22, 23, 24, 25, and the second 6 the input phase voltage is connected to the input 26 of the second additional buffer amplifier, the output of which is connected with the second 11, 14, 17, 20 inputs of each of the voltage Comparators 9, 12, 15, 18 through appropriate corrective capacitors of the second group 27, 28, 29, 30.

Figure 1 shows a diagram of the ADC prototype.

2 shows the diagram of the inventive device in accordance with claim 1 of the claims.

Figure 3 and figure 4 shows a section of the inventive device 2 in accordance with claim 2.

Figure 5 presents a diagram of the inventive ADC 2 in the Cadence environment models SiGe transistors (npn 200-n; the process SG25H1, IHP, Ik.max=4 mA. A high-performance 0.25 µm technology with npn-HBTs up to f_T/f_max=180/220 GHz) when using the ideal source of reference current 3 and 7 (figure 2).

Figure 6 shows the logarithmic amplitude-frequency characteristic of the transfer coefficients of the analog section of the ADC 5 of Suhodol 2 and 6 to the inputs of voltage Comparators 9, 12, 15, 18 (K1, K2, K3, K4). From these charts, it follows that by introducing new relations significantly (from 0.6 GHz to 10.4 GHz, i.e. in 17 times) extends the frequency range within which the ratio voltage analog section differs from the low value of not more than 1 dB. On the data graphs also show that the scheme ADC prototype transfer coefficient significantly decreases when f>0,GGC. This observed asymmetry of the transfer coefficients of the different Comparators (K1, K2, and K3, K4). This effect in the inventive device is missing.

Figure 7 presents a diagram of the inventive device 2 in the Cadence environment models SiGe transistors (npn 200-n; the process SG25H1, IHP, Ik.max=4 mA. A high-performance 0.25 µm technology with npn-HBTs up to f_T/f_max=180/220 GHz) for the case when taken into account the parasitic capacity of the source reference current (C_p=300 FF), which corresponds to the sum of capacitances to the substrate and the capacitance of the collector-base real transistors of this circuit.

On Fig given logarithmic amplitude-frequency characteristic of the transfer coefficients of the analog sections of the ADC 7 input 2 and 6 to the inputs of voltage Comparators 9, 12, 15, 18 (K1, K2, K3, K4). From these charts, it follows that for large tanks source reference current (300 FF) operating frequency range declared ADC extends from 0.19 GHz to 4.0 GHz, so what. more than 21 times. The coefficients of the transfer to the inputs of each comparator (K1, K2, K3, K4) are slightly different from each other in a wide frequency range.

Thus, from the graphs 6 and Fig with different combinations of parasitic capacitances (i.e. depending on the technology used and the properties of passive and active components) the proposed solution provides the extension limit of the operating frequency range of the processed ADC input signals.

High-speed analog-to-digital Converter with a differential input figure 2 contains the first 1, the input buffer amplifier, the input of which is connected with the first 2 input source voltage, and the output connected with the first 3 reference current through the first group of N series-connected reference resistors, including the first (4.1) of the reference resistor, the second (4.2) of the reference resistor and the N-th (4.N) of the reference resistor, the second 5, the input buffer amplifier, the input of which is connected with the second 6 source phase with the input voltage, and the output associated with the second 7 reference current through the second group of N sequentially connected reference resistors, including the first (8.1) of the reference resistor, the second (8.2) of the reference resistor and the N-th (8.N) of the reference resistor, the first 9 of the voltage comparator, the first 10 entrance that is on is connected to the output of the first 1, the buffer amplifier, and the second input 11 is connected to the common node of the second 7 reference current and the N-th (8.N) of the reference resistor of the second group, 12 second voltage comparator, the first 13 an input connected to a common node of the first (4.1) and second (4.2) of the reference resistors of the first group and the second input 14 is connected to the common node of the N-th (8.N) and second (8.2) of the reference resistors of the second group, the third 15 a voltage comparator, the first 16 input connected to a common node of the second (4.2) and the N-th (4.N) the reference resistors of the first group and the second input 17 is connected to the common node of the second (8.2) and the first (8.1) of the reference resistors of the second group, the N-th 18 the voltage comparator, the first 19 whose input is connected to a common node of the first 3 of the reference current and the N-th (4.N) of the reference resistor of the first group and the second input 20 is connected to the output 5 second buffer amplifier, the parasitic capacitors associated with the inputs of each of the voltage Comparators 9, 12, 15, 18. The first 2 source of input voltage connected to the input of the first 21 additional buffer amplifier, the output of which is connected with the first 10,13.16,19 inputs of each of the voltage Comparators 9, 12, 15, 18 through appropriate corrective capacitors of the first group 22, 23, 24, 25, and the second 6 the input phase voltage is connected to the input 26 of the second additional buffer amplifier, the output of which contact the n with the second 11, 14, 17, 20 inputs of each of the voltage Comparators 9, 12, 15, 18 through appropriate corrective capacitors of the second group 27, 28, 29, 30. Capacitors 31÷34 in the circuit of figure 2 model the impact on the operation of the ADC circuit stray capacitance to the substrate used reference resistors 4.1, 4.2, 4.N and the input capacitances of the Comparators 9, 12, 15, 16.

In the drawings, figure 3 and figure 4, in accordance with claim 2, in series with each adjustment of the first capacitor (22, 23, 24, 25) and second (27, 28, 29, 30) groups include those additional adjustment resistors 35, 36, 37, 38 (Fig 3) and 39, 40, 41, 42 (figure 4).

Figure 4 capacitors 43, 44, 45, 46 simulate parasitic capacitance at the inputs of the voltage Comparators 9, 12, 15, 18 (2).

Consider the ADC prototype 1 in the field of high frequency input signals.

The ADC prototype figure 1 the performance of the analog part (its limiting frequency range f_vmag) is determined by the parasitic capacitances 31÷34 and 43÷44. Almost upper cutoff frequency level -1 dB ADC prototype does not exceed 700 MHz (6,_to=0), while the performance of the applicable Comparators 9, 12, 15, 18, realized at microwave SiGe transistors [8,9] with f_T=200 GHz, allows you to work in a wider frequency range.

In the inventive device 2 by introducing a correction capacitors 22, 23, 24, 25, and 2, 28, 29, 30, the operating frequency range of the analog section of the ADC is expanding more than an order of magnitude (6). This allows analog-to-digital conversion of the higher frequency input signals.

The formation of the digital equivalent of the input differential voltage in this ADC is provided by the traditional method by analysis of the output logic level of the voltage Comparators 9, 12, 15, 18.

Introduction sequentially correcting the first capacitors (22, 23, 24, 25) and second (27, 28, 29, 30) groups additional adjustment resistors (figure 3, figure 4) allows you to optimize the flatness of the amplitude-frequency characteristics of the analog part of the ADC, which creates conditions for further expansion of its marginal frequency range (Fig).

Reviewed ADC provides even greater relative winning frequency range (from 0.19 GHz to 4.0 GHz) using reference sources current 3 and 7 with higher capacity on a substrate With a_p=300 FF.

Thus, the inventive device is characterized by significant advantages in comparison with the prototype over the frequency range of the processed signals.

Sources of information

1. Patent US 5.589.831.

2. Patent US 5.231.399.

3. Patent US 6.437.724 fig.4.

4. Patent US 7.394.420 fig.2.

5. Patent application US 2008/0036536 fig.43.

6. Patent US 4.63.106.

7. Patent US 4.912.469 fig.1.

8. Y.Borokhovych. 4-bit, 16 GS/s ADC with new Parallel Reference Network / Y.Borokhovych, H. Gustat, C.Scheytt // COMCAS 2009 - 2009 IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems.

9. Serebryakov A.I. Method of improving performance of a parallel ADC / Ahikereru, E.B. Borokhovich // Solid-state electronics. Complex functional blocks REA: materials of the scientific-technical conference. - M.: MENTORES them. A.S. Popov, 2012. - P.150-155.

1. High-speed analog-to-digital Converter with a differential input, containing the first (1) input buffer amplifier, whose input is connected to the first (2) a source of input voltage and output associated with the first (3) a reference current through the first group of N series-connected reference resistors, including the first (4.1) of the reference resistor, the second (4.2) of the reference resistor and the N-th (4.N) of the reference resistor, the second (5), the input buffer amplifier, the input of which is connected with the second (6) source of phase with the input voltage, and the output is connected with the second (7) a reference current through the second group of N series-connected reference resistors, including the first (8.1) of the reference resistor, the second (8.2) of the reference resistor and the N-th (8.N) of the reference resistor, the first (9) the voltage comparator, the first (10) input connected to the output of the first (1) of the buffer amplifier, and the second I is d (11) is connected to the common node of the second (7) reference current and the N-th (8.N) of the reference resistor of the second group, the second (12) of the voltage comparator, the first (13) the input of which is connected to a common node of the first (4.1) and second (4.2) of the reference resistors of the first group and the second input (14) is connected to the common node of the N-th (8.N) and second (8.2) of the reference resistors of the second group, the third (15) of the voltage comparator, the first (16) the input of which is connected to a common node of the second (4.2) and the N-th (4.N) reference resistors of the first group and the second input (17) is connected to the common node the second (8.2) and the first (8.1) of the reference resistors of the second group, N-th (18) the voltage comparator, the first (19) the input of which is connected to a common node of the first (3) reference current and the N-th (4.N) of the reference resistor of the first group and the second input (20) is connected to the output of the second (5) of the buffer amplifier, the parasitic capacitors associated with the inputs of each of the voltage Comparators(9), (12), (15), (18), characterized in that the first (2) the source of input voltage connected to the input of the first (21) additional buffer amplifier, the output of which is connected with the first(10), (13), (16), (19) the inputs of each of the voltage Comparators(9), (12), (15), (18) through appropriate corrective capacitors of the first group(22, 23, 24, 25), and the second (6) the input phase voltage is connected to the input of the second (26) additional buffer amplifier, the output of which is connected with the second(11), (14), (17), (20) the inputs of each of Comparators e.g. the supply (9), (12), (15), (18) through appropriate corrective capacitors of the second group(27, 28, 29, 30).

2. High-speed analog-to-digital Converter with a differential input according to claim 1, characterized in that in series with each adjustment of the first capacitor (22, 23, 24, 25) and second (27, 28, 29, 30) groups included additional adjustment resistors.