Programmable logic device. RU patent 2503993.
 Method of facilitating multiplication of floating-point numbers represented in residue number system / 2500018Method comprises steps of: concurrently writing the remainder on base p1 of a multiplicand in memory elements; concurrently counting the number of units bi in each column of the i-th matrix; shifting the binary number b1 one bit to the right; summing with a number b2; shifting the obtained sum b 2 s one bit to the right and summing with a number b3. Similarly, the obtained sums are shifted and summed with subsequent numbers to obtain a sum b 2 * m − 1 s , wherein the least significant bit of the number b1 is the first multiplication bit s1, the least significant bit of each obtained sum b i s is the i-th multiplication bit. The binary number b 2 * m − 1 s is shifted; the least significant bit of the obtained number is the (2*m)-th bit of the determined product s2*m. If s is greater than p1, the obtained product s is corrected by successive subtraction of the base p1 from s until s is less than p1, otherwise correction is not performed; similarly, products of m-bit residues on the rest of the bases are calculated and corrected; the powers of multipliers are simultaneously summed up and the resultant sum is the power of the determined product. |
 Method of exact division of integer binary numbers, starting from least significant bit / 2498393Method includes stages, at which a divisor is recorded in parallel into matrix cells on memory elements, the first bit of the quotient becomes equal to the sum of module two of the least significant bit in the first column of the matrix and the first bit of the dividend, other bits of the quotient become equal to zero; the number of units b2 is counted in a vector equal to bit-by-bit logical multiplication of the appropriate bits of the second column of the matrix and bits of the quotient, at the same time the second bit of the quotient becomes equal to the sum of module two for the least significant bit b2 and the second bit of the dividend; similarly, the number of units bi is counted in a vector, which is equal to the bit-by-bit logical multiplication of the appropriate bits of the i column of the matrix and quotient bits, afterwards the sum ci of the vector bi and the vector bi-1 shifted by one bit to the right is calculated, at the same time the i bit of the quotient becomes equal to the sum of module two of the least significant bit ci and the i bit of the dividend, as a result the m-bit quotient of initial numbers will be generated. |
 Device to predict exceptional situation "accuracy loss" of "multiplication with accumulation" operation unit / 2498392Device comprises a subblock of prediction of a sum of fractional parts, a counter of senior zeros of the sum of fractional parts, registers of fractional parts of numbers, input registers of number exponents, a counter of junior zeros of the summand fractional parts, a subblock of calculation of a shift of levelling and prediction of a shift of preliminary normalisation, a comparator of early loss of accuracy, a counter of junior zeros of a sum of fractional parts, a comparator of late loss of accuracy. |
 Logic module / 2497181Logic module has six closing switches and six opening switches. |
 Apparatus for boundary composite coding in interval computations / 2497180Apparatus includes flip-flops, registers, ROM, subtractors, adders, multiplexers, shifters, a comparator unit, modulo two adders, AND and OR elements and a priority encoder. |
 Apparatus for decoding jointly stored boundaries in interval computations / 2497179Apparatus includes an encoder, a decoder unit, ROM, shifters, subtractors, multiplexers, an adder, modulo two adders, an inverter, AND and OR elements. |
 Method by kuvyrkov for information processing and calculation (versions) and device "generaliser" for method realisation / 2494445In one of versions the method includes parallel-serial processing of a signal in a block of triggers of an input register; in a matrix device; in a unit of logical elements, preferably logical elements "AND"; in a unit of triggers of an output register. At the same time the signal processing in the matrix device is performed in accordance with the geometric model of the signal processing, representing a combination of graphs that forms at least one right triangle, which is divided into three parts, with lines stretching from the tops of the triangle angles. |
 Logic processor / 2491613Disclosed is a logic processor designed to execute eight simple symmetrical Boolean functions which depend on eight arguments - input binary signals, which can be used in digital computer systems as a code converting means, and also having nineteen computational cells (11,…,119), each having an OR element (2) and an AND element (3). |
 System and method for adaptive prioritisation of antivirus scanning objects / 2491611System for adaptive prioritisation of antivirus scanning objects includes a rule setting device which sets rules for prioritising antivirus scanning objects, a rule database for storing prioritisation rules and providing rule data to a queuing device. The system also includes an analyser which determines parameters of antivirus scanning objects required for prioritisation and sends said parameters to the queuing device. The queuing device is designed to assign priority and a scanning method with defined parameters in accordance with set rules. The queuing device also constructs a queue in accordance with the assigned priorities and sends the queue to a malicious object detecting device. The malicious object detecting device performs antivirus scanning of the scanning queue in accordance with the scanning method assigned for each object and sends the scanning results to a scanning result analyser. |
 Methods and systems for implementing approximate string matching within database / 2487394Method for character string matching of a candidate character string with a plurality of character string records stored within a database involves identifying a set of reference character strings in the database. The reference character strings are identified using an optimised search for a set of dissimilar character strings. An n-gram representation of each of the reference character strings in the set of reference character strings is generated and an n-gram representation of the candidate character string is also generated. Further, similarity between n-gram representations of each of the reference character strings and the candidate character string is determined. The candidate character string in the database is indexed based on the determined similarities between the n-gram representation of the candidate character string and the reference character strings in the identified set. |
 Pulse code transformer / 2248607Device has information input device, clock generator, connected to address counter with decoder, outputs of which are connected to inputs of recording device, inputs of which are connected to output of programming device, signal generator and multiplexers. Device for recording object sate is connected to output of decoder of cells address of device. Signal generator includes cells for recording checksum. First input of signals generator is connected to output of decoder of address of cells of checksum, second input - to output of recording device, first output - to first inputs of multiplexers, and second output - to first input of binary adder, by its output connected to third input of signal generator and checksum. Outputs of decoder of checksum cells address and decoder of object state recording device cells addresses are connected to second output of address counter, which is connected to second inputs of multiplexers. Recording device is programmable. |
 Homogenous substance cell / 2251140In a cell, containing seven inputs, eight OR elements, ten AND elements, three outputs by its adjustment different combination variants of connections of inputs to cell outputs are provided, to provide for calculation of Boolean formulae systems from classes of non-repeated orderly and disorderly formulae. |
 Homogenous substance cell / 2251141Cell has eight outputs, forty-five AND elements, three OR elements, three inputs. |
 Method for automatic detection of current state during multi- parameter comparison / 2255368Method includes forming parameters aij for each object, where i - object number, , and j - parameter number , normalization of values of objects parameters relatively to maximal value for each object and calculation of value of vector Vi in space of n parameters according to formula , where with following recording and comparison of vectors values. Normalization relatively to value of maximal parameter allows to exclude wrong estimation of object state. |
 Logical module / 2262733Device has two majority elements, while output of first majority element is connected to second input of second majority element, connected by first, third inputs and an output respectively to second superstructure, third information inputs and output of logical module, first, second information and first superstructure inputs of which are formed by respectively second, third and first inputs of first majority element. |
 Logical calculator / 2262734Device has n logical modules, each of which has two AND elements, OR element and two D-triggers. |
 Device for correcting order of a result of summing of floating point numbers / 2267806Device has order correction adder, block for forming scaling signal, resolution inputs for scaling result, limiting and order correction codes of which are, respectively, first, second, and third inputs of device, and output is connected to first information input of order correction adder, second information input of which is fourth input of device, third input of device is connected to third information input of order correction adder, output of which is device output. |
 Spatial commutation structure / 2270474Spatial commutation structure has programmable commutation environment, groups of outputs of which are electrically connected to groups of outputs for connecting typical replacement elements. It is made in form of a polyhedron with n sides, on which groups of outputs are mounted for connecting typical replacement elements, while programmable commutation environment is positioned in the center of polyhedron. Second variant is different because spatial commutation structure is made in form of polyhedron with n sides, circling line of which approaches a spheroid shape. Groups of outputs of programmable commutation environment in accordance to both variants are electrically connected to groups of outputs for connecting typical replacement elements by means of conductors, positioned in appropriate radially positioned channels. |
 Combination type adder / 2275676Device has two RS-triggers, seven AND elements, seven OR elements, four NOT elements, seven control buses, transfer bus. |
 Logical calculator / 2276399Logical calculating device for realization of n simple Boolean functions depending on n arguments - input binary signals contains (n-1) elements AND, (n-1) OR elements and (n-1) D-triggers. |
FIELD: information technology.
SUBSTANCE: device includes groups of D flip-flops, function calculating units, a counter, a decoder, conjunction units, conjunction value units, wherein the function calculating units, conjunction units and conjunction value units are based on 2·2NOT-AND-OR elements which execute the function
EFFECT: reducing hardware costs when designing circuits for logic functions with a large number of variables.
4 dwg, 8 tbl
The invention relates to the computer engineering and may be used for computing logic functions on a fault-tolerant hardware.
Known programmable logic device containing n g- items And (n - number of information of the device inputs, 2≅g≅2 n ), t elements OR (t - number of information outputs of the device), first, second and third group D-flip-flops, the first group of items with three-state output, the group of items IS NOT a three-state output, g·t two-input elements, And the counter and decoder, first, second and third RS-triggers an additional element OR a second group of elements And three-state output (.. USSR №1444892, cl. G11C 17/00, G06F 7/00, 1988).
The disadvantages of this device are the poor performance computing logic functions in case of failures and high hardware expenses on realization of systems of Boolean functions due to the use of standard logic of the bases.