RussianPatents.com
|
Homogenous substance cell. RU patent 2251140. |
|
FIELD: computer science. SUBSTANCE: in a cell, containing seven inputs, eight OR elements, ten AND elements, three outputs by its adjustment different combination variants of connections of inputs to cell outputs are provided, to provide for calculation of Boolean formulae systems from classes of non-repeated orderly and disorderly formulae. EFFECT: broader functional capabilities. 13 dwg
|
Random series generator / 2250489 Device has random numbers source, N-digit selector-multiplexer, RAM, ranges control block, generations number control block, J-input OR element, AND elements block. Because series of given values of data set is broken in ranges and frequency of their appearance is set within certain limits, random series is generated with distribution law, presented in form of ranges. |
Data processing method / 2250488 Signals from each two bits of code of inputted data are converted to 1 of 4 code, calculations in said code are performed in accordance to operation code, result signals in said code are recorded, recorded signals are inputted into code control device and in case of mismatch error signal is generated and processing result output is blocked. |
Divider based on neurons / 2249846 Device has separator register block, data input block, divided part register block, block for sum and forming digits of result of division, block for analysis of digit grid overflow, block for recording remainder, block for recording result of division, control block. |
Multiplier based on neurons / 2249845 Device has data input block, multiplied part register, multiplying part register, adder block, block for analyzing multiplying part digit, storage block, control block, threshold elements, neurons. Multiplication operation is performed by analyzing higher digits of multiplying part with displacement of multiplied part to the right. Combination blocks provide for parallel, digit-wise production of multiplication result digits. |
Logic module / 2249844 Logic module has And element, first, second majority elements, OR element, three data inputs and two adjustment inputs. |
Pulse code transformer / 2248607 Device has information input device, clock generator, connected to address counter with decoder, outputs of which are connected to inputs of recording device, inputs of which are connected to output of programming device, signal generator and multiplexers. Device for recording object sate is connected to output of decoder of cells address of device. Signal generator includes cells for recording checksum. First input of signals generator is connected to output of decoder of address of cells of checksum, second input - to output of recording device, first output - to first inputs of multiplexers, and second output - to first input of binary adder, by its output connected to third input of signal generator and checksum. Outputs of decoder of checksum cells address and decoder of object state recording device cells addresses are connected to second output of address counter, which is connected to second inputs of multiplexers. Recording device is programmable. |
Logical calculator / 2248036 Device has 2n AND elements, n OR elements, n D-triggers. |
Symmetric module / 2248035 Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered And element is connected to first input of i-numbered OR element, connected by second input to data input of i-numbered D-trigger, setting input and clock input of which are connected respectively to first and second control inputs of module, connected by i-numbered information input to first input of i-numbered And element, second input of which is connected to non-inverse output of i-numbered D-trigger, output of each previous OR element is connected to second input of following OR element, and second input of first and output of n-numbered OR elements are connected respectively to zero potential bus and module output. |
Logical converter / 2248034 Device has eleven majority elements, four information inputs, two adjustment inputs. |
Device for scaling number in modular scale of notation / 2246753 Device has N blocks for calculating remainders, each of which has N devices for calculating remainders from bases of modular notation scale, including multiplication blocks, module adders of 3N numbers and tabular calculators. |
Multilevel m-dimensional matrix adding structure for vertical arithmetic / 2246128 Into multilevel m-dimensional matrix adding structure, containing one-digit adding nodes of first, second and third levels, m-dimensional matrix structures for one-digit adding of second, third and fourth level are inserted, which form hierarchical multilevel adding structure of vertical arithmetic, representing a regular hierarchical logarithmical structure connected along vertical line, with inter-level links, along horizontal line - matrix structure, wherein matrix structures of previous levels, connected by links, form a matrix structure of next hierarchical level of multilevel m-dimensional matrix structure. |
Random numbers generation method / 2246129 Method includes generating random numbers with use of displacement register with check connection, elementary digit of which is a q-based symbol (q=2l, l - binary symbol length) at length of q-based digits register, in check connection networks nonlinear two-parameter operations on q-based symbols F (ub, ud) are used, on basis of random replacement tables, for generating next random number values z1=F(ui, uj), z2=F(ut, um), zg=F(z1, z2) are calculated, where ui, uj, ut, um - values of filling of respective register digits, value of result in check connection networks zg is recorded to g digit of displacement register and is a next result of random numbers generation, after which displacement of register contents for one q-based digit is performed. |
Device for sorting numbers / 2246750 Device has n analysis blocks, each of which contains two And elements, two groups of AND elements, OR element, comparison circuit and register, commutation trigger, control trigger, delay element, AND-NOT element, AND elements, pulse generator. |
High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751 System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states. |
Parallel subtractor-adder on neurons / 2246752 Device has numbers input block, comparison block, greater number register, adding-subtracting block, least number register block, result register block, control block. |
Device for scaling number in modular scale of notation / 2246753 Device has N blocks for calculating remainders, each of which has N devices for calculating remainders from bases of modular notation scale, including multiplication blocks, module adders of 3N numbers and tabular calculators. |
Logical converter / 2248034 Device has eleven majority elements, four information inputs, two adjustment inputs. |
Symmetric module / 2248035 Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered And element is connected to first input of i-numbered OR element, connected by second input to data input of i-numbered D-trigger, setting input and clock input of which are connected respectively to first and second control inputs of module, connected by i-numbered information input to first input of i-numbered And element, second input of which is connected to non-inverse output of i-numbered D-trigger, output of each previous OR element is connected to second input of following OR element, and second input of first and output of n-numbered OR elements are connected respectively to zero potential bus and module output. |
Logical calculator / 2248036 Device has 2n AND elements, n OR elements, n D-triggers. |
Pulse code transformer / 2248607 Device has information input device, clock generator, connected to address counter with decoder, outputs of which are connected to inputs of recording device, inputs of which are connected to output of programming device, signal generator and multiplexers. Device for recording object sate is connected to output of decoder of cells address of device. Signal generator includes cells for recording checksum. First input of signals generator is connected to output of decoder of address of cells of checksum, second input - to output of recording device, first output - to first inputs of multiplexers, and second output - to first input of binary adder, by its output connected to third input of signal generator and checksum. Outputs of decoder of checksum cells address and decoder of object state recording device cells addresses are connected to second output of address counter, which is connected to second inputs of multiplexers. Recording device is programmable. |
© 2013-2014 Russian business network RussianPatents.com - Special Russian commercial information project for world wide. Foreign filing in English. |