Logical module

IPC classes for russian patent Logical module (RU 2262733):

G06F7 - Methods or arrangements for processing data by operating upon the order or content of the data handled (logic circuits H03K0019000000)

Another patents in same IPC classes:

Device for selecting minimal or maximal numeric value of two n-digit numbers / 2262130
Device has numeric conversion block for converting numbers to digit-wise signals, block for forming selection strobes, commutator of selection of minimal or maximal number.

Accumulation-type adder / 2261469
Device has in each digit one RS trigger, eight AND elements, five OR elements, two NOT elements, nine control buses.

Method for word-logical presentation and analysis of dynamics of state of multi-parametric object or process / 2261468
Method includes processing all different parameters using a computer considering their type, mutual influence and contents in such a way, as for all information to have differentiating signs, excluding interference of solution variants, taken by analyst on basis of multi-parametric objects state. Transformation operation is performed by forming at output of mathematical models of phrase functions, activating generation of word-logical interpretations, showing complex estimation of multi-parametric space of intersection between classes of state of objects on basis of data of telemetric control or information, inputted from terminal systems.

Logical calculator / 2260837
Device has five OR elements, five AND elements, register, six closing and six opening keys.

Unary signals adder / 2260836
Device has n calculating cells, each of which consists of AND element and XOR element, n AND elements, n D-triggers.

Logical processor / 2260205
Device has closing and opening keys, register and calculating cells, each of which consists of OR element, AND element.

Parallel counter of single signals / 2260204
Device has seventeen XOR elements and thirteen AND elements.

Logic calculator / 2257608
Device has n computing cells, each of which has AND element, OR element, D-trigger.

Multilevel m-dimensional matrix adding structure for vertical arithmetic / 2246128
Into multilevel m-dimensional matrix adding structure, containing one-digit adding nodes of first, second and third levels, m-dimensional matrix structures for one-digit adding of second, third and fourth level are inserted, which form hierarchical multilevel adding structure of vertical arithmetic, representing a regular hierarchical logarithmical structure connected along vertical line, with inter-level links, along horizontal line - matrix structure, wherein matrix structures of previous levels, connected by links, form a matrix structure of next hierarchical level of multilevel m-dimensional matrix structure.

Random numbers generation method / 2246129
Method includes generating random numbers with use of displacement register with check connection, elementary digit of which is a q-based symbol (q=2^l, l - binary symbol length) at length of q-based digits register, in check connection networks nonlinear two-parameter operations on q-based symbols F (u_b, u_d) are used, on basis of random replacement tables, for generating next random number values z₁=F(u_i, u_j), z₂=F(u_t, u_m), z_g=F(z₁, z₂) are calculated, where u_i, u_j, u_t, u_m - values of filling of respective register digits, value of result in check connection networks z_g is recorded to g digit of displacement register and is a next result of random numbers generation, after which displacement of register contents for one q-based digit is performed.

Device for sorting numbers / 2246750
Device has n analysis blocks, each of which contains two And elements, two groups of AND elements, OR element, comparison circuit and register, commutation trigger, control trigger, delay element, AND-NOT element, AND elements, pulse generator.

High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751
System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states.

Parallel subtractor-adder on neurons / 2246752
Device has numbers input block, comparison block, greater number register, adding-subtracting block, least number register block, result register block, control block.

Device for scaling number in modular scale of notation / 2246753
Device has N blocks for calculating remainders, each of which has N devices for calculating remainders from bases of modular notation scale, including multiplication blocks, module adders of 3N numbers and tabular calculators.

Logical converter / 2248034
Device has eleven majority elements, four information inputs, two adjustment inputs.

Symmetric module / 2248035
Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered And element is connected to first input of i-numbered OR element, connected by second input to data input of i-numbered D-trigger, setting input and clock input of which are connected respectively to first and second control inputs of module, connected by i-numbered information input to first input of i-numbered And element, second input of which is connected to non-inverse output of i-numbered D-trigger, output of each previous OR element is connected to second input of following OR element, and second input of first and output of n-numbered OR elements are connected respectively to zero potential bus and module output.

Logical calculator / 2248036
Device has 2n AND elements, n OR elements, n D-triggers.

Pulse code transformer / 2248607
Device has information input device, clock generator, connected to address counter with decoder, outputs of which are connected to inputs of recording device, inputs of which are connected to output of programming device, signal generator and multiplexers. Device for recording object sate is connected to output of decoder of cells address of device. Signal generator includes cells for recording checksum. First input of signals generator is connected to output of decoder of address of cells of checksum, second input - to output of recording device, first output - to first inputs of multiplexers, and second output - to first input of binary adder, by its output connected to third input of signal generator and checksum. Outputs of decoder of checksum cells address and decoder of object state recording device cells addresses are connected to second output of address counter, which is connected to second inputs of multiplexers. Recording device is programmable.

FIELD: computer science.

SUBSTANCE: device has two majority elements, while output of first majority element is connected to second input of second majority element, connected by first, third inputs and an output respectively to second superstructure, third information inputs and output of logical module, first, second information and first superstructure inputs of which are formed by respectively second, third and first inputs of first majority element.

EFFECT: broader functional capabilities.

1 dwg

The invention relates to computer technology and can be used for building automation, functional units of the control systems and other

Known logical units (see, for example, figure 3.3 on page 39 in the book of Jakubaitis E.A. Asynchronous logic automata. Riga: zinatne, 1966), which implement a simple symmetric Boolean function τ₁=x₁∨x₂∨x₃that depends on three arguments - input binary signals x₁x₂x₃∈{0,1}.

For the reason that impede the achievement of specified following technical result when using known logic modules include limited functionality due to the fact that there is no implementation of other simple symmetric Boolean functions τ₂=x₁x₂∨x₂x₃∨x₂x₃and τ₃=x₁x₂x₃that depends on three arguments - input binary signals x₁, x₂, x₃∈{0,1}.

The closest device to the same destination to the claimed invention by the combination of features is adopted for the prototype logic module (see RIS on str in the book Digital and analog integrated circuits: Handbook / Sviatoslavsky, Lignosellus, Vigolana and other M.: Radio and communication, 1989)containing DV is a majority element, each of which implements a simple symmetric Boolean function τ₂=x₁x₂∨x₁x₃∨x₂x₃where x₁x₂x₃- the binary signals acting on the inputs of the element.

For the reason that impede the achievement of specified following technical result when using the prototype include limited functionality due to the fact that there is no implementation of a simple symmetric Boolean functions τ₁=x₁∨x₂∨x₃and τ₃=x₁x₂x₃.

The technical result of the invention is the extension of functionality by ensuring the implementation of any of the three simple symmetric Boolean functions that depend on three arguments - input binary signals.

This technical result in the implementation of the invention is achieved in that in the logic module containing two majority element, the peculiarity lies in the fact that the output of the first majority element is connected to a second input of the second majority element, connected first to third inputs and output respectively to the second configuration, a third information input and output logic module, the first, second information and the first tuning input of which is formed by cuts in estwenno second, the third and the first inputs of the first majority element.

The drawing shows the proposed scheme logic module.

The logic module includes first and second majoritarian elements 1₁and 1₂and the output of the element 1₁connected with the second input element 1₂connected first to third inputs and output respectively to the second configuration, a third information input and output logic module, the first, second information and the first tuning input of which is formed respectively second, third and first inputs of the element 1₁.

The work of the proposed logic module is as follows.

At its first, second, third information and the first, second tuning inputs are given correspondingly binary signals x₁, x₂, x₃∈{0,1} and y₁,₂∈{0,1}. Then the signal at the output is determined by the expression Z=y₂F∨y₂x₃∨Fx₃where F=y₁x₁∨y₁x₂∨x₁x₂. Thus, the proposed module will play operation

The above data allow us to conclude that the proposed logic module has a wider compared to the prototype functionality, as is provides an implementation of any of the three simple symmetric Boolean functions τ ₁=x₁∨x₂∨x₃that τ₂=x₁x₂∨x₁x₃∨x₂x₃that τ₃=x₁x₂x₃that depends on three arguments - input binary signals.

The logic module that is designed to implement any of the three simple symmetric Boolean functions that depend on three arguments - input binary signals containing two majority element, characterized in that the output of the first majority element is connected to a second input of the second majority element, connected first to third inputs and output respectively to the second configuration, a third information input and output logic module, the first, second information and the first tuning input of which is formed respectively second, third and first inputs of the first majority element.