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Logical calculator

IPC classes for russian patent Logical calculator (RU 2262734):

G06F7 - Methods or arrangements for processing data by operating upon the order or content of the data handled (logic circuits H03K0019000000)

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FIELD: computer science.

SUBSTANCE: device has n logical modules, each of which has two AND elements, OR element and two D-triggers.

EFFECT: broader functional capabilities.

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The invention relates to computer technology and can be used for building automation, functional units of the control systems and other

Known logic solvers (see, for example, in figure 1 the description of the invention to the patent of the Russian Federation 2124754, CL G 06 G 7/52, 1999), which can be used to implement any of the three simple symmetric Boolean functions that depend on three arguments - input binary signals

For the reason that impede the achievement of specified following technical result when using known logic solvers, is limited functionality due to the fact that there is no parallel implementation n simple symmetric Boolean functions that depend on n arguments - input binary signals

The closest device to the same destination to the claimed invention by the combination of features is adopted for the prototype logic solver (figure 1 in the description of the invention to the patent of the Russian Federation 2227931, CL G 06 F 7/00, 2004), which contains n logical units, and implements any of the n simple symmetric Boolean functions that depend on n arguments - input binary signals

For the reason that impede the achievement of specified below on the basis of the one result when using prototype refers limited functionality due to the fact that there is no parallel implementation n simple symmetric Boolean functions that depend on n arguments - input binary signals

The technical result of the invention is the extension of functionality by providing a parallel implementation of n simple symmetric Boolean functions that depend on n arguments - input binary signals.

This technical result in the implementation of the invention is achieved in that in a logical computer that contains n logical modules, each of which contains two elements And the element OR two D-flip-flop, each logic module output of the first element And connected to the first input of the second element And the second input of the OR element connected to the first input to the second input of the second element And the fifth input of the logic module, the third input and the first output of which is combined, a fourth input connected to the second input of the first element And the first and second inputs respectively formed United inputs installation and United clock inputs of D-flip-flops, the fifth input of each subsequent logic module is connected to a second output of the preceding logic module, and the fifth input of the first logic module is connected to the bus zero potential, the first inputs of all logic modules are combined to form the first control input logic solver, connected to the second Manager of the entrance to the joint second inputs of all logic modules, the peculiarity lies in the fact that each logic module non-inverting output and the data input of the first D-flip-flop are connected respectively to the first input of the first element And the third input of the logic module, the first, second, and third outputs, and the sixth input of which is formed respectively by the output of the second element And the output element OR reinvestiruet output and data input of the second D-flip-flop, a sixth input of each of the previous logic module is connected to the third output subsequent logic module, and the sixth input of the n-th logic module is connected to its second output, the third output of the i-ththe logic module is the i-th output of the logic solver.

Figure 1 and figure 2 presents respectively the proposed scheme logic solver and time diagrams of signals settings.

Logic solver contains logic modules 1₁,...,1_n. Each logical module contains two elements And 2₁and 2₂the element OR 3, two D-flip-flop 4₁and 4₂and data input and non-inverting output of D-flip-flop 4₁connected to the respectively with the third input of the logic module and the first input element 2 ₁connected to the second input and output, respectively, to the fourth input of the logic module and combined with the first input element 2₂, the second input element 3, the first input connected to the second input element 2₂and the fifth input of the logic module connected first, second, third outputs and the sixth input respectively to the output element 2₂the output element 3, not inverting output and the data input of D-flip-flop 4₂the input set and the clock input of which is connected respectively with the input set and the clock input of D-flip-flop 4₁and form respectively the first and second inputs of the logic module. The first output of each logic module is connected to its third input, a second output, and the sixth input of each of the previous logic module connected respectively to the fifth input and a third output of the subsequent logic module, and the fifth input module 1₁and the sixth input module 1_nconnected respectively with the bus zero potential and a second output module 1_nthe first inputs of all logic modules are combined to form the first control input logic solver that is connected to the i-thoutput and the second managing input respectively to the third module output 1_iand United to the second inputs of all logical the ski modules.

The work of the proposed logic solver is as follows. On the fourth inputs of the logic modules 1₁,...,1_nserved accordingly binary signals; on the first, second control inputs of the logic solver are given correspondingly of pulse signals(figure 2). Then the signals on the first, second, and third outputs of the logic module 1_iwill be determined by recurrent expressions

whereand q=j is the number of points in time t_jand(figure 2), Δt₄- the length of the delay introduced D-trigger 4₂;; W_0j=0;The period T of the signal y₂must satisfy the conditionwhere Δt₁that Δt₂and Δt₃there is duration of the delay introduced respectively D-trigger 4₁the elements of 2₁and 3. Since according to (1.1) are

then taking into account (1.2) we get

The following table shows the values of the expressions (2) and (1.3) for n=.

Thus, at the first, second,..., nth outputs of the proposed logic solver when q=n, respectively, have

where τ₁,...,τ_nthere is a simple symmetric Boolean functions (see str in the book Pospelov D.A. Logical methods of analysis and synthesis schemes. M: Energy, 1974).

The above data allow us to conclude that the proposed logic solver has a wider compared to the prototype functionality, as it provides a parallel implementation of n simple symmetric Boolean functions that depend on n arguments - input binary signals.

Logic solver, designed for parallel operation n simple symmetric Boolean functions that depend on n arguments - input binary signals containing n logic modules, each of which contains two elements And the element OR two D-flip-flop, each logic module output of the first element And connected to the first input of the second element And the second input of the OR element connected to the first input to the second input of the second element And the fifth input of the logic module, the third input and the first output of which is combined, a fourth input connected to the second input of the first element And the first and the second entrance is formed, respectively, are combined inputs installation and United clock inputs of D-flip-flops, the fifth input of each subsequent logic module is connected to a second output of the preceding logic module, and the fifth input of the first logic module connected to the bus zero potential, the first inputs of all logic modules are combined to form the first control input logic solver, connected to the second Manager of the entrance to the joint second inputs of all logic modules, wherein each logical module non-inverting output and the data input of the first D-flip-flop are connected respectively to the first input of the first element And the third input of the logic module, the first, second, and third outputs, and the sixth input of which is formed respectively by the output of the second element, And the output element OR reinvestiruet output and data input of the second D-flip-flop, a sixth input of each of the previous logic module is connected to the third output of the subsequent logic module, and the sixth input of the n-th logic module is connected to its second output, the third output of the i-th () logic module is the i-th output of the logic solver.