Spatial commutation structure
 Accumulating type adder / 2269153Adder has two RS-triggers, nine AND elements, five OR elements, NOT element, ten control buses. Adder performs operations of addition and subtraction, operations for bitwise shifting of code to left and right, inversion, two-module addition, logical addition and logical multiplication. |
 Arithmetic device / 2268482Device has twelve registers, three delay elements, three three-input subtracter-adders, nine subtracter-adders, six multiplication blocks, six decoders, control block, interface bus. |
 Method and device for generation of multiple bits of pseudo-noise series for each clock pulse by means of parallel calculation of bits / 2267807Beginning values of states are loaded in registers of parallel pseudo-noise generator, which immediately generates following n bits of pseudo-noise series, where n - arbitrary number, depending on required productiveness level. Then, first sub-portion of pseudo-noise generator in accordance to invention receives current state of pseudo-noise generator and outputs state of n bits pseudo-noise generator in the future. |
 Device for correcting order of a result of summing of floating point numbers / 2267806Device has order correction adder, block for forming scaling signal, resolution inputs for scaling result, limiting and order correction codes of which are, respectively, first, second, and third inputs of device, and output is connected to first information input of order correction adder, second information input of which is fourth input of device, third input of device is connected to third information input of order correction adder, output of which is device output. |
 Device for modeling mass service system / 2266557Device for modeling of mass service system has generators of request flows, counters of received requests, counters of refused requests, OR elements, AND elements, denying elements, random time delay blocks, reverse busy channels counter, reverse queue length counter, refuses flow generator, reverse counter of broken channels and an adder. |
 Multilevel m-dimensional vertical arithmetic computing structure / 2265239Multilevel m-dimensional matrix computing structure has m-dimensional matrix computing structures from first to m level, forming hierarchical multilevel computing structure of vertical arithmetic, in form of regular, vertical-lined, hierarchical logarithmic structure with inter-level links, along horizontal line m-dimensional matrix structure form hierarchical matrix structure, wherein matrix structures of previous levels, linked by links, form matrix structure of next hierarchical level of multilevel m-dimensional matrix structure. |
 Adder / 2264646In each digit device has two RS-triggers, eight logical elements AND, six logical elements OR, four logical elements NOT, seven control buses. |
 Device for sorting binary numbers / 2264645Device has n-1 logic modules, each of which has register, locking and unlocking keys, ROM device. |
 Device for adding n numbers by p modulus / 2263948Device has harmonic signal generator, controlled phase changers, means for measuring phase of harmonic signal, phase changers for fixed phase values, transformers of binary number code to unary in accordance to first and second sub-modules, coder and table calculation means. |
 Integer-valued high order multiplication with truncation and shift in architecture with one commands flow and multiple data flows / 2263947Method includes receipt of first operand, having first set of L data elements, receipt of second operand, having second set of L data elements, and multiplication of L data element pairs for forming a set of L multiplication results, while each of L pairs includes one data element from first set and second data element from appropriate position of data element from second set. Each of L multiplication results is truncated for forming of L truncated values, which are scaled for forming of L scaled values, for each of which truncation is performed for storing in destination place, while each truncated value should e kept in position of data element, appropriate for its data elements pair. |
 Multilevel m-dimensional matrix adding structure for vertical arithmetic / 2246128Into multilevel m-dimensional matrix adding structure, containing one-digit adding nodes of first, second and third levels, m-dimensional matrix structures for one-digit adding of second, third and fourth level are inserted, which form hierarchical multilevel adding structure of vertical arithmetic, representing a regular hierarchical logarithmical structure connected along vertical line, with inter-level links, along horizontal line - matrix structure, wherein matrix structures of previous levels, connected by links, form a matrix structure of next hierarchical level of multilevel m-dimensional matrix structure. |
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Random numbers generation method / 2246129 Method includes generating random numbers with use of displacement register with check connection, elementary digit of which is a q-based symbol (q=2l, l - binary symbol length) at length of q-based digits register, in check connection networks nonlinear two-parameter operations on q-based symbols F (ub, ud) are used, on basis of random replacement tables, for generating next random number values z1=F(ui, uj), z2=F(ut, um), zg=F(z1, z2) are calculated, where ui, uj, ut, um - values of filling of respective register digits, value of result in check connection networks zg is recorded to g digit of displacement register and is a next result of random numbers generation, after which displacement of register contents for one q-based digit is performed. |
 Device for sorting numbers / 2246750Device has n analysis blocks, each of which contains two And elements, two groups of AND elements, OR element, comparison circuit and register, commutation trigger, control trigger, delay element, AND-NOT element, AND elements, pulse generator. |
 High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states. |
 Parallel subtractor-adder on neurons / 2246752Device has numbers input block, comparison block, greater number register, adding-subtracting block, least number register block, result register block, control block. |
 Device for scaling number in modular scale of notation / 2246753Device has N blocks for calculating remainders, each of which has N devices for calculating remainders from bases of modular notation scale, including multiplication blocks, module adders of 3N numbers and tabular calculators. |
 Logical converter / 2248034Device has eleven majority elements, four information inputs, two adjustment inputs. |
 Symmetric module / 2248035Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered |
 Logical calculator / 2248036Device has 2n AND elements, n OR elements, n D-triggers. |
 Pulse code transformer / 2248607Device has information input device, clock generator, connected to address counter with decoder, outputs of which are connected to inputs of recording device, inputs of which are connected to output of programming device, signal generator and multiplexers. Device for recording object sate is connected to output of decoder of cells address of device. Signal generator includes cells for recording checksum. First input of signals generator is connected to output of decoder of address of cells of checksum, second input - to output of recording device, first output - to first inputs of multiplexers, and second output - to first input of binary adder, by its output connected to third input of signal generator and checksum. Outputs of decoder of checksum cells address and decoder of object state recording device cells addresses are connected to second output of address counter, which is connected to second inputs of multiplexers. Recording device is programmable. |
FIELD: computer science equipment engineering, possible use for engineering of VLSI, devices and systems.
SUBSTANCE: spatial commutation structure has programmable commutation environment, groups of outputs of which are electrically connected to groups of outputs for connecting typical replacement elements. It is made in form of a polyhedron with n sides, on which groups of outputs are mounted for connecting typical replacement elements, while programmable commutation environment is positioned in the center of polyhedron. Second variant is different because spatial commutation structure is made in form of polyhedron with n sides, circling line of which approaches a spheroid shape. Groups of outputs of programmable commutation environment in accordance to both variants are electrically connected to groups of outputs for connecting typical replacement elements by means of conductors, positioned in appropriate radially positioned channels.
EFFECT: increased resource of spatial commutation structure by amount of realized electrical connections and connected typical replacement elements and simplified manufacture technology.
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The invention relates to the field of computer engineering and can be used for designing VLSI devices and systems.
Known multilayer printed circuit boards (CMP)containing multiple metallization layers and groups of leads for connection of standard replacement elements: circuits, connectors, and other Electrical connections in the CMP receive the trace of the printed conductors on the area of each layer and the connection of fragments of printed conductors on different layers, for example through plated holes.
Known programmable switching matrix (PCM), selected as a prototype containing programmable switching environment, the group's conclusions which are electrically connected with leads for connection of standard elements replacement [www: Aptix. ru]. PKM made under sub-micron technologies and contains multiple layers of metallization. Electrical connections in the PCM receives the connection of fragments of printed conductors by switching bidirectional keys located on the area of each layer of metallization and between metallization layers in a certain optimal way.
In known devices the existing level of technology has restrictions on the maximum allowable minimum physical dimensions of the printed conductors, the distance between catname conductors, the length of the printed conductors, etc. Traditionally adopted design involves wiring topology implemented by the electric circuit on the planes of the layers, which leads to resource limitation on the number of ongoing electrical connections, reducing surface area for placement of model elements replacement and complexity of technology.
The disadvantages of the known devices are limited by the number of ongoing electrical connections and plug standard replacement elements and the complexity of the technology.
The objective of the invention is to increase the resource spatial switching patterns by number sold electrical connections and plug standard replacement elements and simplification of manufacturing technology.
The problem is solved due to the fact that the spatial patch structure containing programmable switching environment, the group's conclusions which are electrically connected with leads for connection of standard elements replacement, according to the invention is made in the form of a polyhedron with n faces that have groups of leads for connection of standard elements substitutions, and programmable switching environment is placed in the center of the polyhedron.
The problem is solved also by t the th, the spatial patch structure containing programmable switching environment, the group's conclusions which are electrically connected with leads for connection of standard elements replacement, according to the invention is made in the form of a polyhedron with n faces, the envelope of which is approaching the area, which has a group of leads for connection of standard elements substitutions, and programmable switching environment is placed in the center of the polyhedron.
Group findings programmable switching environment is electrically connected with the groups of leads for connection of standard elements replacement through conductors embedded in corresponding radially spaced channels.
For example, when implementing the design of the device in the form of a polyhedron, the envelope of which is approaching the area, the achievement of the objective of the invention is composed of the following factors:
- surface area for groups of leads for connection of standard elements replacement will increase by about 4 times (the ratio of the surface area of the ball to the square radial cross-section of the ball);
resource programmable switching environment by number sold electrical connections (if you implement it in accordance with the invention patent of the RF No. 2092896) is given by the number of cells of the matrix commute the Directors and virtually unlimited. Wiring topology implemented by the electric circuit is reduced to the programming matrix. The placement of the conductors is carried out in the space inside the polyhedron and does not change during the implementation of any electrical circuits;
- the use of the polyhedron envelope which is approaching the area, including regular polyhedrons: tetrahedra, cubes, dodecahedrons, icosahedrons, etc. allows you to achieve the same length all the implemented electrical connections.
The proposed device while increasing the surface area for placement of model elements replace approximately 4 times allow the implementation of any electrical circuits when the maximum filling them with the standard replacement elements.
Programmable switching environment, made, for example, patent RF №2092896, figure 2, has a regular structure and can be manufactured according to any technology that allows to obtain matrix switchers.
Thus, in the invention solved the problem of increasing the resource by the number of ongoing electrical connections and plug standard elements replace and simplify technology.
Figure 1 shows a design drawing of the spatial patch structure.
Figure 2 presents a circuit diagram of a programmable switching environment.
Spatial patch structure (figure 1), made for example in the form of a cube 1, the sides of which carries a pin groups 2 to connect standard replacement elements: circuits, connectors, etc. Programmable switching medium 3 is placed in the center of the cube 1. Group outputs 4 programmable switching environment 3 through conductors 5, are placed in respective radially arranged channels 6, are electrically connected with groups conclusions 2 to connect model elements replacement.
The work of the spatial patch structure (figure 1) is as follows.
Typical elements of a replacement set on the faces of the polyhedron, and the group of the findings of each element is connected with its corresponding group of conclusions 2. The location of the model elements replacement on the faces of the polyhedron can be arbitrary. Programming matrix first (1.1...1.F) and second (2.1...2.Q.) groups of the matrix switches programmable switching environment (figure 2) get the topology implemented by the electrical circuit.
If necessary, the Association of devices constructed on the basis of the spatial patch structure (figure 1), in more complex systems, the location of the model elements replacement on the faces of the polyhedron must allow for the connectivity of these devices in Quas the regular or regular patterns.
Spatial patch structure can be made in the form of other polyhedra, including regular polyhedrons, the envelope of which is close to the sphere.
1. Spatial patch structure containing programmable switching environment consisting of the first (1.1...1.F) and second (2.1...2Q) groups, matrix programming, which receive the topology implemented by the electric circuit, when this group of findings programmable switching environment are electrically connected to the fact that it is made in the form of a polyhedron with n faces that have group lessons for installation of model elements substitutions, and programmable switching environment is placed in the center of the polyhedron.
2. Spatial patch structure containing programmable switching environment consisting of the first (1.1...1.F) and second (2.1...2Q) groups, matrix programming, which receive the topology implemented by the electric circuit, when this group of findings programmable switching environment is electrically connected with the groups of leads for connection of standard replacement elements, characterized in that it is made in the form of a polyhedron with n faces, the envelope of which is approaching the area on which the group's conclusions to install a typical El is having replacement with programmable switching environment is placed in the center of the polyhedron.
3. Spatial switching structure according to any one of paragraphs. 1 and 2, characterized in that the pin groups programmable switching environment is electrically connected with the groups of leads for connection of standard elements replacement through conductors embedded in corresponding radially spaced channels.