Device for correcting order of a result of summing of floating point numbers

FIELD: computer science.

SUBSTANCE: device has order correction adder, block for forming scaling signal, resolution inputs for scaling result, limiting and order correction codes of which are, respectively, first, second, and third inputs of device, and output is connected to first information input of order correction adder, second information input of which is fourth input of device, third input of device is connected to third information input of order correction adder, output of which is device output.

EFFECT: higher speed of summing process, registration of scaling constant.

2 cl, 3 dwg

The invention relates to the field of computer technology, in particular to devices adding floating-point numbers, and can be used in the development of arithmetic devices, microprocessors, both universal and specialized.

In the operation of addition of floating point numbers pre-order of the result is equal to the order of a larger absolute value of the operand by the RO. If the result requires normalization, then pre-order result is reduced by an amount called the order of correction, is equal to the number of senior non-significant digits of the mantissa SH. According to the standard ANSI/IEEE 754" on binary arithmetic, the order of the result must be an integer, not a smaller one. Thus, the result should not move to the left by the number of digits exceeds the maximum allowable for the data operand value M, which is equal to M=PB-1, i.e. the order of the larger operand minus 1. The value M is called the code restrictions. If M is less than the number of senior non-significant digits of the mantissa is shifted left by M bits, and the result will be denormalizing number, thereby providing a mode of gradual negative overflow.

According to the standard when receiving denormalizing result in the case of an open mask interrupts "underflow" is mastalirova is selected. It lies in the fact that the mantissa is normalized without regard to code restrictions. If the result is zero or negative, then it is added to the scaling constant 3·2¹³. The order of the result is positive and generates an interrupt "underflow".

A device for correction of the order of the addition of floating point numbers that contain the adder correction order, the first and second inputs which receive respectively the order of a greater number and order of correction (Behrooz Parhami, Computer Arithmetic: Algorithm and Hardware Implementation, str, Oxford University Press, 2000).

The disadvantages of this device include the absence of signal scaling, which makes it impossible to consider the scaling constants, when the order of the result is zero or negative, and is not taken into account the fact that the discharge order correction are formed at different points in time, and this significantly slows down the calculation order of the result.

The closest in technical essence to the invention is a device for correction of the order of the addition of floating-point numbers, which is part of the system that contains the schema definition code left shift, the schema definition of a right shift by one digit, incrementor, the inverter code left shift, and the adder to the correction order (US No. 6301594, CL G 06 F 7/00, 2001).

The disadvantage of this device is the lack of consideration of the scaling constants, when the order of the result is zero or negative, and the long process of summation, due to the fact that the adder is started after the entry of the last digit of the order of correction.

The technical result is to accelerate the summation in the correction of the order of the addition of floating-point numbers, as well as the inclusion of the scaling constants in obtaining denormalizing result in the case of an open mask interrupts "underflow" ("underflow").

This is achieved in that the device for the correction of the order of the addition of floating-point numbers includes a processing unit scaling inputs allow scaling of the code, limitations and correction procedures which are respectively the first, second and third inputs of the device, the output is connected to the first information input of the adder correction order, the second information input of which is the fourth input of the third input connected to the third information input of the adder correction procedure whose output is the output device according to the invention contains an adder correction procedure, which contains three in the La, the first of which performs the following functions:

X₁=PB₆And₆,

P₆=And₆+PB₆,

X₂=X₁+P₆And₅PB₅,

P_5-6=P₆(A₅+PB₅),

X₃=X₁+P_5-6And₄PB₄,

P_4-6=P_5-6(A₄+PB₄),

X₄=X₃+P_4-6And₃PB₃

P_3-6=P_4-6(A₃+PB₃),

X₅=X₄+P_3-6And₂PB₂,

P_2-6=P_3-6(A₂+PB₂),

Y₁=C_in+PB₁,

Y₂=C_inPB₁,

G6=X₅+Y₂P_2-6+P_2-6A₁Y₁,

the second node performs the following function:

G13=G6+(PB₁₃+PB₁₂+...+PB₈+PB₇),

and the third node performs the following functions:

where G6, G13 - signal transfer of six and thirteen least significant bits, respectively, Scale - tone scale, With_insignal input transfer. A₆, A₅, A₄And₃And₂, A₁values of inversions of the signals SH32_l, SH16_l, SH8_l, SH4_l, SH2_l, SH1_lcode , shift considering the limitation of the magnitude of the shift, respectively"32", "16", "8", "4", "2", "1" discharge, respectively, X_i, Y_j- intermediate signals, i, j - a is f number, i ranging from 1 to 5, j ranging from 1 to 2, R_2-6, R_3-6, R_4-6, R_5-6, R₆signals propagate transfer, respectively, by discharges from the 2 nd to 6-nd, 3-th and 6-th, 4-th and 6-th, 5-th and 6-th and 6-th discharge, PB₁₅, PB₁₄,...,PB₂, PB₁signals about the larger addend, respectively, 15-th, 14-th,..., 1-th digits, in addition, the processing unit scaling performs the following logical function:

Scale=ScaleEN*

where Scale - signal scaling, SH64_l, SH32_l, SH16_l, SH8_l, SH4_l, SH2_l, SH1_lthe code signals of the shift taking into account the limitations of the shift values, respectively"32", "16", "8", "4", "2", "1" discharge, respectively, M₇, M₆,..., M₁signals code restrictions, respectively, 7-th, 6-th,..., 1-th digits, ScaleEN - permission signal scaling result.

The essence of the invention lies in the fact that the implementation of the inventive device as described above using adder correction procedure and the processing unit scaling, allows to provide high performance with a significant simplification of the device.

A comparison of the proposed device with the closest analogue suggests the criterion of "novelty", and the lack of

in analogically characteristics of the claimed device says about the criterion of "inventive step".

Preliminary tests allow to judge about the possibility of widespread industrial use.

Figure 1 shows the block diagram of the device for the correction of the order of the addition of floating-point numbers, figure 2 presents the principle of structural breaks adder correction order on separate nodes, figure 3 presents an example implementation of the first node of the adder correction order by the appropriate logical formulas.

The device comprises a block 1 signal scaling adder 2 correction order, the first, second, third and fourth inputs 3-1-3-4 and output 3-5. Output 4 unit 1 signal scaling is connected to the first information input of adder 5-1 2 correction order, the second input 5-2 which is the fourth entry 3-4 device, and a third input 5-3 connected to the third input 3-3 device. Inputs 3-1-3-3 are input unit 1, signal scaling, and the output of 3-5 device is the output of the adder 2 correction order.

Unit 1 signal scaling performs the following logical function:

Scale=Scale EN*

where Scale - signal scaling, SH64_l, SH32_l, SH16_l, SH8_l, SH4_l, SH2_l, SH1_lthe code signals of the shift considering the limitation of the magnitude of the shift line is the result for "32", "16", "8", "4", "2", "1" discharge, respectively, M₇, M₆,..., M₁signals code restrictions, respectively, 7-th, 6-th,..., 1-th digits, ScaleEN - permission signal scaling result.

The adder 2 correction procedure contains three nodes, the first of which performs the following functions:

X₁=PB₆And₆,

P₆=And₆+PB₆,

X₂=X₁+P₆And₅PB₅,

P_5-6=P₆(A₅+PB₅),

X₃=X₁+P_5-6And₄PB₄,

P_4-6=P_5-6(A₄+PB₄),

X₄=X₃+P_4-6And₃PB_3,

P_3-6=P_4-6(A₃+PB₃),

X₅=X₄+P_3-6And₂PB₂,

P_2-6=P_3-6(A₂+PB₂),

Y₁=C_in+PB₁,

Y₂=C_inPB₁,

G6=X₅+Y₂P_2-6+P_2-6A₁Y₁,

the second node performs the following function:

G13=G6+(PB₁₃+PB₁₂+...+PB₈+PB₇),

and the third node performs the following functions:

where G6, G13 - signal transfer of six and thirteen least significant bits, respectively, Scale - tone scale, With_insignal input transfer, And₆And₅And₄, A₃And₂, A₁- value the inversions of the signals SH32 _l, SH16_l, SH8_l, SH4_l, SH2_l, SH1_lcode , shift considering the limitation of the magnitude of the shift, respectively"32", "16", "8", "4", "2", "1" discharge, respectively, X_i, Y_j- intermediate signals, i, j are integers, i ranging from 1 to 5, j ranging from 1 to 2, R_2-6, R_3-6P_4-6, R_5-6, R₆signals propagate transfer, respectively, by discharges from the 2 nd to 6-nd, 3-th and 6-th, 4-th and 6-th, 5-th and 6-th and 6-th discharge, PB₁₅, PB₁₄,..., PB₂, PB₁signals about the larger addend, respectively, 15-th, 14-th,..., 1-th digits.

An example implementation of the first node of the adder correction order by the appropriate logical formulas presented in figure 3, where the logical block 6 is an element of type OR, and logical blocks 7-11 are elements of type 2-1-AND-OR.

The device operates as follows :

Consider the Block 1 signal scaling Scale:

Scale=ScaleEN*

He strobiles signal resolution scaling of the ScaleEN. Next, Scale equal to "1"if SH64_l="1", a M₇="0" (the first term in brackets). If SH64_l=M₇then move on to comparing the factors of the second term. If SH32_l="1", and the M₆="0"Scale produced. If SH64_l=M₇and SH32_l=M_{6 then go ahead and analyzed discharges SH16land M5.}

This process ends with a comparison of discharges SH1_land M_l.

Thus, the signals SH_land M bit are compared, beginning with the oldest discharge; if the discharge SH_lmore appropriate level M, then the signal scaling, otherwise proceed to the comparison of younger grades. Using several times the Boolean identityyou can convert the expression for the Scale to the following:

Scale=ScaleEN*

The expression for the signal Scale can be expanded relatively SH1_l.

Scale=A₁+B₁*SH1_l,

where A₁and In₁are functions that depend on SH2_l, SH4_l, SH8_l, SH16_land SH32_l.

The dependence on M is immaterial from the point of view of the delay, since M is formed in advance. A₁and B₁you can prepare for the same time as SH1_l. Thus, this expression can be obtained for one logical level on the element 1I-2I-ILY.

Similarly, you can put A₁and B₁relatively SH2_l.

A₁=A_2a+B_2a*SH2_l,

In₁=And_2b+_2b*SH2₁,

Here a_2aIn_2aAnd_2band In_2bare functions that depend on SH4_l, SH8 l, SH16_land SH32_l.

These expressions can be implemented in one logic level after receiving SH2_lAnd_2aIn_2a, A_2band In_2b. Thus, the sequential decomposition of the signal on the decimal Scale SH_lgives a chance to implement it through one logical level after the appearance of SH1_l.

Figure 2 shows the partitioning of the adder 2 correction procedure on three corresponding node: the node with the digits "1" through "6", the node with the digits "7" "13" and the node with two older bits.

"15"-bit order more (double extended format) supplied to the adder in the direct phase, "6"-bit shift code is inverted, while the "9" senior ranks of the second term are filled units. In addition, two senior level adder start signal scaling Scale.

Addition occurs in the reverse code, as well as the amount according to the standard must be positive (E_min="1"), then there will always be circular migration, therefore, in the adder have to start With_in=1.

On the other hand, when the number of senior non-significant digits of the mantissa is equal to "64"bits of code shift with SH32_lon SH1_lequal to "1", that is, in the adder from about greater subtracted code 111111, and it is necessary to take the code 1000000. If in this case to do With_in="0"then it will be equivalent to an additional subtract"1" from order more. Thus, we believe

The transfer of "6" low G6 can be expanded in series inversions bits of code shift SH1_l, SH2_l,..., SH32_land get it through one logical level after joining SH1₁. An example implementation figure 3.

Transfers in Junior "6" digits of the adder can be calculated not slower than the G6, that is, "1"-"6" discharge order results can be obtained through two logic level after SH1_l.

The sum in the middle group is determined by the signal G6:

- if the transfer is, the amount equal to PB₁₃, PB₁₂,..., PB₈, PB₇,

- if transfer no amount equal {PB₁₃, PB₁₂,..., PB₈, PB₇}+{11...11) (it can be computed in advance).

Thus, the sum of the digits "7" "13" can also be calculated through the "2" logic level after joining SH1_l.

The transfer of 13 digits G13 is used to calculate the two high-order bits of the sum. Obviously,

G13=G6+(PB₁₃+PB₁₂+...+PB₈+PB₇).

The expression can be calculated for the same time as the G6, as it

differs only summands in brackets, which do not depend on SH_l.

For "14"-th and "15"on the digits of the sum can be written:

that can be implemented in one logiteck the level after receiving G13.

Thus, all the bits about the result, it is possible to form through "2" logic level after receiving minor category code shift SH1_l.

Thus, the proposed device allows you to speed up the process of summation in the correction of the order of the addition of floating-point numbers, and to consider the scaling constant when receiving denormalizing result in the case of an open mask interrupts "underflow" ("underflow").

1. A device for correction of the order of the addition of floating-point numbers, characterized in that it comprises a processing unit scaling inputs allow scaling of the code, limitations and correction procedures which are respectively the first, second and third inputs of the device, the output is connected to the first information input of the adder correction order, the second information input of which is the fourth input of the third input connected to the third information input of the adder correction procedure whose output is the output device, and the adder correction procedure contains three nodes, the first of which performs the following functions:

X₁=PB₆And₆,

P₆=And₆+PB₆,

X₂=X₁+P₆And₅PB_{5 ,}

_{P5-6=P6(A5+PB5),}

X₃=X₁+P_5-6And₄PB₄,

P_4-6=P_5-6(A₄+PB₄),

X₄=X₃+P_4-6And₃PB₃

P_3-6=P_4-6(A₃+PB₃),

X₅=X₄+P_3-6And₂PB₂,

P_2-6=P_3-6(A₂+PB₂),

Y₁=C_in+PB₁,

Y₂=C_inPB₁,

G6=X₅+Y₂P_2-6+P_2-6A₁Y₁,

the second node performs the following function:

G13=G6+(PB₁₃+PB₁₂+...+PB₈+PB₇),

and the third node performs the following functions:

where G6, G13 - signal transfer of six and thirteen least significant bits, respectively,

Scale - signal scaling

C_insignal input transfer

And₆And₅And₄And₃, A₂, A₁values of inversions of the signals SH32_l, SH16_l, SH8_l, SH4_l, SH2_l, SH1_lcode , shift considering the limitation of the magnitude of the shift, respectively"32", "16", "8", "4", "2", "1" discharge, respectively,

Xi, Yj - intermediate signals, i, j are integers, i ranging from 1 to 5, j ranging from 1 to ,

P_2-6, R_3-6, R_4-6, R_3-6, R₆signals propagate transfer, respectively, by discharges from the 2 nd to 6-nd, 3-th and 6-th, 4-th and 6-th, 5-th and 6-th and 6-th digit,

PB₁₅PB₁₄,...PB₂, PB₁signals about the larger addend, respectively, 15-th, 14-th,..., 1-th digits.

2. The device according to claim 1 characterized in that the processing unit scaling performs the following logical function:

Scale=ScaleEN*

where Scale - signal scaling

SH64_l, SH32_l, SH16_l, SH8_l, SH4_l, SH2_lSH1_lthe code signals of the shift taking into account the limitations of the shift values, respectively"32", "16", "8", "4", "2", "1" discharge, respectively,

M₇, M₆,...M₁signals code restrictions respectively the 7th, 6th,...1-th digits,

ScaleEN signal resolution mashtabirovanie result.