Logical calculator
 Quantum-effect integrated not gate / 2272353Proposed device has half-insulating GaAs substrate, input metal bus disposed under the latter to form Schottky junction, first AlGaAs region of second polarity of conductivity, first self-conductance AlGaAs region of spacer disposed under the latter, self-conductance GaAs region of first channel disposed under the latter, second AlGaAs region of second polarity of conductivity, second self-conductance AlGaAs region of spacer, output region of second polarity of conductivity, input, power, and zero-potential metal buses, isolating dielectric regions, self-conductance AlGaAs region of tunnel barrier, self-conductance InGaAs region of second channel, self-conductance AlGaAs region of second barrier, L-section power region of second polarity of conductivity, and Γ-section zero-potential region of second polarity of conductivity; self-conductance GsAs region of first channel and self-conductance InGaAs region of second channel are vertically disposed relative to one another. |
 Method, device and command for performing sign multiplication operation / 2275677Device has memory cell and executing resources, meant for execution of command on first operand and storing the result, having value of first operands for all values of appropriate second operand greater than zero, and zero, if value of appropriate second operand is zero, negative version of first operand for all values of appropriate second operand lesser then zero. |
 Combination type adder / 2275676Device has two RS-triggers, seven AND elements, seven OR elements, four NOT elements, seven control buses, transfer bus. |
 Method for integrating control signal for astatic systems for controlling aircrafts and device for realization of said method / 2275675Method for integrating control signal for astatic systems for controlling aircrafts includes setting control signal for integration, integrating current integration signal and integrated signal is scaled, scaled signal is amplified, amplified signal is inverted, threshold signal ε≥0 is set, setting control signal is multiplied with scaled signal, multiplication signal is compared to threshold signal, check connection signal is formed, equal to inverse signal during excess of multiplication signal over threshold signal, current integration signal is formed, equal to total of setting signal and check connection signal, and scaled integrated signal is limited. Device for realization of method contains integration signal set-point device, adder, integrating link, scaling amplifier, signal limiter, inverting amplifier, controlled key, multiplication block, relay element, threshold signal set-point device. |
 Information sorting device / 2274893Device has stack memory blocks, comparison element, control block, input and output channels, random-access memory block, block for commutation and identification, external controlling inputs, external controlling outputs, controlling outputs of control block. |
 Frequency splitter with alternating splitting coefficient / 2273043Device has two n-bit binary counters, n AND elements, OR element. |
 Neuron network for rounding and scaling numbers, represented in system of remainder classes / 2271570Network has input layer of neurons, neuron network of end ring for determining number rank, neuron network of end ring for calculating remainder at base n+1, n-neuron networks of end ring for calculating scaled number, neuron network for calculating difference in numbers between input remainders and base remainder. |
 Generator for modeling flow of requests in mass service systems / 2271564Generator has set-point generator 1, generator 2 of exponential voltage, generator 3 of evenly distributed random numbers, digital-analog converter 4, elements OR 5,6, block 7 for comparison, device for pulse generation 8, forbidding element 9, trigger 10, multiplication block 11, input 12 and output 13 of device. Requests stream is formed of elementary stream by excluding one request with preservation of second request, i.e. at output 13 of generator through temporal ranges, distributed in accordance to Erlang law of second order, pulses are generated, modeling receipt of requests. |
 Device for adding n numbers by module p / 2270476Device has encoder, controlled phase shifter, harmonic signal generator, phase shifters for fixed phase value, device for measuring the phase of harmonic signal, multiplexer, commutator, amplitude detector and harmonic signal amplifier. |
 Device for calculating sums of paired results of multiplications in polynomial system of residual classes / 2270475Device uses neural-network technologies and polynomial residuals system, wherein as system base minimal polynomials pi(z), where input=1,2,...,n, are utilized, determined in expanded Galois fields GF(2V), while device has clock counter, two blocks for calculating sums of paired results of multiplication by arbitrary base, error correction block, modular adder and block for calculating sums of paired results of multiplication based on control base. |
 Spatial commutation structure / 2270474Spatial commutation structure has programmable commutation environment, groups of outputs of which are electrically connected to groups of outputs for connecting typical replacement elements. It is made in form of a polyhedron with n sides, on which groups of outputs are mounted for connecting typical replacement elements, while programmable commutation environment is positioned in the center of polyhedron. Second variant is different because spatial commutation structure is made in form of polyhedron with n sides, circling line of which approaches a spheroid shape. Groups of outputs of programmable commutation environment in accordance to both variants are electrically connected to groups of outputs for connecting typical replacement elements by means of conductors, positioned in appropriate radially positioned channels. |
 Multilevel m-dimensional matrix adding structure for vertical arithmetic / 2246128Into multilevel m-dimensional matrix adding structure, containing one-digit adding nodes of first, second and third levels, m-dimensional matrix structures for one-digit adding of second, third and fourth level are inserted, which form hierarchical multilevel adding structure of vertical arithmetic, representing a regular hierarchical logarithmical structure connected along vertical line, with inter-level links, along horizontal line - matrix structure, wherein matrix structures of previous levels, connected by links, form a matrix structure of next hierarchical level of multilevel m-dimensional matrix structure. |
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Random numbers generation method / 2246129 Method includes generating random numbers with use of displacement register with check connection, elementary digit of which is a q-based symbol (q=2l, l - binary symbol length) at length of q-based digits register, in check connection networks nonlinear two-parameter operations on q-based symbols F (ub, ud) are used, on basis of random replacement tables, for generating next random number values z1=F(ui, uj), z2=F(ut, um), zg=F(z1, z2) are calculated, where ui, uj, ut, um - values of filling of respective register digits, value of result in check connection networks zg is recorded to g digit of displacement register and is a next result of random numbers generation, after which displacement of register contents for one q-based digit is performed. |
 Device for sorting numbers / 2246750Device has n analysis blocks, each of which contains two And elements, two groups of AND elements, OR element, comparison circuit and register, commutation trigger, control trigger, delay element, AND-NOT element, AND elements, pulse generator. |
 High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states. |
 Parallel subtractor-adder on neurons / 2246752Device has numbers input block, comparison block, greater number register, adding-subtracting block, least number register block, result register block, control block. |
 Device for scaling number in modular scale of notation / 2246753Device has N blocks for calculating remainders, each of which has N devices for calculating remainders from bases of modular notation scale, including multiplication blocks, module adders of 3N numbers and tabular calculators. |
 Logical converter / 2248034Device has eleven majority elements, four information inputs, two adjustment inputs. |
 Symmetric module / 2248035Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered |
 Logical calculator / 2248036Device has 2n AND elements, n OR elements, n D-triggers. |
 Pulse code transformer / 2248607Device has information input device, clock generator, connected to address counter with decoder, outputs of which are connected to inputs of recording device, inputs of which are connected to output of programming device, signal generator and multiplexers. Device for recording object sate is connected to output of decoder of cells address of device. Signal generator includes cells for recording checksum. First input of signals generator is connected to output of decoder of address of cells of checksum, second input - to output of recording device, first output - to first inputs of multiplexers, and second output - to first input of binary adder, by its output connected to third input of signal generator and checksum. Outputs of decoder of checksum cells address and decoder of object state recording device cells addresses are connected to second output of address counter, which is connected to second inputs of multiplexers. Recording device is programmable. |
FIELD: computer science, possible use for building automatic devices, functional assemblies of control systems and the like.
SUBSTANCE: logical calculating device for realization of n simple Boolean functions depending on n arguments - input binary signals contains (n-1) elements AND, (n-1) OR elements and (n-1) D-triggers.
EFFECT: simplified construction due to decreased number of information inputs in n times while maintaining functional capabilities of prototype.
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The invention relates to computer technology and can be used for building automation, functional units of the control systems and other
Known logic solvers (see, for example, is on str in the book Gutnikov B.C. Integrated electronics in the measuring devices. HP: Energoatomizdat, 1988), which implement a simple symmetric Boolean function τ2=x1x2∨x1x3∨x2x3that depends on three arguments - input binary signals x1, x2, x3∈{0,1}.
For the reason that impede the achievement of specified following technical result when using known logic solvers are limited functionality due to the fact that there is no implementation of n simple symmetric Boolean functions that depend on n arguments - input binary signals x1, ...,xn∈{0,1}.
The closest device to the same destination to the claimed invention by the combination of features is adopted for the prototype logic solver (see figure 2 in the article Savchenko YG, Hop A.V. methods consistent implementation of symmetric Boolean functions // Automatic control and computer engineering. 1974. No. 3. P.24-29), which contains n-1 elements And n-1 elements OR implements n simple SIM is etnichnyh Boolean functions, depend on n arguments - input binary signals x1, ...,xn∈{0,1}.
For the reason that impede the achievement of specified following technical result when using the prototype, is a complex structure, because the prototype has n information inputs.
The technical result of the invention is to simplify the structure by reducing the number of information inputs n times while maintaining the functionality of the prototype.
This technical result in the implementation of the invention is achieved in that in a logical computer containing n-1 elements And n-1 elements OR peculiarity lies in the fact that it introduced n-1 D-flip-flops, and a non-inverting output of the i-thD-flip-flop connected to a second input of the i-th element And the first input of the i-th element OR connected to the second input and output respectively to the first input of the i-th element And the input data of the i-th D-flip-flop, a reset input and a clock input of which is connected respectively with the first and second control inputs of the logic solver, connected to the information input and the i-th output, respectively, to the first input of the first element And the output of the i-th element OR the output of each previous element And connected to the first input of the subsequent element, And the output (n-1)-th El kelaa the enta And is the nth output of the logic solver.
Figure 1 and figure 2 presents respectively the proposed scheme logic solver and timing diagrams explaining the principle of its operation.
Logic solver contains the elements 1 And1, ...,1n-1elements OR 21, ...,2n-1D-triggers 31, ...,3n-1and non-inverting output of D-flip-flop 3iconnected with the second input element 1iand the first input element 2iconnected to the second input and output respectively to the first input element 1iand the data input of D-flip-flop 3i, reset input and a clock input of which is connected respectively with the first and second control inputs of the logic solver, connected to the information input and the i-th output, respectively, to the first input element 11and the output element 2ithe output of element 1k
connected to the first input element 1k+1and the output of the element 1n-1is the nth output of the logic solver.
The work of the proposed logic solver is as follows. At its first, second control inputs are given correspondingly of pulse signals y1, y2∈{0,1} (2)with the period T of the signal y2must satisfy the condition T>Δt, where Δt=ΔtTr+(n-1)ΔtAndthat is Δ tTrand ΔtAndthere is duration of the delay introduced D-trigger and element Acting Synchronously with the front edge of the pulse signal y1and front fronts first, ..., (n-1)-th pulse signal y2on the information input logic solver consistently served binary signals x1and x2, ..., xnrespectively (figure 2). Then the signals at the outputs of the elements 1i, 2iwill be determined by recurrent expressions
wherethere are a number of time ti(figure 2); Vi0=0; W0j=xj. The following table shows the values of the expressions (1) when n=4.
| V11=x1 | V12=x1∨x2 | V13=x1∨x2∨x3 | V14=x1∨x2∨x3∨x4 |
| W11=0 | W12=x1x2 | W13=x1x3∨x2x3 | W14=x1x4∨x2x4∨x3x4 |
| V21=0 | V22=x1x2 | V23=x1x2∨x1x3∨x2 x3 | V24=x1x2∨x1x3∨x1x4∨ |
| W21=0 | W22=0 | W23=x1x2x3 | ∨x2x3∨x2x4∨x3x4 |
| W24=x1x2x4∨x1x3x4∨x2x3x4 | |||
| V31=0 | V32=0 | V33=x1x2x3 | V34=x1x2x3∨x1x2x4∨x1x3x4∨x1x3x4 |
| W31=0 | W32=0 | W33=0 | W34=x1x2x3x4 |
Thus, at the first, second, ..., nth outputs of the proposed logic solver when j=n, respectively, have
where τ1, ..., τnthere is a simple symmetric Boolean functions (see str in the book Pospelov D.A. Logical methods of analysis and synthesis schemes. M: Energy, 1974).
The above data allow us to conclude that the proposed logic solver implements n simple symmetric Boolean functions that depend on n is of argumentof - input binary signals, and has a more simple compared to the prototype structure, as it has only one data input.
Logic solver to implement n simple symmetric Boolean functions that depend on n arguments - input binary signals containing n-1 elements And n-1 elements OR, characterized in that it introduced n-1 D-flip-flops, and a non-inverting output of the i-thD-flip-flop connected to a second input of the i-th element And the first input of the i-th element OR connected to the second input and output respectively to the first input of the i-th element And the input data of the i-th D-troster, a reset input and a clock input of which is connected respectively with the first and second control inputs of the logic solver, connected to the information input and the ith output respectively to the first input of the first element And the output of the i-th element OR the output of each previous element And connected to the first input of the subsequent element, And the output (n-1)-th element is the n-th output of the logic solver, on the first, second control inputs of which are given correspondingly of pulse signals y1, y2∈{0,1}, and the period T of the signal y2satisfies the condition T>Δt, where Δt=ΔtTp+(n-1)ΔtAnda ΔtTrand ΔtAnd- d is italinate delays, make D-trigger element And the first and second, ..., nth input binary signals sequentially served on the information input logic solver synchronously with the front edge of the pulse signal y1and front fronts first, ..., (n-1)-th pulse signal y2respectively.