Apparatus for boundary composite coding in interval computations. RU patent 2497180.
 Apparatus for decoding jointly stored boundaries in interval computations / 2497179Apparatus includes an encoder, a decoder unit, ROM, shifters, subtractors, multiplexers, an adder, modulo two adders, an inverter, AND and OR elements. |
 Method by kuvyrkov for information processing and calculation (versions) and device "generaliser" for method realisation / 2494445In one of versions the method includes parallel-serial processing of a signal in a block of triggers of an input register; in a matrix device; in a unit of logical elements, preferably logical elements "AND"; in a unit of triggers of an output register. At the same time the signal processing in the matrix device is performed in accordance with the geometric model of the signal processing, representing a combination of graphs that forms at least one right triangle, which is divided into three parts, with lines stretching from the tops of the triangle angles. |
 Logic processor / 2491613Disclosed is a logic processor designed to execute eight simple symmetrical Boolean functions which depend on eight arguments - input binary signals, which can be used in digital computer systems as a code converting means, and also having nineteen computational cells (11,…,119), each having an OR element (2) and an AND element (3). |
 System and method for adaptive prioritisation of antivirus scanning objects / 2491611System for adaptive prioritisation of antivirus scanning objects includes a rule setting device which sets rules for prioritising antivirus scanning objects, a rule database for storing prioritisation rules and providing rule data to a queuing device. The system also includes an analyser which determines parameters of antivirus scanning objects required for prioritisation and sends said parameters to the queuing device. The queuing device is designed to assign priority and a scanning method with defined parameters in accordance with set rules. The queuing device also constructs a queue in accordance with the assigned priorities and sends the queue to a malicious object detecting device. The malicious object detecting device performs antivirus scanning of the scanning queue in accordance with the scanning method assigned for each object and sends the scanning results to a scanning result analyser. |
 Methods and systems for implementing approximate string matching within database / 2487394Method for character string matching of a candidate character string with a plurality of character string records stored within a database involves identifying a set of reference character strings in the database. The reference character strings are identified using an optimised search for a set of dissimilar character strings. An n-gram representation of each of the reference character strings in the set of reference character strings is generated and an n-gram representation of the candidate character string is also generated. Further, similarity between n-gram representations of each of the reference character strings and the candidate character string is determined. The candidate character string in the database is indexed based on the determined similarities between the n-gram representation of the candidate character string and the reference character strings in the identified set. |
 Self-checking special-purpose computer of boolean function systems / 2485575Device has memory units, adders, multiplexers, a remainder modulo calculating unit, a memory register, logic elements AND and NOR. |
![Method to generate arguments of analog signals of partial products [n<sub>i</sub>]&[m<sub>j</sub>]f(h)<sub>↓cd</sub> arguments of multiplicand <sup>±</sup>[m<sub>j</sub>]f(2<sup>n</sup>) and arguments of multiplier <sup>±</sup>[n<sub>i</sub>]f(2<sup>n</sup>) -](http://img.russianpatents.com/img_data/996/9969637-s.gif)
Σ(↓cdΣ) for subsequent logical decoding f1(cd↓) and generation of resulting sum in format ±[sΣ]f(2n) -"additional code" and functional structure for its realisation (versions of russian logics)" align=left vspace="30" hspace="30" />
Σ(Σcd), implementing procedure for "decryption" of input structures of arguments of terms [1,2sj h1]f(2n) and [1,2sj h2]f(2n) of "complementary code ru" positional format by applying arithmetic axiom of ternary number system f(+1,0,-1) and logic differentiation d1/dn → f1(+←↓-)d/dn of arguments in combined structure thereof (versions of russian logic)" align=left vspace="30" hspace="30" />
Σ(Σcd), implementing procedure for "decryption" of arguments of terms [1,2sg h1] and [1,2sg h2] "complementary code ru" by arithmetic axiom of ternary number system f(+1,0,-1) and logic differentiation d1/dn → f1(+←↓-)d/dn (versions of russian logic)" align=left vspace="30" hspace="30" />
 Cell of homogeneous computing environment, homogeneous computing environment and apparatus for pipeline computation of sum of m n-bit numbers / 2475815Cell of a homogeneous computing environment has an XOR element, an AND element and two flip-flops. |
 Pulse code transformer / 2248607Device has information input device, clock generator, connected to address counter with decoder, outputs of which are connected to inputs of recording device, inputs of which are connected to output of programming device, signal generator and multiplexers. Device for recording object sate is connected to output of decoder of cells address of device. Signal generator includes cells for recording checksum. First input of signals generator is connected to output of decoder of address of cells of checksum, second input - to output of recording device, first output - to first inputs of multiplexers, and second output - to first input of binary adder, by its output connected to third input of signal generator and checksum. Outputs of decoder of checksum cells address and decoder of object state recording device cells addresses are connected to second output of address counter, which is connected to second inputs of multiplexers. Recording device is programmable. |
 Homogenous substance cell / 2251140In a cell, containing seven inputs, eight OR elements, ten AND elements, three outputs by its adjustment different combination variants of connections of inputs to cell outputs are provided, to provide for calculation of Boolean formulae systems from classes of non-repeated orderly and disorderly formulae. |
 Homogenous substance cell / 2251141Cell has eight outputs, forty-five AND elements, three OR elements, three inputs. |
 Method for automatic detection of current state during multi- parameter comparison / 2255368Method includes forming parameters aij for each object, where i - object number, , and j - parameter number , normalization of values of objects parameters relatively to maximal value for each object and calculation of value of vector Vi in space of n parameters according to formula , where with following recording and comparison of vectors values. Normalization relatively to value of maximal parameter allows to exclude wrong estimation of object state. |
 Logical module / 2262733Device has two majority elements, while output of first majority element is connected to second input of second majority element, connected by first, third inputs and an output respectively to second superstructure, third information inputs and output of logical module, first, second information and first superstructure inputs of which are formed by respectively second, third and first inputs of first majority element. |
 Logical calculator / 2262734Device has n logical modules, each of which has two AND elements, OR element and two D-triggers. |
 Device for correcting order of a result of summing of floating point numbers / 2267806Device has order correction adder, block for forming scaling signal, resolution inputs for scaling result, limiting and order correction codes of which are, respectively, first, second, and third inputs of device, and output is connected to first information input of order correction adder, second information input of which is fourth input of device, third input of device is connected to third information input of order correction adder, output of which is device output. |
 Spatial commutation structure / 2270474Spatial commutation structure has programmable commutation environment, groups of outputs of which are electrically connected to groups of outputs for connecting typical replacement elements. It is made in form of a polyhedron with n sides, on which groups of outputs are mounted for connecting typical replacement elements, while programmable commutation environment is positioned in the center of polyhedron. Second variant is different because spatial commutation structure is made in form of polyhedron with n sides, circling line of which approaches a spheroid shape. Groups of outputs of programmable commutation environment in accordance to both variants are electrically connected to groups of outputs for connecting typical replacement elements by means of conductors, positioned in appropriate radially positioned channels. |
 Combination type adder / 2275676Device has two RS-triggers, seven AND elements, seven OR elements, four NOT elements, seven control buses, transfer bus. |
 Logical calculator / 2276399Logical calculating device for realization of n simple Boolean functions depending on n arguments - input binary signals contains (n-1) elements AND, (n-1) OR elements and (n-1) D-triggers. |
FIELD: information technology.
SUBSTANCE: apparatus includes flip-flops, registers, ROM, subtractors, adders, multiplexers, shifters, a comparator unit, modulo two adders, AND and OR elements and a priority encoder.
EFFECT: high accuracy of stored results of interval computations in floating point format, while maintaining overall code length of the upper and lower boundaries of an arithmetic interval.
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The invention relates to the technique of organization of interval computations in the floating point format and is aimed at improving the accuracy of estimating the interval boundaries at a given bit of code that is stored in the computer memory. It is assumed that the intermediate calculations can be made with a higher bit depth than the bitness of the numbers stored in the computer memory. The proposed device uses 64 bits to joint coding of the two boundaries of the interval arithmetic.
Known method and apparatus for submission of arithmetic intervals in a computing system (US 6658443 B1, 02.12.2003).
The system performs arithmetic operations on the rules of interval arithmetic, receiving the result of the calculation in the form of interval. The resulting interval is represented the first number in the floating point format, which is the first boundary of the interval and the second number in the floating point format, which is the second boundary of the interval. Both numbers representing the limit of the interval, whatever is written in the memory of a computer.
The essence of technical solutions is manifested in situations when the intervals become very large, i.e. when the significance of the result is largely lost.
A drawback of the system is the low accuracy of the method is provoking a situation of having large intervals, representing the results of calculations.
Known computer system of interval computing, is closest to its technical nature of the present invention, and selected as a prototype (EN 2006929 C1, 30.01.1994).
This computer system contains the first and second modules of memory to store numbers that are the upper and lower boundaries of the intervals, two arithmetic device to calculate the upper and lower bounds group multiplexers that are broadcasting chosen from memory in arithmetic units and transfer of recordable of arithmetic units in code memory intervals.
In the course of computation of two memory modules simultaneously is extracted upper and lower limits of the first interval, then simultaneously retrieved upper and lower limits of the second interval. Read from the memory numbers of appropriately transferred to operational units carrying out calculations according to the rules of interval arithmetic. The resulting calculation interval is stored in the memory as two numbers represented in floating point format.
Lack of device is selected as a prototype - a little bit width top and bottom edge, stored in memory, which leads to a rapid increase in the intervals in calculations, which, in turn, leads to excessively pessimistic estimates of the accuracy of calculation results.
The technical result of the invention is increasing the accuracy of the results of interval computations in the floating point format when saving the total bitness persistent in-memory code of the upper and lower boundaries of the interval, provided that the intermediate calculations are performed over numbers with increased bitness. The technical result is achieved due to the joint encoding stored in memory values of upper and lower boundaries of the interval computations, and to specify the mantissa numbers not subjected to rounding used 42 discharge (in the prototype only 23 discharge). The proposed device in a joint encoding close numbers allows you to save the information to a greater number of bits of the mantissa. The increased accuracy of the boundaries of the interval is ensured until one of the borders will not exceed the absolute value of another border in 32 times. Thus, whenever the results of calculations can be considered to be credible, the proposed device helps to provide greater accuracy of estimation of results of calculations.