Frequency agile digital computational synthesiser

FIELD: radio engineering, communication.

SUBSTANCE: digital computational synthesiser has a reference generator 1 and a formation and delay unit 2, a first memory register 3, a first counter 4, a code multiplier 5, a digital storage 6, a code converter 7, a digital-to-analogue converter (DAC) 8, a low-pass filter 9, the output of which is the analogue output of the digital computational synthesiser; a second memory register 10, a second counter 11, a third memory register 12, a variable-ratio divider 13; inputs of the first, second and third memory registers are the digital inputs of the digital computational synthesiser.

EFFECT: high rate of adjusting operational frequency.

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The invention relates to electronic computing and engineering is intended for the synthesis of frequency-modulated signals and can be used in radar, navigation and modern adaptive communication systems.

Known digital frequency synthesizers containing two blocks of permanent digital memory storage device, the multiplier codes, preset counters, the code Converter, a memory register, a d / a Converter, low pass filter, clock generator pulses, the delay unit [1].

The closest technical solution (prototype) is a digital frequency synthesizer, comprising a generator of clock pulses, the delay block, the block of continuous memory, preset counters, multiplier codes, digital memory, digital to analog Converter, low pass filter, the memory register [2].

However, the known digital frequency synthesizers do not have a high speed frequency hopping and have limited functionality when forming signals with linear frequency modulation.

The technical result is to increase the speed of adjustment of the frequency is achieved by the digital computer synthesizer containing serially connected reference generator and the shaping unit and the time delay is; a second memory register, the input of which is digital input digital synthesizer; sequentially connected to the first counter, a multiplier codes, digital drive, the code Converter, digital to analog Converter and a low pass filter whose output is an analog output digital synthesizer; the outputs of the shaping unit and the delay is connected to the clock inputs mnimogo, the multiplier and the product of multiplier codes, as well as to the clock inputs of the digital memory and digital to analogue Converter, and the new is that the first and third memory register, a second counter, a divider with a variable division ratio, while digital inputs digital synthesizer are the inputs of the first and third memory registers; the output of the first memory register connected to the input of the first counter; the output of the second memory register connected to the input of a second counter and a second counter connected to the input of multiplier multiplier codes; the output of the third memory register connected to the input of the divider with a variable division ratio, the yield of the latter is connected to the clock input of the second counter; the outputs of the shaping unit and the delay is connected to the respective clock inputs of the first counter, divider with variable ratios is ntom division.

Digital synthesizer includes a reference oscillator 1 and the shaping unit and delay 2, the first memory register 3, the first counter 4, the multiplier codes 5, the digital memory 6, the code Converter 7, a digital-to-analogue Converter (DAC) 8, a lowpass filter (LPF) 9 whose output is an analog output digital synthesizer, the second register memory 10, the second counter 11, the third memory register 12, a divider with a variable division ratio of 13; the inputs of the first, second and third memory registers are digital inputs digital computer synthesizer.

Digital synthesizer contains serially connected reference generator 1 and the power generation and delay 2; sequentially connected first memory register 3, the first counter 4, the multiplier codes 5, the digital memory 6, the code Converter 7, a d / a Converter 8 and the low pass filter 9 whose output is an analog output digital synthesizer; serially connected second memory register 10 and the second counter 11, the output of which is connected to the input of multiplier multiplier codes 5; connected in series, the third memory register 12 and the divider with a variable division ratio of 13, the output of the latter is connected to the clock input of the first sketchy the and 11; the outputs of the shaping unit and delay 2 are connected to the respective clock inputs mnimogo, the multiplier and the product of multiplier codes 5, the digital memory 6, a d / a Converter 8, the first counter 4, a divider with a variable division ratio of 13; digital inputs digital synthesizer are the inputs of the first, second and third memory registers 3, 10, and 12.

Digital synthesizer operates as follows: the Reference generator 1 generates a sinusoidal signal of clock frequency, from which the shaping unit and delay 2 are formed heartbeats form "meander", spaced in time and are used to synchronize the operation of the digital computer keyboard.

The inputs of the first memory register 3 receives code X_i(code mnimogo), at the input of the second memory register 10 receives the code Y_j(code multiplier), to the input of the third memory register 12 receives code D_k.

These codes are written respectively: code X_i- in the first counter 4, the code Y_jthe second counter 11, code D_k- in divider with a variable division ratio of 13.

With the first clock pulse at time t₁codes X_iand Y_jcome on inputs mnimogo and multiplier multiplier codes 5.

Starting with the second clock pulse time t₂and the button code works code (frequency) in the multiplier codes will vary according to the formula:

$$P=(X_i+T)\times Y_j=X_i\times Y_j+Y_j\times T(1)$$

The code amount in the digital memory 6 (code phase) will change according to the formula:

$$S=P\times T=X_i\times Y_j\times T+Y_j+T^2(2)$$

If you type designation

ω₀=X_i×Y_j- primary circular frequency;

ω'=0.5Y_j- the rate of change of frequency;

T=Δt - clocked interval

the phase of the synthesized signal DCS will be described by the formula:

$${\phi }_i=S={\omega }_{0}t+0.5\omega \text{'}{t}^2(3)$$

Code phase φ_iis supplied to the code Converter 7, and senior level SGN, which is significant, is supplied to the control input of the inversion of the code Converter 7, and the remaining discharges through the code Converter 7 receives information on the inputs of the DAC 8.

If SGN=0, the DAC 8 is supplied direct code phase, and if SGN=1, the DAC 8 is fed back code phase.

In the DAC 8 is formed of the "step" signal "triangular" shape. After filtering in low-pass filter 9, which has a cutoff frequency equal to half the clock frequency at the output of the DCS signal is formed with a linear frequency modulation:

$$u_c(t)=U_{0}sin\left({\omega }_{0}t+0.5\omega \text{'}{t}^2\right)mi>(4\text{)}$$

The divider with a variable division ratio of 13 serves to control the rate of change of frequency, the more code D_kthe smaller the rate of change of frequency.

In the proposed digital synthesizer has the capability to control the frequency of the output signal, for example, to transmit an information message in the chirp mode, changing the code of the multiplier Y_j.

This disease you can create a signal with a quadratic law change frequencies. If you start both counters, the first counter code will change according to the formula: X=X_i+T

and in the second counter by the formula: Y=Y_j+T/D_k

Then, the signal frequency will change according to the formula:

During this phase of the synthesized signal will vary according to the formula:

$$S=(X_i+T)\times \left(Y_j+T/D_k\right)\times T=X_i\times Y_j\times T+X_i\times T^2/D_k+Y_j\times T^2+T^3/D_k(6\text{)}$$

Thus, this digital computing synth has more features and can generate signals with linear and quadratic law change frequencies, and have the option to send an informational message in the chirp mode.

Literature

1. As the USSR №1774464. MCI H03B 19/00. Digital frequency synthesizer / Ryabov I., N. Ryabova, Uryadov V.P... Appl. 30.08.1990. Publ. 07.11.1992. Bull. No. 41. - 4 S.

2. RF patent №2143173. IPC H03L 7/18, H03B 19/00. Digital frequency synthesizer / Ryabov I. Ryabov, I. Appl. 04.02.1999. Publ. 20.12.1999. Bulletin no.35. - 6 S. (prototype).

Digital synthesizer containing serially connected reference generator and the power generation and delay; a second memory register, the input of which is digital input digital synthesizer; sequentially connected to the first counter, a multiplier codes, digital drive, the code Converter, digital to analog Converter and a low pass filter whose output is an analog output digital synthesizer; the outputs of the shaping unit and the delay is connected to the clock inputs mnimogo, the multiplier and the product of multiplier codes, as well as to the clock inputs of the digital memory and digital to analog Converter, wherein the introduced first and the third memory register, a second counter, the divider with a variable division ratio, while digital inputs digital synthesizer are the inputs of the first and third memory registers; the output of the first memory register connected to the input of the first counter; the output of the second memory register connected to the input of a second counter and a second counter connected to the input of multiplier multiplier codes; the output of the third memory register connected to the input of the divider with a variable division ratio, the yield of the latter is connected to the clock input of the second when etchika; the outputs of the shaping unit and the delay is connected to the respective clock inputs of the first counter, a divider with a variable division ratio.