Method and device for dynamic scaling of frequency of frequency automatic adjustment scheme for microprocessors |
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IPC classes for russian patent Method and device for dynamic scaling of frequency of frequency automatic adjustment scheme for microprocessors (RU 2461961):
            
 Method and device for dynamic scaling of frequency of frequency automatic adjustment scheme for microprocessors / 2461961
Frequency automatic adjustment scheme contains many generator complexes designed for output signal generation, control circuit configured for selective feeding of output signal of the first generator complex from multiple generator complexes to the output of timing signal and changing of "rough" output frequency of the first generator complex from the first range of "rough" frequencies to the second range of "rough" frequencies when synchronisation from feedback line is stopped as a response that necessary operating frequency of output signals is within the second range of "rough" frequencies, note that "rough" output frequency of the first generator complex remains fed to the output of timing signal; switching device configured for selective connection of the first generator complex with feedback line, note that when control circuit sets the output signal of the first generator complex to the timing signal output synchronised and non-synchronised output signals are received correspondingly, when the first generator complex through switching device is connected to feedback line or when switching device disconnects the first generator complex from feedback line.
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FIELD: radio engineering. SUBSTANCE: frequency automatic adjustment scheme contains many generator complexes designed for output signal generation, control circuit configured for selective feeding of output signal of the first generator complex from multiple generator complexes to the output of timing signal and changing of "rough" output frequency of the first generator complex from the first range of "rough" frequencies to the second range of "rough" frequencies when synchronisation from feedback line is stopped as a response that necessary operating frequency of output signals is within the second range of "rough" frequencies, note that "rough" output frequency of the first generator complex remains fed to the output of timing signal; switching device configured for selective connection of the first generator complex with feedback line, note that when control circuit sets the output signal of the first generator complex to the timing signal output synchronised and non-synchronised output signals are received correspondingly, when the first generator complex through switching device is connected to feedback line or when switching device disconnects the first generator complex from feedback line. EFFECT: extension of generation range. 17 cl, 14 dwg
The technical field to which the invention relates The present disclosure relates in General to the field of circuits phase-locked loop for synchronization of microprocessors and, in particular, to methods and apparatus for dynamic frequency scaling schemes phase-locked loop for microprocessors. The level of technology Microprocessors perform computational tasks for a variety of applications. Improving processor performance is almost always necessary to achieve a more rapid and/or improved functionality through software changes. In many embedded applications, such as in portable electronic devices, energy saving is also an important task in the development and implementation of the processor. Many modern processors use the methods of dynamic voltage scaling and frequency, which include changing the operating frequency and voltage levels of the processor depending on the processing requirements for saving energy consumption. When the processor runs at a slower frequency synchronization, lower operating voltages can be used for power schemes, which leads to lower energy use. One of the common ways to change the hour is the notes includes a programmable circuit phase-locked loop (PLL), which operates on the same frequency, pauses, reprogrammed to work on a different frequency while PLL is suspended and restarted on the new required frequency. This approach can cause large fluctuations in current between the working frequency, which leads to the need to use a more reliable power source. It may also lead to stoppage of operation of the processor controlled by the output of the PLL, for many cycles during the working phases reprogram and restart. The PLL contains the generators, the frequency of which can be controlled by voltage or current. The generators are designed to operate within assigned operating frequency range. For example, one generator may be designed to work between 400 MHz and 800 MHz, while the other generator can be designed to work between 800 MHz and 1200 MHz. Effectiveness is reduced if you want to develop a generator for operation in the range between 400 MHz and 1200 MHz. The width of the operating range for the generator is directly proportional to its negative characteristics jitter. Therefore, the more the operating range for a given generator, the more relevant characteristics of the jitter. There is therefore a need to generate varying in a wide range of the of Ascot synchronization who have poor characteristics jitter. The INVENTION In one aspect of the disclosed scheme phase-locked loop that uses multiple generator systems. Diagram of a phase-locked loop includes an output clock signal and the multiple generator systems designed to generate output signals. Diagram of a phase-locked loop further includes a control circuit that is configured to selectively supply the output signal of one of the many generator complexes on the output clock signal. In another aspect of scheme phase-locked loop includes an input for receiving the reference signal, the output clock signal and the feedback signal synchronization in phase with the reference signal. Diagram of a phase-locked loop additionally includes multiple generator systems designed to generate output signals and the selective connection line feedback and output the clock signal. Diagram of a phase-locked loop also includes a control circuit configured to selectively supply the output signal of the first set of generator complexes on the output clock signal. In another aspect of the disclosed method of frequency change in the output signal circuit of the phase locked loop. In this way enter the desired frequency, which should work output circuit of the phase locked loop. Generating complex detaches from the line of the feedback circuit of the phase locked loop. Management of the disconnected generator complex is adjusted to generate a signal as output from the circuit phase-locked loop. Generating the complex is connected by line feedback for synchronization signal in phase with a reference signal when the signal has a frequency within the required frequency range. In another aspect of the disclosed method of changing the frequency of the output signal circuit of the phase locked loop. In this way the first generator complex is connected with the output circuit of the phase locked loop. The first generator complex detaches from the line of the feedback circuit of the phase locked loop. Enter the required frequency on which to operate the output signal circuit of the phase locked loop. Turns on the second generator complex. The second generator complex is managed in digital form to generate a signal in the frequency range that contains the desired frequency. The first generator complex detaches from the output of the circuit phase-locked loop. The second generator complex connects the I output of the circuit phase-locked loop. Implies that other ways of implementation will be obvious to experts from the subsequent detailed description, in which different ways of implementation shown and described for illustration. It is clear that the invention can be implemented in other different variants of implementation, and some of its details can be modified in various other aspects, without deviating from the invention. Accordingly, the drawings and detailed description be regarded as illustrative in nature and not as restrictive. BRIEF DESCRIPTION of DRAWINGS Fig. 1 is a functional block diagram of the processor. Fig. 2 - the first version of the implementation scheme of the phase-locked loop shown in Fig. 1. Fig. 3 is an alternative implementation of the generator complex, shown in Fig. 2. Fig. 4 is a graph of an exemplary output circuit of the phase locked loop shown in Fig. 1. Fig. 5 - the second variant of implementation of the scheme phase-locked loop shown in Fig. 1, which selectively connects the two generator output line and a line feedback. Fig. 6 is a graph of an exemplary output signal showing the operation of a simple switching scheme phase-locked loop. Fig. 7 is a graph of an exemplary output ofwhich is shown the operation abrupt switch to change the frequency scheme of the phase-locked loop. Fig. 8 is the third version of the implementation scheme of the phase-locked loop shown in Fig. 1. Fig. 9 is a graph of an exemplary output signal showing the operation of switching from the synchronization circuit of the phase locked loop. Fig. 10 is a graph of an exemplary output signal showing the operation of a complex switching circuit phase-locked loop. Fig. 11 is a sequence that shows how a simple switch to change the frequency of the output signal circuit of the phase locked loop. Fig. 12 is a sequence that shows how abrupt switch to change the frequency of the output signal circuit of the phase locked loop. Fig. 13 is a sequence that shows how to toggle sync for changing the output frequency of the circuit phase-locked loop. Fig. 14 is a sequence that shows how complex switch to change the frequency of the output signal circuit of the phase locked loop. DETAILED DESCRIPTION Fig. 1 depicts a functional block diagram of an exemplary processor 100, in which you can apply options for implementation. The processor 100 can be used in wired devices, such as a base station, a personal computer is (PC) and the like, and wireless devices such as mobile phone, laptop computer, pocket PC (PDA) and the like, the Processor 100 includes circuit 140 phase-locked loop (PLL)circuit 130 processing, a modem 120, a memory 110 and the circuit 150 I / o (In/In). The modem 120 receives modulated signals and converts them into baseband signals. The memory 110 stores data and commands for the circuit 130 processing. The circuit 130 performs processing commands stored in the memory 110, and sends the data and the management information to the schema 150 I / o. The circuit 150 I / o includes schemes which are a means of interfacing with displays, audio devices and other Circuit 130 processing communicates with the modem 120, a memory 110 and circuit 150 I / o system 160 tire. The PLL 140 receives the reference signal 145 synchronization. The reference signal 145 synchronization can be provided by using a quartz resonator, which is located outside of the processor 100. The PLL 140 generates a signal 148 synchronization, which is a multiple of the frequency of the reference signal, to start the synchronous devices, such as circuit 130 processing, a modem 120, a memory 110, the circuit 150 I / o and system 160 tire. The PLL 140 is programmable and can automatically change the frequency of the signal 148 synchronization depending on the processing requirements or external factors affecting the processor 10. The PLL 140 will be described additionally in connection with the discussion of Fig. 2-10. Professionals should be clear that there can be many types of processor 100. For example, there may be more than one scheme of the phase-locked loop for separate control of the different elements in the processor, including the 160 tire. In addition, one or more functional blocks depicted in the processor 100 may be omitted in certain embodiments of the implementation. Other functional blocks that may be among the components of processor 100 are not disclosed and are omitted for clarity. For example, the circuit 130 processing may include multi-stage pipeline, buffer fast conversion address, the cache data memory, etc. Fig. 2 - the first version of the implementation scheme of the phase-locked loop shown in Fig. 1. PLL 200 includes block 210 determination/comparison phase, the generator 215 swap charge, low-pass filter 220, the divider 230, the circuit 260 controls, generator complexes 240A-240B and does not create interference multiplexer 250. Generating complexes 240A-240B include generators 248A-240B and roughly adjust the output frequency of the generator so that it was within the selected frequency range. For simplicity, only the generator complexa will be described in detail in this document, but generating complex 240B may consequently be similar and use similar components, except that the generator complex 240A includes a current controlled oscillator 248A, which is designed to work at low frequencies, and generating complex 240B includes a current controlled oscillator 248B, which is designed for operation in the high frequency range. Additionally, generating complex 240A includes five digit register 242A, source 244A of the control current, the adder 246A and a managed switch 247A. In an alternative embodiment, the source 244A of the control current, and a current controlled oscillator 248a can be replaced with a source of control voltage and a voltage controlled oscillator depending on the particular application and all constraints on the design. Generating complex 240A in digital form is managed in such a way that the source 244A of the control current to generate the bias current 245 in response to the value of five digit register 242A. Five digit register 242A install software, and its value can be changed based on the load of the processor, the condition of the equipment or on both of them. A specific value five digit register 242A corresponds to a frequency range within which to operate the signal is the synchronization, the output of the PLL 200. Current controlled oscillator 248A is designed to generate vibrations in the low frequency range between approximately 400 and 800 MHz. For example, given thirty-two different values five digit register 242A and the operating range of the generator 248A equal to 400 MHz, each specific value five digit register 242A corresponds to the width of the output range of approximately 12,5 MHz. It should be noted that the size of a five digit register 242A and thus the size of the output range may vary depending on design constraints. When a managed switch 247A is connected to ground and, for example, is five digit register 242A equal to two, the exit 249A-controlled current generator 248A will be installed in a relatively constant value between about 425 MHz and 437,5 MHz. Exit 249A generator connected to not create interference multiplexer 250, which multiplexes the output signals of the generator complexes 240A and 240B. Similarly, in relation to generating complex 240B, which contains the generator 248B, designed to generate vibrations in a higher frequency range, when a managed switch 247B connected to ground and, for example, is five digit register 242B equal to two, the exit 249B-controlled current generator 248B will generate Coleman the I between 825 MHz and 837,5 MHz. For the stabilization and synchronization of the output clock signal an output clock signal is fed through a shared line feedback, defined by the divider 230, block 210 determination/comparison phase, the generator 215 swap charge and low-pass filter 220. The divider 230 is programmable and divides the output signal of the multiplexer 250 by an amount corresponding to the frequency of the generator complex 240A or 240B, divided by the frequency of the reference signal 203 to generate a signal 207 feedback. Block 210 to determine/compare phase takes as input the reference signal 203, such as an external signal 145, and the signal 207 feedback. Block 210 to determine/compare the phase compares the phase of the external signal 203 and signal 207 feedback to generate a differential signal. Generator 215 swap charge receives the differential signal and generates a control current. Low-pass filter 220 receives the control current and reduces frequencies above the limit frequency to dampen the input control signals from the generator 215 swap charge to generate a reduced control current 225. When generating complex 240A is connected to a low-pass filter 220 through a programmable switch 247A, reduced control current 225 stack or with positive or negative is considerable current 245A offset. Summarizes current controls the controllable current generator 248A synchronization signal 249A generator with a reference signal 203. It should be noted that the switches 247A and 247B are connected with a low-pass filter 220 mutually exclusive way. In this embodiment, the synchronized output signal gain, and when the appropriate switch of the generator complex is connected with a low-pass filter 220 and the output of the same generator complex is selected through not creating interference multiplexer 250. The output signal does not create interference multiplexer 250 is directed through an additional circuit 270 "divide by two" before transmission to the synchronous device. Additional circuit 270 "divide by two" protects from external influences synchronous devices that may not be suitable for processing high-speed transition frequencies and described in connection with Fig. 6. Circuit 260 controls connected to the switches 247A-247B and does not create interference multiplexer 250. To avoid control circuit output phase-locked loop frequency multiple generators, the switching operation between the outputs of the generator complexes delayed for three or more clock cycles of the generator. For this purpose, the circuit 260 controls may include a state machine to ensure that the button no short pulses or short cycles does not appear when switching the outputs of the generator complexes 240A-240B through the multiplexer 250. Circuit 260 controls the switches 247A-247B independently. In particular, the circuit 260 control determines whether to connect the switches 247A-247B ground or shared line feedback. Circuit 260 also controls the circuit 270 "divide by two" during simple way switch described in connection with Fig. 6, to change the frequency synchronization. Circuit 260 controls can optionally manage the contents of registers 242A and 242B to provide different ways of changing the frequency synchronization, which is described below. Circuit 260 controls takes as input information specifying the desired frequency, which should work scheme phase-locked loop. This input information can be based on the processor load, the condition of the equipment or on both of them. Circuit 260 controls may also communicate back to the device when the target frequency is reached. Fig. 3 is an alternative implementation of the generator complex 300, shown in Fig. 2, used in the schematic phase-locked loop. Generating complex 240A may be coupled with the reference voltage VFL310, rated voltage, which can be expected from the control circuit, when it is synchronized. Generator 248A can connect with VFL310 at the time the I calibration register values when you initialize the PLL. During calibration reference voltage set in the VFL310, and the currents "coarse" adjustment gradually change over the range. Measure the resulting frequency of the ICO for each installation of the register. During operation of the PLL in the steady state, if necessary, a new frequency, we choose the value of the register, which generates a frequency, very close to the desired frequency, with the corresponding input signal VFLtogether with the appropriate setting of the divider. Fig. 4 is a graph 400 changes the approximate frequency of the output clock signal circuit of the phase locked loop shown in Fig. 1. It should be noted that the continuous oscillation signal, shown in Fig. 4, receive without selecting additional circuit 270 "divide by two". In this example, the output clock signal at time 410 is clocked at 600 MHz and it should be changed for operation at a frequency of 1.2 GHz. At time 410 output clock signal control using generator complex 240A. Additionally, generating complex 240A is connected with a low-pass filter 220. At time 415 register 242A increase (and the corresponding coefficient of the divisor to determine divider 230) to increase the corresponding bias current generator 248A and thus cause an increase in the frequency of the output clock signal is. At time 420 generator 248A is in synchronization with an external reference signal 203. This cycle synchronized with the output signal of increasing the bias current and re-sync with the generator complexes 240A repeat until time 425. At time 425 it is necessary to increase the output frequency synchronization for value generator 248A. At time 425 scheme 260 control sets the offset by setting register 242B, sets the coefficient of the divider selects the generator complex 240B to control the output clock signal by switching the switch 247A to ground, switches the switch 247B line feedback and selects the output of the generator 249B to control the output clock signal. Generating complex 240B increases the frequency up to 1.2 GHz by increasing the value of the register 242B for three additional cycles. At time 430 in one embodiment, the implementation of additional circuit 270 "divide by two" is not used. In this embodiment, the output clock signal 280 will monitor the generator output 249B (shown as a solid line in Fig. 4). This alternative implementation has particular application when the synchronous scheme, managed output clock signal 280, designed to handle above the Oia at high frequencies. In another embodiment, at time 430, the circuit 260 controls increases the register 242B to achieve the target operating frequency. Also at time 430, the circuit 260 control activates the circuit 270 "divide by two" to divide into two output clock frequency, as shown by the dashed line 422. At the time 435 generator output 249B initiate synchronization with a reference signal 203. At the time 427 circuit 260 control deactivates the circuit 270 "divide by two" to provide opportunities to increase the frequency of the clock output signal synchronized to the target output frequency. It should be noted that although in Fig. 1 shows a diagram 270 "divide by two", you can use other factors, which include fractional divider or any other scheme of the divider, which reduces the frequency of the output clock signal. Lowering the frequency of the output clock signal to allow the generator to be synchronized with the target frequency protects synchronous schemes, which may not be designed to handle the excess of the rate on such a high operating frequency. Even if synchronous circuits are designed to handle the exceedance of the target frequency, this design usually requires an increase in the operating voltage of the synchronous circuits made thereby. The lower frequencies of the output clock signal, as described, eliminates the need to use synchronous control schemes is the increased operating voltage. Fig. 5 - the second variant of implementation of the scheme phase-locked loop shown in Fig. 1, which selectively connects the two oscillators line feedback and output line. Fig. 5 contains all the elements described in Fig. 1, except the schema 270 "divide by two". Additionally, the circuit 500 phase-locked loop includes not creating interference multiplexer 530, which provides independent connection between a line feedback, defined by the divider 230, block 210 definition phase, low-pass filter 220, and the output of one generator complexes 240A-240B. For example, the schema 560 control can be configured to select the output of the generator complex 240A so that he was connected with the output 540 of the clock signal using the control does not create interference multiplexer 250, and to select the output of the generator complex 240B for connection with a line of feedback provided by the control does not create interference multiplexer 530 and switch 247B. Diagram 500 of the phase-locked loop eliminates excess changing the control output clock signal between the generator complexes. In addition, this alternative implementation which allows the output clock signal to operate without synchronization, as described in connection with Fig. 6. Fig. 6 is a graph 600 of exemplary output clock signal, which embodies the way a simple switch to change the output clock signal to achieve the target frequency 615. Graph 600 depicts the output signal of the generator complex 240B and the output clock signal 540 in the frequency domain. The graph 600 output clock signal 540 controls the generator complex 240B. At time 601, the output of the generator complex 240B controls the output clock signal 540 so that he worked at a frequency of 800 MHz. At time 605 way to easily switch begins by switching 247A on "earth" and select the generator complex 240A for connection with a line of feedback. In the result, the generation frequency generator complex 240B and thus the output clock signal 540 is stopped and started without synchronization at a slightly lower frequency. The term "synchronization" refers to the management of the output clock signal of the PLL using a generator that is not connected to line feedback PLL. Professionals should be clear that the term "no sync" may also include removing one of the signal PLL on line feedback circuit phase-locked loop. It should be noted that the clock signal without synchronization, the conclusion is that for a given bias voltage, in General operate at a lower frequency than the output clock signal with the synchronization for the same specified offset. The reduction is within the range defined by the value in register 242B, for generating complex 240B. At time 610 register 242B increase with schema 560 control, which leads to the fact that the generator output 249B and the output clock signal 540 increase for the next operating frequency range. In other embodiments, the implementation of the increase of the working frequency range may include frequency hopping through the next working frequency range. Register 242B continuously increase to ensure that changes the output frequency of approximately 5 MHz/μs. As the scheme is a phase-locked loop operates without synchronization, the working frequency at each increment is slightly lower than it would be when working with synchronization. In addition, since the generator complex 240B controls the output without connection line feedback coefficient of the divisor does not matter while changing the frequency of the generator complex 240B. Additionally it should be noted that the amount of increase between each level of the output clock signal or the step shown in Fig. 4 and 6 are selected in Illustra the positive purposes, and it can not directly be displayed on the frequency bands defined by the values of the five digit register. In addition, the frequency characteristics of the generators are not as linear as shown in Fig. 4 and 6. Frequency curve of the generator is usually bent, but it is monotonic, as shown. Fig. 7 is a graph 700 of an exemplary output signal, which shows how abrupt switch to change the frequency of the clock signal to achieve the target frequency of 1 GHz. The output clock signals shown in Fig. 7, can be respectively generated using the schema 500 phase-locked loop. Graph 700 shows an abrupt switch to change the frequency from the operating frequency of the clock signal 600 MHz to 1 GHz. Graph 700 depicts the output frequency generator 735 complex 240A and the output frequency generator 730 complex 240A. The solid line indicates the frequency 540 output clock signal circuit 500 phase-locked loop. The dotted line indicates that the corresponding generator set is not selected as the output of the circuit 600 phase-locked loop. At time 705 generator complex 240A works with synchronization at a frequency of 600 MHz and is selected to control the output clock signal. In addition, at a frequency less than 1 GHz generator sets is 240B works without synchronization and is not selected. If the generator complex 240B is not yet enabled, the corresponding register can be changed to a value that will lead generator complex 240B to work at a frequency less than 1 GHz. At time 710 line feedback disconnect from generator complex 240A, prompting him to work without synchronization and inducing them to reduce the frequency of the output clock signal with 600 MHz. In addition, the line is feedback connected to the generator complex 240B and determine the ratio of the divider 230, thereby increasing the output signal of the generator complex 240B. In the time period 715 generator complex 240B is in synchronization with a reference signal 203. Meanwhile, the output of the generator complex 240A remains selected to control the output clock signal at a frequency of less than 600 MHz. At the time 725 after generating complex 240B starts with a synchronization scheme 560 control selects the generator complex 240B to control the output clock signal by switching the multiplexer 250, causing the frequency of the output clock signal to increase from less than 600 MHz to 1 GHz without exceeding the output clock signal. Generating complex 240A can be switched off while the generator complex 240B controls the output clock signal until the next target frequency is not the Dol is to be provided by the generator complex 240A. It should be noted that the circuit 500 phase-locked loop may generate the output clock signal, whose frequency is abruptly changed between any two combinations of the frequencies of the output clock signal in either direction, with one frequency of the output clock signal generated using a generator complex, and another frequency of the output clock signal generated by another generator complex. Fig. 8 is the third version of the implementation scheme of the phase-locked loop shown in Fig. 1. Diagram 800 of a phase-locked loop includes a feedback elements, such as those described in Fig. 2. Diagram 800 of a phase-locked loop also includes generating complexes 840A-840D, circuit 860 control and does not create interference multiplexers 855 and 865. Generating complexes A and 840 In, all together called generator complexes lower frequencies, designed to generate signals at a frequency between 400 MHz and 800 MHz. Generating complexes S and 840D, all together called generator complexes upper frequencies, are designed to generate signals at a frequency between 800 MHz and 1200 MHz. Each generator complexes connected to the multiplexers 855 and 865. Scheme 860 management configure to connect any generator complex is in the output clock signal diagram 800 of a phase-locked loop. Additionally, the circuit 860 control to configure independent of any connection of the generator with the line of the feedback circuit 800 phase-locked loop. Scheme 860 control can be connected to the same generator complex and with the output clock signal line feedback, or can connect one generator complex line feedback, and the other generator complex with an output clock signal. Scheme 860 management can generate various ways of switching the clock signal, changing what the generator controls the line of feedback, and what the generator controls the output of the PLL. Fig.9 is a graph showing a method of switching synchronization sample of the output signal generated by circuit 800 phase-locked loop., Scheme 860 controls the sequence of connection and disconnection of the generator complexes of the same range (i.e. generating complexes lower frequency) to increase the output frequency synchronization. By doing so, the output clock signal 905 is generated by switching between generator complexes. When considering Fig. 9 the solid line indicates the output clock signal 905 schema 800 phase-locked loop. The dashed line points is t, that the corresponding generator set is not selected as the output of the circuit 800 of the phase-locked loop. Before the time generator 910 complex 840A works with sync and selected to control the output clock signal 905. At time 910 include a generator within a generator of complex 840B, another bias circuit for lower frequencies, and it begins to work without synchronization. Generating complex 840B initialize with its case management within the frequency range of approximately 700 MHz. At time 920 scheme 860 control disconnects the generator complex 840A from the line of feedback, which leads to reduction in the frequency of the output clock signal 905. In addition, at time 920 scheme 860 control connects the generator complex 840B line feedback and programs the divider 230, which causes the output frequency of the generator complex 840B increases to approximately 700 MHz. At time 930 generator complex 840B begins to work with sync. Scheme 860 control disconnects the generator complex 840A from the output clock signal and connects the generator complex 840B with the output clock signal, resulting in higher frequencies up to 700 MHz without exceeding the frequency of the output clock signal. In this example, the output signal 905 this cycle switch between generator complexes are repeated five times, while the output clock signal 905 will not work at 1.2GHz. Fig. 9 also shows the switching between generator complexes lower frequency (shown as region 940), generator complexes upper frequency (shown as region 960) and between the lower generator system of the lower frequency and the upper generator system of the lower frequency (shown as region 950). Fig. 10 is a graph of an exemplary output signal 1005, which shows how complex switch to change the output circuit of the phase locked loop. How complex switch similar to the way a simple switch described in Fig. 6, except that the circuit 800 of the phase-locked loop removes the excess from the output clock signal by switching to another generator complex. Although the above exemplary oscillating output clock signals as shown in the General case, changing growing method, specialists should be clear that the approximate oscillatory output clock signals can alternatively be changed descending way. Fig. 11 is a sequence showing a method 1100 of a simple switch to change the frequency of the output signal circuit of the phase locked loop. At step 1110 transmit the desired frequency at which dollars the yen to operate the output signal circuit of the phase locked loop. For example, the CPU utilization may increase, thus requiring a higher frequency clock pulses to handle the load for a shorter period of time. At step 1120 break the timing generator that controls the output of the circuit phase-locked loop with a reference signal, such as reference signal 203. The termination of the synchronization control of the generator leads to a decrease in the frequency of the output circuit of the phase locked loop. At step 1130 change tool digital control, such as a register 242A, which manages managing generator to change its "gross" output frequency, which leads to an increase or decrease in the frequency of the output signal of the circuit phase-locked loop frequency depending on changes in the control generator. Two variants of the method simple switch shown in Fig. 11. Steps 1140 and 1150 determine one of the embodiments, while the stages 1160, 1170, 1180 and 1190 define another variant implementation. At step 1140, the method 1100 determines whether the "coarse" frequency of the output signal of the generator within the range of the required output frequency. For example, the desired frequency can be defined as 1.1 GHz. The method determines whether the range defined by the value of the register, which operated the t corresponding generator complex, frequency of 1.1 GHz. If Yes, then the method 1100 proceeds to step 1150, where synchronizing the generator with a reference signal by setting the coefficient of the divisor and the connection of the control of the generator with the line of the feedback circuit of the phase locked loop. If not, then the method 1100 proceeds to step 1130 to change numerical values, such as the value of the register 242A. If you want to switch the output of the circuit phase-locked loop frequency to a higher frequency, the higher the value of the register will cause an abrupt change in the frequency of the output clock signal up to the next "coarse" frequency range. If you want to switch the output of the circuit phase-locked loop frequency to a lower frequency, lowering the value of the register will cause an abrupt change in the frequency of the output clock signal down to the next "coarse" frequency range. In the second embodiment, and returning to step 1130, the method 1100 moves to step 1160. At step 1160, the method 1100 performs the function prediction, determining whether will the following change "coarse" frequency of the output signal generator to the output frequency, which is within the range of the required output frequency. If not, then the method 1100 proceeds to step 1130, where the generator is adjusted for operation in the second frequency range. If Yes, then the method 1100 proceeds to step 1170, which divide the frequency of the output signal circuit of the phase locked loop. For example, the output can be divided by the inclusion schemes "divide by two", such as circuit 270. The "divide by two" in one of the embodiments can be enabled before the last stage without synchronization. In another embodiment, the scheme of "division by two can be turned on after the last stage of the work without synchronization. In both of these two options for the implementation of the scheme "divide by two" include before switching circuit configuration synchronization. At step 1175 adjust the generator that controls the output of the circuit phase-locked loop through the divider so that its output frequency was within the range of the required output frequency. At step 1180 perform synchronization with a reference signal generator that controls the output of the circuit phase-locked loop, by setting the ratio of the divider and the connection of the control of the generator with the line of the feedback circuit of the phase locked loop. As soon as the generator starts to work with synchronization, the method 1100 proceeds to step 1190 where the frequency of the output signal circuit of the phase locked loop is no longer divided. For example, dividing the frequency of the output signal can no longer is made by disconnecting the circuit 270 "divide by two". Fig. 12 is a sequence showing the method 1200 abrupt switch to change the frequency of the output signal circuit of the phase locked loop. At step 1210 enter the desired frequency, which should work output circuit of the phase locked loop. At step 1220 stop synchronization with a reference signal of the first oscillator that controls the output of the circuit phase-locked loop. At step 1230 includes a second generator. The second generator is not connected to control circuit output phase-locked loop. At step 1240 the second generator is digitally controlled so that it generates vibrations within a frequency range that includes the desired frequency. At step 1250 perform synchronization with a reference signal of the second oscillator by connecting it independently of the first generator line feedback circuit phase-locked loop. At step 1260, the first generator switch so that it will not operate the output circuit of the phase locked loop, and the second generator switch so that it ran the output of the circuit phase-locked loop. The first generator is optional, you can then turn off. Fig. 13 is a sequence showing a method of switching synchronization to change the frequency you are the one of the signal circuits of the phase-locked loop. At step 1310 enter the desired frequency, which should work output circuit of the phase locked loop. At step 1320 stop synchronization with a reference signal generator that controls the output of the circuit phase-locked loop. At step 1330 another generator digital control to change its "gross" output frequency. Depending on the required direction of switching of the output signal change may be to a higher or lower frequency. At step 1340 initiate synchronization with a reference signal of another generator. For example, another generator connected to a line feedback circuit phase-locked loop. At step 1350, as soon as it is synchronized, other generator switch to control the output of the circuit phase-locked loop. At step 1360, the method 1300 determines whether the coarse output frequency of the control oscillator within the range of the required output frequency. If Yes, then the method 1360 finish. If not, then the method 1300 proceeds to step 1320, where the generator that controls the output of the circuit phase-locked loop, works without synchronization. Fig. 14 is a sequence that shows a method 1400 complex switch to change the output frequency of the circuit phase-locked loop. On the stage 1410 enter the desired frequency, which should work output circuit of the phase locked loop. At step 1420 stop synchronization with a reference signal generator that controls the output of the circuit phase-locked loop. At step 1430 generator digital control to change its "gross" output frequency when it is disconnected from the line of the feedback circuit of the phase locked loop. At step 1440, the method 1400 performs the function prediction. In particular, it determines whether a subsequent change in the "coarse" frequency of the output signal generator to the output frequency outside the range of the desired output frequency. If not, then the method 1400 proceeds to step 1430 to change the "gross" output frequency while working without synchronization. If Yes, then the method 1400 proceeds to step 1450, which include a second generator. At step 1460 the second generator is digitally controlled so that it generates oscillations in the range that includes the desired frequency. At step 1470 perform synchronization with a reference signal of the second oscillator. At step 1480, the first generator switch for stopping the control circuit output phase-locked loop, and the second generator switch to control data access. The various illustrative logical blocks, modules, circuits,elements and/or components, described in connection with open options implemented, it is possible to carry out or implement by using the universal CPU, processor, digital signal processing (PCOS), a specialized integrated circuit (List), user-programmable gate arrays (PWM) or other programmable logic component, discrete circuits or transistor logic, discrete hardware components, or any combination thereof designed to perform the described functions. Universal processor may be a microprocessor, but the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor can also translate as a combination of computing components, such as a combination PCOS and microprocessor, multiple microprocessors, one or more microprocessors with the core PCOS, or any other such configuration. The methods described in connection with open options implemented, it is possible to implement directly in hardware, in a software module executed by a processor, or combinations thereof. A software module may reside in OP (RAM), flash memory, read-only memory (ROM), EPROM (erasable programmable permanent memory the devices), EEPROM (electrically erasable programmable ROM), registers, hard disk, removable disk, CD-ROM (CD-ROM) or on data media of any other species known from the prior art. The media data may be associated with the processor so that the processor can read information from the data medium and to record information on it. Alternative storage medium may be integral to the processor. Although the invention disclosed in the context of embodiments, it is clear that professionals can use with a wide variety of implementations that are compatible with the above discussion and the following claims. 1. Diagram of a phase-locked loop, comprising: 2. Diagram of a phase-locked loop according to claim 1, additionally containing: 3. Diagram of a phase-locked loop according to claim 1, additionally containing: 4. Diagram of a phase-locked loop according to claim 1, additionally containing: 5. Diagram of a phase-locked loop according to claim 2, additionally containing: 6. Diagram of a phase-locked loop according to claim 2, in which the control circuit switches the generator set of complexes between the control line for the feedback and the output clock signal to generate a simple switching operation. 7. Diagram of a phase-locked loop according to claim 2, in which the control circuit switches the generator set of complexes between the control line for the feedback and the output clock signal to generaloperation abrupt switch. 8. Diagram of a phase-locked loop according to claim 2, in which the control circuit switches the generator set of complexes between the control line for the feedback and the output clock signal to generate the switch operation with synchronization. 9. Diagram of a phase-locked loop according to claim 2, in which the control circuit switches the generator set of complexes between the control line for the feedback and the output clock signal to generate a complex operation switch. 10. Diagram of a phase-locked loop, comprising: 11. Diagram of a phase-locked loop of claim 10, further containing a control circuit, and a control circuit configured to selectively disconnect the first generator on-line feedback and connection of the second generator complex of multiple generator systems with in-line feedback when the next change "gross" output frequency is outside the frequency range of the first generator complex. 12. Diagram of a phase-locked loop according to claim 11, in which the control circuit additionally konfigurirovanija selective disconnection of the first power generation complex on three or more cycles of the generator, moreover, the control circuit includes a state machine configured to substantially eliminate short cycles that appear when switching between the output signal of the first generator of the complex and the output signal of the second generator of the complex through the multiplexer. 13. How to change the output frequency of the circuit phase-locked loop containing steps are: 14. The method according to item 13, additionally containing a stage, on which: 15. The method according to item 13, in which the control is disconnected generator facility is digital. 16. How to change the frequency of the output signal circuit of the phase locked loop containing steps are: 17. The method according to item 16, further containing phase, which stops power to the first generator complex after first generating complex disconnect from the output of the circuit phase-locked loop.
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