Stand for studying electronic automation means

FIELD: training devices engineering, possible use for getting practical skills of working with digital electric circuits, digital-analog and analog-digital transformers, researching dynamics of operation of digital devices, performing computer measurements.

SUBSTANCE: stand for studying electronic automation means contains counter 1, decoder of binary code to positional code 4, register 6, block of switches 7, analog adder 9, block of triggers 10, six commutators 2,3,5,8,11,12, indication block 13, input-output block 14, logical elements block 15, set of diodes 16, set of resistors 17, set of capacitors 18, set of comparators 19, control block 20, voltage adjuster 21, generator 22, voltage meter 23 and type-setting field 24 with a set of connector links 25. by means of stand it is possible to study both elementary logical elements and complex electronic circuits in static and dynamic operation modes. Possible automatic construction of temporal diagrams, performing of computerized measurements and printing of results of operation all increase didactic capabilities of device.

EFFECT: expanded nomenclature of studied electronic circuits while increasing didactic capabilities for studying of these.

5 cl, 12 dwg

The invention relates to the field of training devices and can be used to obtain practical skills of work with digital electrical circuits, converters analog signals into a digital code, the study of the dynamics of digital devices.

The closest technical solution, selected as a prototype, is a stand to learn the basics of digital electronics (EN, 2214628, 7 G 09 At 23/18). The stand contains a control unit, composition field, block trigger block diode splitters, the unit logic elements, the decoder binary code in position, two switches, a display unit, symbolic indicator and unit code of variants of tasks.

The disadvantage of this prototype is a limited set of the devices studied, in which there is no possibility of the Assembly and study of d / a and a / d converters (DAC and ADC). In addition, the device has a low didactic opportunities, as it allows to memorize and transmit to the computer the status array checkpoint study of electronic circuits for automatic construction timing of their work and make calculations.

The problem solved by the invention is the expansion of the study of electronic circuits with increasing educational opportunities of studying.

the shown task is performed by that stand for studying electronic automation, containing two switches, the decoder binary code in position, a set of jumpers, connectors and composition field, the nests of which the unit is connected triggers, the unit logic elements, a set of diodes, the display unit and the control unit, inputs of the third, fourth, fifth and sixth switches, block I / o, counter, register, generator, switch block, the analog adder block Comparators, a voltage regulator, a set of resistors, a set of capacitors and a voltmeter.

The proposed solution has the following distinctive features of the prototype characteristics:

- a wider range of elements to build complex devices discrete automation;

- presence of elements with different degree of integration to simplify the complex circuits;

- using multibit switches to perform the group of compounds;

- the existence of a block I / o with internal memory for data recording and issuing them to the computer.

Functionally complete set of logical elements allows to collect and analyse synthesized by means of Boolean algebra, combinational logic circuits: switches, encoders, decoders, converters codes, triggers, etc.

A set of pre-defined triggers allows post is OIT based on them and explore the work of a variety of counters, registers and other devices discrete automation.

The counter register, the decoder are also "elementary building blocks" of more complex devices - they are used to build various analog-to-digital converters.

For pre-processing analog signals and build a simple digital to analog converters stand contains a switch block, a block of Comparators and analog adder. The unit allows to deliver on its outputs one of two input voltages in accordance with a digital code received at control inputs of the block. Block Comparators consists of several voltage Comparators, the first inputs are combined, and the signal at the output of each comparator is a logic level "0"when the potential at its second input is less than the potential at the first input, and a logic "1" otherwise. The performance of the analog adder with the resistors that are related as 1:2¹:2²:...2^Nit is necessary to obtain at its output a voltage proportional to the input code received at control inputs of the switch block.

To verify the collected schemes in step mode, use the display unit.

Input actions are buttons and switches of the control unit, the outputs of which is s for suppressing bounce of contacts connected RS-triggers.

To investigate the operation of the circuits in the dynamics, the input specified by the generator, and the current status of the control points are entered with the selected clock frequency to the memory block I / o, where they can be read into the computer. The computer running the appropriate software works as a logic analyzer - multi-indicator time diagrams.

In the study of complex logic circuits, have a regular internal structure, do not require a large number of logic elements to recreate the entire structure, as the stand allows you to explore and collect it from the elements with varying degrees of integration.

To make a group of compounds used multibit managed switches that simplifies and speeds up the Assembly process and improves the reliability of the schemes and the visibility of their study.

The ability to automatically build time diagrams, execution of the computer measurement and outputting to the printer results raise the didactic potential of the device.

Given a set of features characterizing the stated object, leads to the achievement of the technical result, which provides the solution of the invention.

The analysis of the prior art shows that it is not known stand, which is characterized by p is snake, identical to all the essential features of the present invention. This speaks to the novelty of the proposed technical solutions.

The proposed solution is applicable, workable, feasible and reproducible, as can be produced in batch and single production using commercially available components, and therefore corresponds to a condition of patentability "industrial applicability".

Figure 1 shows the structure of the training stand, figure 2 - scheme of the block I / o figure 3 - option internal structure of the analog adder, 4 - option schemes of the switch block, figure 5 - option scheme of the control unit, 6 is a variant of the internal structure of the generator, figa diagram of parallel digit ADC 7b is an example of compiling tables of survey results parallel digit ADC, Fig - example build on the patterned field parallel digit ADC figure 9 - diagram of the four-bit successive approximation ADC, figure 10 - example of an Assembly into a type field, a four-digit serial ADC approximation, figa diagram of the four-digit ADC successive balancing, figb sample preparation state table four-digit ADC successive balancing, Fig - example build on the patterned floor is a four-digit ADC successive balancing.

Stand for studying electronic automation (figure 1) contains the count of 1, the first switch 2 (S1), the second switch 3 (S2), the decoder 4 binary code in position, the third switch 5 (S3), the case of 6, unit 7 of the switch, the fourth switch 8 (S4), the analog adder 9, block 10 triggers, the fifth switch 11 (S5), the sixth switch 12 (S6), unit 13 of the display unit 14 of the I / o block 15 logical elements, a set of 16 diodes, a set of resistors 17, a set of capacitors 18, block 19 of the Comparators, the control block 20, the voltage regulator 21, the generator 22, the voltmeter 23, inlaid box 24 with a set of jumper connectors 25. To dial field 24 is connected to the counter 1, six switches 2, 3, 5, 8, 11 and 12, the decoder 4, the case of 6, unit 7, an analog adder unit 9, unit 10 triggers the display unit 13, block I / o 14, block 15 logical elements, a set of 16 diodes, a set of resistors 17, a set of capacitors 18, block 19 analog Comparators, the control unit 20, the voltage regulator 21, the generator 22 and the voltmeter 23. The output of counter 1 is connected to the inputs of the first 2 and second 3 switches and to the first input of the fifth switch 11. The outputs of the fifth 11 and 12 sixth switches form a multibit data bus connected to the input of the display unit 13 and the data input unit I / o 14, the input query data, output data and output confirmation goth is vnesti data which are the respective outputs of the stand and can be connected to a computer (not shown in figure 1). The output of the first switch 2 is connected to the input of the decoder 4 binary code in position, the output of the second switch 3 is connected to the input of the register 6 and to the input of the third switch 5, the output of which is connected to the control input of the switch block 7, the output of which through the fourth switch 8 is connected to the analog adder 9. The output of the register 6 is connected to the first input of the sixth switch 12, the second input is connected to the first output unit triggers 10, the second output of which is connected to the second input of the fifth switch 11. Block I / o 14 (figure 2) contains a module of RAM 14.1, the address counter 14.2, trigger 14.3, generator, single pulses 14.4, the pulse generator write 14.5, the frequency divider 14.6, switch 14.7, click "ENTER" 14.8, element And 14.9, the multiplexer 14.10 and indicator 14.11. Entrance digging ENTER 14.8 connected to logical "1"and the output to the set input of the trigger 14.3, direct the output of which is connected with the control input of the multiplexer 14.10 and the input of the start of the single pulse generator 14.4, and the inverted output - indicator 14.11, entry permit writer module RAM 14.1 and a second input element "And" 14.9 whose output is the output ready (RA) data block 14. The pulse generator write 14.5 connected to the frequency divider 14.6 whose outputs are connected to the corresponding input of the m switch 14.7. The first multiplexer input 14.10 is the input data request (RQ) block I / o 14 and connected to the first input element And 14.9. A second multiplexer input 14.10 connected to the output of the switch 14.7, and the return to the incremental input of the address counter 14.2, the reset input of which is connected to the generator output single pulse 14.4. The reset input of trigger 14.3 connected to the output of the overflow of the address counter 14.2, the other output of which is connected to the address input of the RAM module 14.1, input data which is input data (DI) block 14, and the output of the output data (DO) block I / o 14.

The device operates as follows.

In the study of combinational logic circuits, the learner sets the buttons and switches of the control unit 20 (Fig 1, 5) input ("0", "1") in the target logic element or circuit comprising multiple logical block elements 15, the control point which is connected to the display unit 13 for visual inspection of their condition.

Similarly studied the work of trigger circuits of different patterns, where the schema is collected using block elements triggers 10 and the logical block elements 15.

When studying the work of the counters and registers the learner on methodological task collects on the patterned field 24 different types of counters and registers, in adnie condition which is specified by the control unit 20, and status of inputs and outputs collected diagram shows the indicators of the display unit 13.

When studying the operation of the combined devices, such as digital-to-analog or analog-to-digital converters, used analog adder 9 (3), unit 7 (figure 4), and a block of Comparators 19. To set the input effects are variable and the reference voltage, which is connected in the circuit from the respective sockets of the voltage regulator 21 with jumpers connectors 25. The voltage level control is carried out by the voltmeter 23.

Sets of resistor 17 and capacitor 18 are used to form the integrating and differentiating chains, delay lines, and to build a resistor voltage dividers. A set of diodes 16 is used to build shapers, combiners, splitters.

To investigate the operation of the circuits in the dynamics, the input specified by the generator 22 (6), and the current state of the checkpoint is recorded in the memory unit I / o 14 with a clock frequency set by the position of the switch 14.7. They can be read into the computer via a standard interface.

Block I / o 14 (2) works as follows. In the initial state, the address counter 14.2 and trigger 14.3 reset. The low level signal from the direct output of flip the EPA 14.3 connects the first input of the multiplexer 14.10, connected to the input of the data request block I / o 14, incremental counter input 14.2. And a high signal from the inverted output of the trigger 14.3 sets the RAM module 14.1 in read mode and permits the formation signal the availability of data. Indicator 14.11 glows, indicating the readiness of the block I / o 14 to communicate with the computer. When receiving a request signal of data stored in the module memory 14.1, the output element And 14.9 formed the ready signal, whereby the data stored in the memory cell with address "0"can be read from the output of the RAM module 14.1. Withdrawal request signal data state of the address counter 14.2 increases, and the output are the data stored in the next memory cell. Next, the reading process of the memory contents is repeated. To write data to the memory used by the sync pulses produced by the generator 14.5 pulse recording, and supplied to the input of frequency divider 14.6. To set the data in the memory, it is necessary to select the desired clock frequency switch 14.7 and press "ENTER" 14.8. When this trigger 14.3 cocked, the signal with its direct output to the input of the generator 14.4, which produces a single pulse counter reset address 14.2, and the control input of multiplexer 14.10, which connects to Inc. agentname input of the address counter 14.2 output switch 14.7. And the low level signal from the inverted output of the trigger 14.3 prohibits the formation of tone data and sets the RAM module 14.1 in the recording mode. The indicator 14.11 goes out, and the data supplied to the input of block I / o 14, is written with the desired clock frequency in the cell module of RAM 14.1 to overflow of the address counter 14.2, the overflow signal which resets the trigger 14.3 and translates the block I / o to its original state.

Let's consider several examples of a student with a stand.

1. Trained on methodological task builds a parallel double-bit ADC, the circuit of which is shown in figa. Assembly is performed using resistors set of resistors 17 and analog Comparators block 19 by connecting the appropriate slots dialer field 24 with jumpers 25, as shown in Fig. In this case, the switches 11 and 12 must be set to "0". The learner sets the compliance voltage input Ux, which is fed into the circuit from the voltage regulator 21 and is displayed on the voltmeter 23, and the output code block analog Comparators 19, which is indicated by the LEDs of the display unit 13. The results are recorded in table (figb). The thresholds of the Comparators block 19 can be altered by setting the discrepancies between the data values of the reference voltage IEP on the voltage regulator 21. To convert the weight of the code in binary, the learner can be synthesized by means of Boolean algebra simple combinational circuit incomplete encoder and easy to assemble from existing logical elements.

2. Trained on methodological task performs the Assembly of the four-bit successive approximation ADC, the circuit of which is shown in Fig.9, inlaid box 24 (see figure 10). It uses elements of your trigger block 10, block of logic elements 15 and block analog Comparators 19, the counter is 1, the switch block 7, the analog adder 9, the register 6. To build the driver signal "reset", which is required to install the schema in the initial state after power-up that uses the elements of the sets of diodes 16, resistor 17 and capacitor 18. The connection of the outputs of the counter 1 with the inputs of the register 6 is made by setting switch 3 (S2) in position "1"; with control inputs of the switch block 7 - mounting the switch 5 (S3) in position "1"; with bits 0...3 input display unit 13 - mounting the switch 11 (S5) to position "1". The outputs of the register 6 is connected to the bits 4...7 of the input display unit 13 installing the switch 12 (S6) in position "1". After power from the generator 22 to the counter 1 receives the rectangular pulses. Code at its output suitable closed the switches of the switch block 7, feed the DCI with the voltage regulator 21 to corresponding inputs of the analog adder 9. Its output is a voltage varying in accordance with the counter code 1. When the voltage at the output of the analog adder 9 will exceed the input voltage Ux at the output of the comparator unit 19 appears logical "1", which "snaps" in the trigger unit 10 front signal coming from the output of the element "NOT" block 15. The signal with its inverted output code of the counter 1 is stored in the register 6 and is displayed on the display 13. The same signal through the NAND gate" block 15, resets the counter to 1 and set to "1" trigger block 10. The learner sets the compliance voltage input Ux and the output code, which is displayed by the LEDs of the display unit 13. To debug the circuit and test it in step mode, the output of the counter 1 through the switch 11 (S5) is connected to the display unit 13, and the output Ux of the voltage regulator 21 is connected to the input of the voltmeter 23. For automatic construction timing and execution of computer measurement the learner must record the current status of the control points in the memory unit I / o 14 (Fig not shown), which selects the clock frequency switch F, presses the ENTER button 14.8 indicator 14.11 "READY" goes out to record it, and send from whom is lutera request RQ to issue data stored in the memory unit I / o 14. The computer running the appropriate software works as a logic analyzer - multi-indicator time diagrams.

3. The learner builds a four-digit ADC successive balancing, the scheme of which is shown in figa, the state table on figb, and the result of the build - Fig. Group connections, as in the previous examples, are multibit switches that simplifies and significantly speeds up the build process schema without loss of clarity. Other links having, however, of fundamental importance for the understanding of the circuit operation are performed manually with jumpers connectors 25 - it promotes deeper learning. The scheme uses the counter to 1, the decoder 4, a block trigger 10, the register 6, the comparator unit 19; unit 7, the switch 8 and the analog adder 9, forming a digital to analogue Converter (see diagram DAC figure 9); the switches 2, 5, 11 and 12 and the block elements logical elements 15, sets of diodes 16 and capacitor 18, forming a "Node restart", and the driver signal "reset" (see FSNS figure 9). After power on count 1 and the trigger unit 10 is reset by the signal from Node restart", and from generator 22 (figa not shown) on sketchy is 1 start coming rectangular pulses. The decoder 4 converts the binary code at the output of counter 1 is unitary. The output signal "0" of the decoder 4 sets to "1" the first trigger block 10. DAC (see Fig.9) converts the code output unit triggers 10 in the corresponding code voltage U. the Comparator unit 19 compares this voltage with an input voltage Ux. If Ux>U at the output of the comparator unit 19 is set to a logical "1", which is the output signal "1" of the decoder 4 is written in the first trigger block 10. Otherwise, there is written "0". The process is repeated for the other triggers of the block 10. The signal from the last output of the decoder 4 is supplied to the first input of the NAND gate" "Node restart", the signal from the first output of which registers in the register 6 code combination received at the output of trigger 10. And the signal from the second output Node restart" resets the counter 1 and the trigger unit 10, thereby preparing the circuit for the next cycle analog-to-digital conversion. Result code corresponding to the input voltage Ux, the learner can observe on the display unit 13. To debug the circuit and test it in step mode, the output of block triggers 10 through the switch 11 (S5) is connected to the display unit 13, and the output Ux of the voltage regulator 21 (Fig) is connected to the input of the voltmeter 23 (figa not shown). The process of analog-to-digital transformation is the method of successive balancing shown in the table on figb.

1. Stand for studying electronic automation, containing two switches, the decoder binary code in position, a set of jumpers, connectors and composition field, the nests of which the unit is connected triggers, the unit logic elements, a set of diodes, the display unit and the control unit, characterized in that the composition of the stand additionally introduced the third, fourth, fifth and sixth switches, all six switches are connected to the corresponding sockets on the dial field, block I / o, counter, register, generator, switch block, the analog adder block analog Comparators, a voltage regulator, a set of resistors a set of capacitors and the voltmeter is also connected to dial field, and the output of the counter is connected to the input of the first and second switches and to the first input of the fifth switch, the output of which together with the output of the sixth switch forms a multibit data bus, which is connected to the input of the display unit and the input block data I / o input query data, output data and the output of the confirmation data which are the respective outputs of the booth, the output of the first switch is connected to the input of the decoder binary code in position, the output of the second switch is connected to the input of the register and to the input of the third switch, the output is vtorogo connected to the control input of the switch block, the output of which through the fourth switch is connected to the input of the analog adder output register connected to the first input of the sixth switch, the second input is connected to the first output unit triggers the second output of which is connected to the second input of the fifth switch.

2. The device according to claim 1, characterized in that the block I / o module contains RAM, the address counter, a trigger, a single pulse generator, the pulse generator write, frequency divider, a switch, a button "ENTER"element "And"indicator and the multiplexer, the first input which is the input of the data request block I / o and connected to the first input element And whose output is the output of the availability of data block I / o, the output of the multiplexer is connected to the increment input of the address counter, the output of which is connected to the address input of the RAM module, the output data which is output data of the block I / o, input data which is input data of the RAM module, the input recording resolution of which is connected to the input of the indicator to the second input element And the inverse of the trigger output, direct output of which is connected to the control input of the multiplexer and the input of the start of the single pulse generator, the output of which is connected to the reset input of the counter is dres, output overflow which is connected to the reset input of trigger, set input of which is connected to the output press "ENTER", the entrance of which is connected to the level of logical units, a second multiplexer input connected to the output of the switch, the input of which is connected to the respective outputs of the frequency divider, the input of which is connected to the output of the pulse generator record.

3. The device according to claim 1, characterized in that the analog adder includes an operational amplifier and N+1 resistors, the output of the operational amplifier is connected to the output of the first resistor and an output of the analog adder, the inputs of which from 1 to N are input resistors from the 2nd to (N+1)-th, the outputs of which are combined and connected to the input of the first resistor and to the first input of the operational amplifier, the second input is connected to logic level zero, and the resistor values from 1 to (N+1)-th relate as 1:2¹:2²:...2^N.

4. The device according to claim 1, characterized in that the unit comprises N switches, normally closed inputs are connected together and connected to the first input unit, the second input is connected to the joint between a normally open inputs of the switches, control inputs which form a multi-channel control input unit, and outputs multi - channel is yhod block.

5. The device according to claim 1, characterized in that the control unit contains a set of switches and buttons, inputs are combined and connected to a logic level zero, and normally closed and normally open outputs of each switch and each button is connected respectively to the inverted inputs S and R of the respective triggers, direct and inverted outputs of which are connected to the corresponding sockets on the dial field.

6. The device according to claim 1, characterized in that the generator comprises a generator of rectangular pulses, the switch and the frequency divider, the input of which is connected to the output of the generator of rectangular pulses, and each output to the corresponding input switch whose output is the output of the generator.