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Coding device, error-correction code configuration method and programme therefor Invention relates to coding means. The coding device includes an inspection matrix generating module which generates a block inspection matrix; and a coding module which generates and outputs a code word from an input message through the inspection matrix. The inspection matrix generating module includes: a degree-allocation unit which prescribes function values of the block inspection matrix through coefficients of a self-dual polynomial expression; a weight distribution determination unit which prescribes the number of components that are non-zero matrices among the components of each block of the block inspection matrix using a mask pattern; a first degree-altering unit which considers the sum of the components of the k_r-th row block of the block inspection matrix as a cyclic permutation matrix; and a second degree-altering unit which prescribes the number of row-block components that are non-zero matrices among the components of each row block excluding said k_r-th row block of the block inspection matrix. |
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Method is implemented by introduction of auxiliary units of weighing dividing capacitors with keys identical to the main unit of weighing dividing capacitors with keys, at that capacitance of the smallest capacitor in each auxiliary unit is not equal to doubled capacitance of the biggest capacitor in the main unit or the previous auxiliary unit of weighing dividing capacitors with keys, and outputs of the above auxiliary units are joined with the output of the main unit of weighing dividing capacitors with keys. |
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Device comprises an n-bit series-parallel shift register, a first OR element, first and second flip-flops, an XOR element, a first AND element, a code check element generator which includes a counter, a second OR element, flip-flops and AND logic elements. |
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System and method for multi-stream video compression using multiple encoding formats Group of inventions relates to data processing for performing video compression. The method includes encoding a plurality of video frames or portions thereof according to a first encoding format, the first encoding format being optimised for transmission to a client device over a current communication channel; transmitting said plurality and concurrently encoding same according to a second encoding format, the second encoding format having a relatively higher-quality compressed video and/or a lower compression ratio than the first encoding format; storing the first plurality of video frames encoded in the second encoding format on a storage device and providing access and playback of the first plurality of video frames encoded in the second encoding format on the client device. |
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Ultra-high-speed parallel analogue-to-digital converter with differential input Ultra-high-speed parallel analogue-to-digital converter with a differential input has N sections of identical architecture. Each of the sections includes a voltage comparator (1), the first (2) input of which is connected to a first (3) input voltage source through a first (4) reference resistor, and the second (5) input of the voltage comparator (1) is connected to a second (6) input anti-phase voltage source through a second (7) reference resistor. The first (2) input of the voltage comparator (1) is connected to a first (8) reference current source and a first (9) parasitic capacitor, the second (5) input of the voltage comparator (1) is connected to a second (10) reference current source and a second (11) parasitic capacitor. The first (3) input voltage source is connected to the base of a first (12) additional transistor, the collector of which is connected to the bus of a first (13) power supply, and the emitter is connected to the bus of a second (14) power supply through a first (15) current-stabilising two-terminal device and through a first (16) balancing capacitor to the first (2) input of the voltage comparator (1). |
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Digital-to-analogue converter includes a weight current switching unit (1), the current output (2) of which is connected to a reference resistor (3), a parasitic capacitor (4) connected to the current output (2) of the weight current switching unit (1). In order to improve operating speed, the current output (2) of the weight current switching unit (1) is connected to the input of a non-inverting voltage amplifier (5) and the current output (6) of a non-inverting current amplifier (7), wherein a frequency correction element (9) is connected between the output of the non-inverting voltage amplifier (5) and the current input (8) of the non-inverting current amplifier (7). |
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Stable current source includes in-series connected filter, transformer with an interrupting transformer connected to primary winding and a rectifying diode in secondary winding, after which a low-pass filter with a measuring shunt in an output current circuit is installed, the measurement outputs of which are connected to a voltage-to-frequency converter, the output frequency of which is supplied through a galvanic isolation element to the input of a frequency-pulse modulator controlling the switch frequency of the interrupting transistor. |
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Microcontroller adc with transient process in rc circuit Microcontroller ADC with transient process in RC circuit includes first resistor 1, second resistor 2, third resistor 3, fourth resistor 4, capacitor 5 and microcontroller 6. Resistance of resistors 2 and 3 is the same. First outputs of resistor 1 and capacitor 5 are connected to the first input of analogue comparator (AC) of microcontroller 6, first outputs of resistors 2 and 3 are connected to the second input of AC of microcontroller 6, second outputs of resistors 1, 2, 3 and capacitor 5 are connected to the first, second, third and fourth discrete outputs of microcontroller 6 respectively, first output of resistor 4 is connected to input voltage source, second output of resistor 4 is connected to second output of resistor 3. |
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Method of converting phase-shift keyed code to binary code Method includes steps of, in each cycle in the region of possible information drop, generating a time interval during which information recording is allowed in either a first pulse counter upon the onset of information drop and change thereof from a positive polarity to a negative polarity, or in a second counter if information drop changes from a negative polarity to a positive polarity, analysing the counter state at the end of the time interval and, if a logic one is recorded in the first counter and a logic zero is recorded in the second counter, generating a binary signal of positive polarity; if a logic zero is recorded in the first counter and a logic one is recorded in the second counter, generating a binary signal of negative polarity; if more than one information drop is recorded in any of the counters or there is no information drop, an information bit error signal is generated. |
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Multiplexing control and data information from user equipment in mimo transmission mode Invention relates to means of multiplexing uplink control information (UCI) with data information in a physical uplink shared channel (PUSCH) transmitted over multiple spatial layers. The method includes determination of the number of coded UCI symbols in each spatial layer when the data information is conveyed using multiple transport blocks, determination of the number of coded UCI symbols in each spatial layer when the PUSCH conveys a single transport block retransmission for a hybrid automatic repeat request (HARQ) process while the initial transport block transmission for the same HARQ process was in a PUSCH conveying multiple transport blocks and determination of the modulation scheme for the coded UCI symbols. |
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Manipulation coding method includes first establishing a number of signal constellation points and ordering said points for Gray coding; establishing a number of points in the signal constellation equal to any natural number; determining the Euclidean distance between signal constellation points and generating a vector of Euclidean distances between signal constellation points; setting a graph incidence matrix, a source and drain vertex and a plurality of vertices that are compulsory for passage; determining the initial vector of graph edge allocations using a Hungarian method of solving the allocation problem; calculating the gradient vector for the initial vector; finding the minimum in the direction of the gradient vector using a one-dimensional search method; recalculating the gradient vector at the minimum point; determining the minimum in a new direction using the one-dimensional search method; obtaining an improved approach of the allocation vector, and using the Newton-Raphson method to find the optimum routing solution in Euclidean space; generating a graph vertex bypass sequence and determining code combinations corresponding to signal constellation points in accordance with the Gray coding rule. |
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Method for noise-immune decoding of signals obtained using a low-density parity check (LDPC) code, where after decoding a LDPC code, the method includes a procedure for detecting and eliminating short unresolved cycles in a Tanner graph, and specifically determining a set of invalid bit indices; based on the obtained set, constructing a frequency of occurrence vector G; determining indices having maximum frequency of occurrence in the vector G; changing the sign therein to an opposite sign in a codeword arriving at the decoder and re-decoding the obtained word; the method being characterised by that during iterative decoding, after every ten iterations, the method includes forming an additional evidential vector of demodulator relaxed solutions, from which demodulator relaxed solutions are corrected when decoding the code and determining a set of invalid bits, from which the frequency of occurrence vector of bit indices is then constructed when detecting and eliminating short cycles in a Tanner graph. |
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Channel code demodulation method and device Group of inventions relates to computer engineering and communication and can be used in local area networks and external storage devices. The device comprises a clocking unit, a clock pulse generating unit, an error detection unit and a channel code conversion unit. |
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Analogue-to-digital converter and zero offset calibration method High-speed N-bit combined analogue-to-digital converter (ADC) includes an input parallel M-bit ADC1, an M-bit digital-to-analogue converter (DAC1), a sampling and storage device (SSD) and a pipelined (N-M+1)-bit ADC2. The M-bit ADC1 and DAC1 employ a common serial resistance divider. The SSD with double sampling, consisting of an amplifier and two samplers, generates a different signal of the input voltage of the ADC and the output voltage of the DAC. The entire analogue circuit of the ADC is differential. The ADC implements individual zero offset calibration for different samplers, for which are used two identical calibration DACs and a switch which transmits to the amplifier of the SSD a calibration signal corresponding to the sampler in storage mode, from one of the calibration DACs. During calibration, a zero differential signal with an in-phase level equal to or close to the in-phase level of the input signal is transmitted to the input of the SSD. |
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Analogue-to-digital converter and method for calibration thereof High-speed N-bit combined analogue-to-digital converter (ADC) includes an input parallel M-bit ADC1, an M-bit digital-to-analogue converter (DAC1), using a common serial resistance divider, a reference voltage Vref source, a sampling and storage device (SSD) for the difference signal of the input of the ADC and output voltage of the DAC and a pipelined (M-M+1)-bit ADC2. Calibration includes calculating and loading into DAC2 a calibration code CR and calibration codes CSi of each segment, used during normal operation as additive adjustments to the output code of the ADC, wherein a signal close to zero is generated through a unit transmission coefficient of the first stage of an ADC2 pipeline. In ADC, using SSD and ADC2 with double sampling, the DAC2 and Vref2 source are doubled and generate voltages Vref2A and Vref2B separately for each of two samplers A and B. |
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Invention relates to a communication system which employs low-density parity check (LDPC) codes. The method of encoding a channel using a LDPC code includes a step of determining the number of parity bits for puncturing. The method also includes a step of generating sets of parity bits from dividing parity bits through predefined intervals. Further, the number of sets of parity bits is determined based on the number of parity bits for puncturing. |
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Invention relates to a communication system which employs low-density parity check (LDPC) codes. The method for channel decoding using a LDPC code includes a step of demodulating a signal transmitted from a transmitter. The method also includes a step of determining positions of punctured parity bits by evaluating information on a predetermined order of sets of parity bits to be punctured and the number of sets of parity bits. Further, data are decoded using said positions of punctured parity bits. |
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Invention relates to computer engineering. A method for electronic transmission of data using one or more transmitters involves: generating a set of intermediate symbols from an ordered set of source symbols, wherein the source symbols can be regenerated from the set of intermediate symbols; designating sets of the intermediate symbols, before transmission, such that each intermediate symbol is designated as a member of one of the sets of intermediate symbols and there are at least a first set of intermediate symbols and a second set of intermediate symbols, and wherein each set of intermediate symbols is associated with its distinct encoding parameters and has as members at least one intermediate symbol; wherein said first set of intermediate symbols are designated as symbols for belief propagation decoding and the second set of intermediate symbols are designated as symbols to be inactivated for belief propagation decoding, wherein the inactivated symbols are symbols that must be found separately from belief propagation decoding; and generating a plurality of encoded symbols. |
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Analogue-to-digital converter comprises an n-bit priority encoder, a flip-flop Tg0, an AND circuit I0, an n-bit register, n flip-flops Tg1, …, Tgn with AND circuits I1, …, In, an n-bit number-to-voltage converter, a comparator circuit, a trigger bus, n analogue voltage comparators K1, …, Kn, n blocks of reference voltages Uet1, …, Uetn, an n-bit demultiplexer and a clock-pulse generator. |
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Ultra-high-speed parallel analogue-to-digital converter with differential input Disclosed is an ultra-high-speed parallel analogue-to-digital converter with a differential input, having N sections of identical architecture. Each of the sections includes a voltage comparator, the first input of which is connected to a first input voltage source through a first reference resistor, and the second input of the voltage comparator is connected to a second input anti-phase voltage source through a second reference resistor, wherein the first input of the voltage comparator is connected to a first reference current source and a first parasitic capacitor, the second input of the voltage comparator is connected to a second reference current source and a second parasitic capacitor. The first reference current source is connected in form of a first current mirror which is matched with a first power supply bus, and a first auxiliary reference current source connected to the input of the first current mirror, wherein the output of the first current mirror is the output of the first reference current source, and the second input anti-phase voltage source is connected to the input of the first current mirror through a first balancing capacitor. |
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Invention relates to a broadband wireless mobile communication system. In a wireless mobile communication system, which supports a resource block group (RBG) distribution scheme for distributed mapping of successively distributed virtual resource blocks to physical resource blocks, when zeros are added to a block interleaver used for mapping, said zeros are uniformly distributed into ND divided groups of the block interleaver, the number of which is equal to the number ND of physical resource blocks to which one virtual resource block is mapped. |
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Reduced dc gain mismatch and dc leakage in overlap transform processing Invention relates to means of generating an equalised multichannel audio signal. Inverse frequency transformation of digital media data is performed. A plurality of overlap operators are applied to results of the inverse frequency transformation. The plurality of overlap operators include at least a first overlap operator and a second overlap operator. The first overlap operator is an interior overlap operator. The second overlap operator is an edge or corner overlap operator. Each of the plurality of overlap operators is characterised by substantially equivalent DC gain. |
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Method and apparatus for selective data encryption Invention relates to data encryption and specifically to encryption of image data organised into bit streams. A layered audiovisual packet data stream (CNT'), such as one obtained by a JPEG2000 encoder (810), is received together with information (metadata) about the contribution of each packet to the reduction of image distortion. The distortion-to-rate ratio for each packet is calculated (710) and the packets are ordered (720) in descending ratio. The non-encrypted packet having the highest ratio is encrypted (730) until the target distortion is obtained. |
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Method of determining violations and correcting violated codes of bit positions in "1 from 4" coding In the encoding device of the transmitting side of a communication channel, information coming from a source in a binary code is converted to a "1 from 4" code with an active zero; the converted information is generated in form of an array of words which can be presented in the form of a table comprising P1 rows (words), each comprising P2 quaternary bits in a "1 from 4" code, wherein like quaternary bits in rows form P2 vertical columns of the array; a check code, Kr and Kv, is formed for each word and vertical column, respectively, via successive summation of bits of the word and the vertical column without carry over; in the control device, the received information is checked for conformity with the "1 from 4" code and check codes Kr and Kv; upon detecting a fault, the information is corrected and transmitted to the end device. |
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Method is carried out by using simplest functional digital to analogue converters in the main channel with the base function of the type f(x)=(1+k)x/(l+kx), and in the correction channel - a shaper of a certain voltage used as an additional component for the signal of the circuit of mismatch in current values of the angle α and the binary code N. |
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Method of expanding signal spectrum estimation bandwidth Method employs original signal processing concurrently on multiple analogue-to-digital converters (ADC) with different sampling frequencies; calculating the amplitude spectrum on each digitised sequence; further scanning the obtained spectra on a single frequency axis in the Nyquist zone in an order which is inverse to the arrangement thereof during sampling; selecting signals in the spectral range by comparing with a given threshold of amplitude spectra from each ADC; selecting spectral lines from all ADC matching on frequency position; a decision on the existence of a narrow-band signal at said frequency is made by finding lines which match on the position on the frequency axis from all ADC. |
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Method of decoding convolutional codes Method of decoding convolutional codes involves receiving radio signals, automatic gain control, demodulation, first deinterleaving, Viterbi algorithm decoding, amplitude detection, averaging, second deinterleaving, nonlinear conversion and multichannel multiplication-summation. |
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Digital angle data transmitter with sign digit Digital angle data transmitter contains an induction pickoff of a synchro resolver type, analogue-to-digital converter of the synchro resolver signals to angle digit (ADC) of a starter type with auxiliary cue signal of the rotation direction and F-counter (LSDV change pulse), a microprocessor controller, a binary bidirectional counter with a number of digits per one most significant bit more than for the ADC, a digital comparator with a number of digits equal to the ADC number of digits, a null code setter with a number of digits equal to a number of digits of the digital comparator. |
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Data transmission method, data reception method, data modulation device, data demodulation device Invention relates to methods of transmitting and receiving data and devices for modulating and demodulating data. By using signal points with a circular arrangement, obtained by rearranging part of signal points arranged in a rectangular form or cruciform, the average signal power and peak signal energy are lowered to improve nonlinear distortion characteristics. Provided is a bit mapping method, wherein the average Hamming distance in indicators of the preassigned portion from less significant bits between neighbouring signal points is low, and the Euclidean distance between signal points, in which portions of less significant bits assigned thereto match, becomes maximum. By applying an error correction code to only the portion of less significant bits, a data transmission method is provided, which is superior on bit error rate characteristics, along with moderation of the bandwidth expansion ratio. |
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Stable current source comprises a low-pass filter, a transformer with a circuit-breaker transistor connected to the primary winding, a rectifier diode, an input filter, an instrument shunt, measuring terminals of which are connected to a voltage-to-frequency converter, the output of which is connected through a galvanic decoupling element to a pulse former. |
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Methods, devices and systems for parallel video encoding and decoding Invention relates to computer engineering and specifically to video encoding. The method involves entropy decoding a first portion of a video bitstream which is associated with a video frame, thereby producing a first portion of decoded data; entropy decoding a second portion of the video bitstream which is also associated with the video frame, thereby producing a second portion of decoded data, wherein the entropy decoding of the second portion of the video bitstream is independent of the entropy decoding of the first portion of the video bitstream; and reconstructing a first portion of the video frame associated with the video bitstream using the first portion of decoded data and the second portion of decoded data. |
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Convolutional turbo coding method and device for implementing coding method Invention relates to a coding method in a wireless mobile communication system. More specifically, the present invention relates to a convolutional turbo coding (CTC) method and a device for implementing the method. The method for CTC includes steps of encoding information bits A and B using a constituent encoder, and outputting parity sequences Y1 and W1, interleaving the information bits A and B using a CTC interleaver to obtain information bits C and D, and encoding the interleaved information bits C and D using the constituent encoder to obtain parity sequences Y2 and W2, interleaving the information bits A and B, the parity sequences Y1 and W1 and the parity sequences Y2 and W2, respectively, wherein the bits in at least one of a bit group consisting of the information bits A and B, a bit group consisting of the sequences Y1 and W1, and a bit group consisting of the sequences Y2 and W2 are alternately mapped to bits of constellation points with high reliability and low reliability and puncturing the interleaving result to obtain the encoded bit sequences. |
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Device for conversion from polynomial system of residue classes to position code Device has a device start input, a group of shift registers, a synchronisation unit, a device output, three-input AND element units, a modulo 2 adder, a group of data inputs, a group of control inputs of the device, a group of orthogonal base computing units, each having memory units, a modulo adder, a register, an index-to-element converter and a multiplier. |
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Digital converter and energy conversion device Group of inventions is related to analogue-to-digital converters and can be used in energy conversion devices for power electronics. The device contains a number of data signals storage units which can select data signals with delay equal to the preset time interval, moreover these signals specify instant value change, and store these selected values with simultaneous selection of each of these signals; a deleting unit capable to delete the maximum and minimum value from values stored at the number of data signals storage units; an averaging unit capable to take an average of values which are not deleted by the deleting unit; and a converter capable of analogue-to-digital conversion of the value outputted from the averaging unit and displaying this converted value as digital information. |
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High-speed analogue-to-digital converter with differential input Unlike the existing high-speed analogue-to-digital converter with a differential input, in the present invention a first input voltage source is connected to the input of a first additional buffer amplifier, the output of which is connected to first inputs of each voltage comparator through corresponding balancing capacitors of a first group, and the second input antiphase voltage source is connected to the input of a second additional buffer amplifier, the output of which is connected to second inputs of each voltage comparator through corresponding balancing capacitors of a second group. |
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Invention contains in ACS structure resonance probes (thermal resistance probes, potentiometric pickups for actuator feedback), which require flow of permanent stable current in order to collect data from them; as a rule probes are connected in series and they require maintenance of stable current at load change and degradation of semiconductor parameters with time due to temperature change and accumulation of dose changes, and in result of such changes operation of transistors is violated and value of output current is changed. To this end the claimed device contains three identical converters of input power to output stable current; output currents of converters through cut-off unit are delivered to balancing unit, from output of the balancing unit through ballast reference resistor they come to load; outputs of the converters are also connected to control and monitoring unit by control outputs to cut-off unit and by control outputs to auxiliary power supply source; output signal comes to voltage-to-frequency converter, which control output through galvanic decoupling element to chopper transistor control module. |
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Digital-to-analogue converter, having multiple current sources and the same number of differential amplifiers based on transistors, wherein the currents of the current sources are in a ternary relationship with each other, in order to solve the set task, includes an adder, positive and negative busbars, wherein each differential amplifier forms a three-way switch, the current sources can be connected by the three-way switches to the positive or negative busbar, or can be disconnected, wherein the positive and negative busbars are connected to the adder which generates the bipolar output signal of the digital-to-analogue converter from the difference in currents of the busbars. One output of each differential amplifier is connected to the positive busbar and the second output of each differential amplifier is connected to the negative busbar. |
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Method for restoration of distorted compressed files Invention relates to means of compressing and restoring transmitted information without loss of digital data generated according to the Deflate format in information systems and electrical communication systems Owing to the introduction of the error search procedure in the current code segment and correction of decoded data distortions, based on use of context simulation of information, it becomes possible to restore data from a damaged archive region, thereby reducing loss of information when uncompressing distorted compressed files. |
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Method of transmitting and receiving information Method of transmitting and receiving information from an information source to a consumer in a digital communication system, in which each of series-arranged symbols in a message is transmitted to a one-to-one corresponding ordered set of bits with a given number and sequence of codes of said bits; in addition to values of a set of binary codes 0 and 1, other given code values are input, wherein codes from the first to the second last in the sequence of codes, corresponding to the ordered set of bits, can assume values only from the set of binary codes 0 and 1, and the last code can assume values only from the additionally input code values. Upon reception, each of the successively received bits is identified with binary codes 0, 1 and codes from the set of additionally input code values; the ordered set of bits and the corresponding sequence of codes situated between the previous received bit with a code from the set of additionally input code values and the next received bit with a code from the set of additionally input code values, including it, is identified and a message symbol is uniquely restored from said sequence of codes. |
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Information transmission and reception system System for transmitting and receiving information from an information source to a consumer in a digital communication system, in which the receiving side includes a symbol converting unit which is configured to transmit each of series-arranged symbols in a message to a one-to-one corresponding ordered set of bits with a given number and sequence of codes of said bits; inputting, in addition to values of a set of binary codes 0 and 1, other given code values, wherein codes from the first to the second last in the sequence of codes, corresponding to the ordered set of bits, can assume values only from the set of binary codes 0 and 1, and the last code can assume values only from the additionally input code values. At the receiving side, the system includes a unit for restoring symbols of the primary alphabet, which is configured to identify each of the successively received bits with binary codes 0, 1 and codes from the set of additionally input code values and identify the ordered set of bits and the corresponding sequence of codes, and uniquely restore a symbol of the message from said sequence of codes. |
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Information transmission and reception system System for transmitting and receiving information optionally from multiple information sources to consumers via digital communication, in which at the transmitting side a unit for converting a digital stream of binary bits is capable of selecting successive groups with a given number p of bits per group, identifying for each group a corresponding sequence of binary codes and one-to-one corresponding conversion of each group of bits into an ordered set of bits with a corresponding sequence of codes of said bits, inputting, in addition to values of a set of binary codes 0 and 1, other given code values, wherein codes from the first to the second last in the sequence of codes corresponding to the ordered set of bits can assume values only from the set of binary codes 0 and 1, and the last code can assume values only from M additionally input code values. At the receiving side, the system includes a unit for restoring the primary digital stream of binary bits, capable of identifying the ordered set of bits and the corresponding sequence of codes, and uniquely restoring the primary digital stream of binary bits without loss of information. |
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Method of transmitting information signals and apparatus for realising said method Information 1 consisting of five pulses is encoded in form of a series of one positive pulse, two positive pulses, each magnified N times, one negative pulse magnified N times and one positive pulse, and an information 0 consisting of five pulses is encoded in form of a series of one negative pulse, two negative pulses, each magnified N times, one positive pulse magnified N times and one negative pulse, wherein N is a positive number greater than 1; the obtained sequences are transmitted to a data transmitting medium, and the received signal is compared with a reference signal by cross-correlation at the receiving side. |
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Method and apparatus for synchronising highly compressed enhancement layer data Invention relates to data formats of multimedia applications which use hierarchical data layers. The method for encoding an audio or video signal has a base layer bit stream and an enhancement layer bit stream relating to the base layer bit stream. The base layer data and the enhancement layer data are structured into packets and packets of the base layer bit stream have corresponding packets of the enhancement layer bit stream. The method involves calculating a checksum of a packet of the base layer bit stream and a corresponding packet of the enhancement layer bit stream, as well as entropy encoding the packet of the base layer bit stream to obtain an entropy encoded, byte-aligned base layer packet starting with a synchronised word. |
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Method involves identifying a contiguous sub-sequence in the sequence of integers, wherein said sub-sequence comprises interrelated integers having the same prefix to be variable-length encoded and an independent last integer; forming a code for the contiguous sub-sequence using a code for an indication of the number of interrelated integers in said contiguous subsequence, a code of a prefix indication and the suffixes of variable length codes of the integers in the contiguous is sub-sequence. Thus, if there are n integers of which each is encoded with the same prefix then, instead of n individual prefixes for the integers, a single prefix for the contiguous subsequence is sufficient. |
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Pseudorandom code scale includes an information track made in form of gradations of a pseudorandom binary sequence with maximum period length M=2n-1, n information reading elements, arranged along the information track with angular spacing which is a multiple of the value of the quantum of the scale δ=360°/M, with the possibility of obtaining therefrom M different n-bit code combinations, k correcting reading elements, arranged along the information track with possibility of obtaining therefrom, along with n information reading elements, M different (n+k)-bit code combinations which represent a Hamming code with detection and correction of a single error, a control reading element arranged along the information track with possibility of obtaining therefrom, along with (n+k) reading elements, M different (n+k+1)-bit code combinations which represent a Hamming code with correction of a single error and detection of a double error, outputs of n information reading elements. |
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Method of processing digital file, particularly of image, video and/or audio type Disclosed is a method of processing a digital file of the image, video and/or audio type which comprises a phase for putting into line per colour layer and/or per audio channel of digital data of any audio, image and video file, a compression phase using an algorithm in which each compressed value VCn of position N is obtained by subtracting from the value Vn of same position N of the original file, a predetermined number of successive compressed values (VCn-1, VCn-2,…) calculated previously, and a restoration phase using an algorithm in which each restored value VDn of position N is obtained by adding to the value VCn,of the same position of the compressed file, a predetermined number of successive compressed values (VCn-1, VCn-2,…). |
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Circular code generator comprises series-parallel shift register, bit concurrent write inputs of which, beginning with the second, are connected to corresponding data inputs of the device, beginning with the last bit; the control input of the parallel-series mode of the register is connected to the control input of the device; clock and general reset inputs are connected to the clock input and the reset input of the device, respectively; outputs of the last and next-to-last bits of the register are connected to inputs of a first XOR element; the device further includes a NOR element and a second XOR element, the output of which is connected to the concurrent write input of the first bit of the register, and the inputs are connected to concurrent write inputs of the second and most significant bit of the register; inputs of the NOR element are connected to the clock input and the reset input of the device, and the output is the clock output of the device; the output of the first XOR element is connected to the serial write input of the register, the output of the last bit of which is the data output of the device. |
j]f(+/-) - "complementary code" structure according to arithmetic axiom of ternary number system f(+1,0,-1) when generating arguments of analogue signals in position-sign conditionally minimised structure thereof ±[mj]fусл(+/-)min (versions of russian logic)" target="_blank"> j]f(+/-) - "complementary code" structure according to arithmetic axiom of ternary number system f(+1,0,-1) when generating arguments of analogue signals in position-sign conditionally minimised structure thereof ±[mj]fусл(+/-)min (versions of russian logic)" />
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Invention can be used in monitoring and control systems in combination with arithmetic devices which perform various arithmetic procedures over arguments represented in the position-sign structure of arguments of analogue signals "Complementary code". In one version, the conversion structure is realised using logic elements AND, OR. |
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Method and apparatus for detecting nonlinear distortions caused by analogue-to-digital converter Invention is based on change in the average value of a random process as a result of nonlinear conversion thereof. After passing through a device with a monotonous nonlinear characteristic, a random process with a zero average changes its spectral composition such that a constant component which depends on the degree of manifestation of nonlinearity arises therein. Thus, the technical result is achieved by measuring and analysing the average value of a digital code at the output of the investigated analogue-to-digital converter. The apparatus for detecting nonlinear distortions has a subtractor unit, a unit for measuring the magnitude of the average value of the digital code and a decision unit. In another version, the apparatus consists of a unit for measuring the average value of the digital code and a decision unit. |
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Method of modelling video signal coding information for compressing/decompressing coding information Invention relates to a method of modelling video signal coding information for compressing coding information or decompressing compressed scalable video codec (SVC) information. The technical result is achieved by obtaining a first index variable based on context-based index offset for image block coding information on a first layer; obtaining a second index variable using context-based index offset and the first index variable; and determining the initial function value for probabilistic coding based on the second index variable, wherein the first index variable is obtained based on coding information indicating correlation between the first layer and the second layer. |
Another patent 2513749.