Cyclic code generator. RU patent 2509414.

FIELD: radio engineering, communication.

SUBSTANCE: circular code generator comprises series-parallel shift register, bit concurrent write inputs of which, beginning with the second, are connected to corresponding data inputs of the device, beginning with the last bit; the control input of the parallel-series mode of the register is connected to the control input of the device; clock and general reset inputs are connected to the clock input and the reset input of the device, respectively; outputs of the last and next-to-last bits of the register are connected to inputs of a first XOR element; the device further includes a NOR element and a second XOR element, the output of which is connected to the concurrent write input of the first bit of the register, and the inputs are connected to concurrent write inputs of the second and most significant bit of the register; inputs of the NOR element are connected to the clock input and the reset input of the device, and the output is the clock output of the device; the output of the first XOR element is connected to the serial write input of the register, the output of the last bit of which is the data output of the device.

EFFECT: generating, at the output of the device, a systematic code in which data items occupy one part of the combination and check items occupy the other part.

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The invention relates to the encoding devices of error-correcting code, which restores transmitted over the communication channel information after it distortions under the action of noise.

Known to the encoder code "3+3" (see «a Simple way of noiseproof coding», magazine «New industrial technologies». №3, p.24-28, 2009, the authors Goncharov S., Shishkin G.I.)that contains a serial-to-parallel shift register the input record the discharge of which is connected to the appropriate information input device, the first input of which is connected with the third output serial-to-parallel shift register, and also with the first entrance gate XOR and first input of the multiplexer, the second input of which is connected to the output of the element EXCLUSIVE OR, the second input of which is connected to the second output serial-to-parallel shift register, the trigger input of which is connected with the address multiplexer input and output trigger counter input of which is the entrance and exit the synchronization of encoder, a second output device is the output of the multiplexer.

The disadvantage of this device is that it outputs a sequence of elements k1, r1, k2, r2, k3 and r3, which is not systematic code, because the check r elements mixed in with information items, k. The use of nonsystematic code makes it difficult to select information items in the place of receiving the code.

The above device is closest to the technical nature of the claimed device is chosen as a prototype.

Meeting the technical task is to create a shaper of the ring code with enhanced functionality.

Achievable technical result is the formation of the output device systematic code, in which the information elements occupy the left part of the code and the test items are on the right.

To obtain a technical result, the former ring code containing a serial-to-parallel shift register, inputs parallel entry of digits which, since the second, connected to the appropriate information input devices starting from the last position, the entrance control of parallel-sequential mode register is connected with a control input device, the input synchronization and master reset is connected respectively with a clock input and reset input device, the outlets of the last bits of the register connected to the inputs of the first element EXCLUSIVE OR, what's new is that introduced additional element OR NOT and the second element is the EXCLUSIVE OR, the output of which is connected to the parallel recording the first digit, and the inputs with inputs parallel recording of the second and older bits of the register, the inputs of the element OR NOT connected with a clock input and reset input device, and the output is a clock output device, the output of the first element EXCLUSIVE OR connected to the input of the serial register entries, the output of the last category which is an informational output.

New set of essential features allows you to generate the output device systematic code, in which the information elements occupy the left part of the code and the test items - right, which allows to extend its functionality.

The figure presents the diagram the alleged driver of the ring code containing a serial-to-parallel shift register 1, inputs parallel entry of digits which, since the second, connected to the appropriate information input devices starting from last discharge control input serial-to-parallel mode register is connected with a control input device, the input synchronization and master reset is connected respectively with a clock input and reset input device, the outlets of the last bits of the register connected to the inputs of the first element EXCLUSIVE OR 2, the element OR NOT 3 and the second element is EXCLUSIVE OR 4, the output of which is connected to the parallel recording the first digit is 1, and the inputs with inputs parallel recording of the second and the senior classes of case 1, the inputs of the element OR NOT connected with a clock input and reset input device, and the output is a clock output device, the output of the first element EXCLUSIVE OR 2 is connected to the input of the serial register entries 1, the output of the last category which is an informational output.

Shaper ring code works as follows.

In the initial state-parallel shift register 1 no information available. At the input of the submitted information, code k1, k2, k3, k4. At the entrance of the total discharge in conjunction with the pulse timing filed impulse master reset.

At the entrance control of parallel/serial mode recording p/s case 1 voltage high level and on the leading edge of the pulse timing at the entrance With the information elements of a code k1, k2, k3, k4 input device discharges are recorded in the register 1, starting from last discharge. First of discharge D1 register 1 will be recorded first testing element r1=k1⊕k2, formed at the output of the first element EXCLUSIVE OR 2.

Slice synchronizing pulse is input to control parallel/serial mode recording p/s is a low voltage switches register 1 in serial mode recording information.

On the second heartbeat on the control input 1 input register information is transmitted to the output register 1, while the last exit Q5 register 1 will be formed the first bit of information packages k1. At the output of the first element EXCLUSIVE OR 2 will be formed first testing element r1=k1⊕k2, which goes to the control input of the serial register entries 1.

The third pulse timing shifts the information on one clock output case 1, while the last exit of the register and output of the device is formed the second data bits k2, the output of the first element EXCLUSIVE OR 2 will be formed the second testing element r2=k2⊕k3, which goes to the control input of the serial register entries 1 and will be recorded in the register.

The Builder of the ring code continues similarly nine cycles, ranging from 6 th to 9-th beat the last exit register 1 and output devices will be formed test elements r1, r2, r3, r4.

Tenth pulse synchronization is served together with pulse master reset register.

Manufactured prototype of the alleged driver of the ring code, tests confirmed the feasibility, practicality and efficiency.

Shaper ring code containing a serial-to-parallel shift register the input record digits which, since the second, connected to the appropriate information input devices starting from last discharge control input serial-to-parallel mode register is connected with a control input device, the input synchronization and master reset is connected respectively with a clock input and reset input device, the outlets of the last bits of the register connected to the inputs of the first element EXCLUSIVE OR, wherein additionally introduced the element OR NOT and the second element is the EXCLUSIVE OR, the output of which is connected to the parallel account of the first discharge register, and the inputs with inputs parallel recording of the second and older bits of the register, the inputs of the element OR NOT connected with a clock input and reset input device, and the output is a clock output device, the output of the first element EXCLUSIVE OR connected to the input of the serial register entries, the output of the last category which is an informational output.