Boolean function variable signal generator. RU patent 2505849.
 Device for matching exponents of m binary numbers / 2503991Device includes a unit for determining the maximum exponent, which consists of an m-input XOR element and m cells, each having AND elements, an XOR element, flip-flops, and a subtracting unit consisting of m cells, each having AND elements, XOR elements, an OR element, a NOT element and flip-flops. |
 Logic processor / 2491613Disclosed is a logic processor designed to execute eight simple symmetrical Boolean functions which depend on eight arguments - input binary signals, which can be used in digital computer systems as a code converting means, and also having nineteen computational cells (11,…,119), each having an OR element (2) and an AND element (3). |
 Phase synchronisation method and apparatus / 2491571Phase synchronisation of a narrowband signal is based on sampling thereof on zero crossing, conversion to a binary code and comparison with one of normalised biorthogonal sequences by integration and summation, wherein the binary code undergoes Boolean transformation over Galois field GF(2n), conjugate pair Boolean transformation coefficients are multiplied, subjected to unitary Boolean transformation and, using fast Walsh transformation by Pontryagin maximum method on a threshold level, the number of one of the biorthogonal sequences which coincides with the number of a narrowband filter, independent of phase, is found. The apparatus includes an amplifier with a sampler, a random-access memory unit, a unit for Boolean transformation over Galois field GF(2n), a fast Walsh transformation unit, and additionally a unitary Boolean transformation unit, the inputs of which are connected to outputs of multipliers, and the output is connected to the input of the fast Walsh transformation unit. |
 Apparatus for calculating galois field gf(2n) boolean transformation coefficients / 2475810Apparatus has a control unit, input and output switches, Log2N unit transformation stages, where N is the number of bits of the transformed sequence, each having a shift register, a Galois field GF(2n) multiply-adder, and an AND element. |
 Majority module / 2473954Device has m(A+B)-A majority decision elements (111, …, 1(a+B+1)(a+B)), wherein |
 Logical calculator / 2445679Device comprises 2n OR elements (11,…,12n) and n D-triggers (21,…,2n) and is made as capable of implementation of simple symmetrical Boolean functions depending on arguments - input binary signals. |
 Method and apparatus for multiplying binary coded decimal / 2410745Invention relates to digital computer engineering and can be used in computer processors and digital automation devices. The method involves successively performing operations of receiving multipliers in tetrads TA1 and TB3, converting multiplier codes from code 8, 4, 2, 1 to decimal numbers 8, 6, 4, 2, 1, multiplying even decimal numbers of tetrads TA1 and TA3 of one decimal place using a multiplication matrix, adding partial values of the product between TC2 and the number of unit digits and multiplication tens digits, adding the number TC2 to the decimal numbers TB3, TA2 using an addition matrix. The apparatus which realises said method has in each decimal place AND elements, OR elements, digital inverters, three four-bit flip-flop registers A, B, C, one-bit three-input adder, a multiplication matrix, an addition matrix, six control inputs. |
 Majority module / 2300137Majority module contains three groups of majority elements, having three inputs each. In each group, output of previous majority element is connected to second input of next majority element, while first and second groups contain m-1 majority elements each, where m=0,5(n+1), n≠1 is any odd positive integer. Introduced to majority module are 2AND elements, which are grouped in N groups so that i group contains m-1 2AND elements. In i group output of previous element 2AND is connected to first input of next element 2AND, outputs of (m-1) majority elements of first, second groups and outputs of (m-1) elements of 2AND first - N groups are connected respectively to second, third inputs of the first and to third inputs of the second - (N+1) majority elements of third group. First inputs of all majority elements of third group are combined, constituting second calibrating input of majority module, output and first calibrating input of which are formed respectively by output (N+1) of majority element of third group and combined first inputs of all majority elements of first and second groups, while . |
 Method for integrating control signal for astatic systems for controlling aircrafts and device for realization of said method / 2275675Method for integrating control signal for astatic systems for controlling aircrafts includes setting control signal for integration, integrating current integration signal and integrated signal is scaled, scaled signal is amplified, amplified signal is inverted, threshold signal ε≥0 is set, setting control signal is multiplied with scaled signal, multiplication signal is compared to threshold signal, check connection signal is formed, equal to inverse signal during excess of multiplication signal over threshold signal, current integration signal is formed, equal to total of setting signal and check connection signal, and scaled integrated signal is limited. Device for realization of method contains integration signal set-point device, adder, integrating link, scaling amplifier, signal limiter, inverting amplifier, controlled key, multiplication block, relay element, threshold signal set-point device. |
 Logical calculator / 2260837Device has five OR elements, five AND elements, register, six closing and six opening keys. |
 High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states. |
 Logical converter / 2248034Device has eleven majority elements, four information inputs, two adjustment inputs. |
 Symmetric module / 2248035Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered And element is connected to first input of i-numbered OR element, connected by second input to data input of i-numbered D-trigger, setting input and clock input of which are connected respectively to first and second control inputs of module, connected by i-numbered information input to first input of i-numbered And element, second input of which is connected to non-inverse output of i-numbered D-trigger, output of each previous OR element is connected to second input of following OR element, and second input of first and output of n-numbered OR elements are connected respectively to zero potential bus and module output. |
 Logical calculator / 2248036Device has 2n AND elements, n OR elements, n D-triggers. |
 Logic module / 2249844Logic module has And element, first, second majority elements, OR element, three data inputs and two adjustment inputs. |
 Logical processor / 2251142Device has majority elements, grouped in V+1 group in such a way, that i-numbered (I = 1, V) and V+1 numbered groups contain respectively n and V-1 majority element groups. |
 Singular signals number identifier / 2256211Identifier has twenty two cells, each of which has two inputs, two outputs, AND, XOR elements, while all cells are grouped as a matrix of four rows and seven columns in such a way, that i-numbered (i=1,4) string and j-numbered (j=1,4) column contain respectively 8-i and j cells. |
 Logic calculator / 2257608Device has n computing cells, each of which has AND element, OR element, D-trigger. |
 Logical processor / 2260205Device has closing and opening keys, register and calculating cells, each of which consists of OR element, AND element. |
 Unary signals adder / 2260836Device has n calculating cells, each of which consists of AND element and XOR element, n AND elements, n D-triggers. |
FIELD: physics.
SUBSTANCE: signal generator comprises log2N unit transformation steps, where N is the number of bits of the transformed sequence, each step comprising a shift register, AND coincidence group elements; outputs of the AND coincidence group elements of each step are connected to inputs of the shift register of the next step and a control unit, outputs of which are connected to second inputs of AND coincidence group elements of all unit transformation steps; each unit transformation step includes an XOR element, the first input of which is connected to the input of the shift register of the same step, and the second input is connected to the output of the shift register of the same step, wherein outputs of the XOR elements are connected to the first inputs of the ND coincidence group elements of the same unit transformation step.
EFFECT: enabling real-time operation.
2 dwg
The invention relates to the computer engineering and is intended for use in systems of processing of the signal at the construction of the systems of targeting, and self-guidance on underwater objects. Known generators of Boolean functions designed for processing of signals, see, for example, «schema majority logic General purpose» US Patent # 3296424, 1967, Bulletin of inventions January №1, cl. USA 235-152, logic solver G06F 7/57 2324219 on 12.12.2006.
A.S. 1084782, 1990, G06F 7/00 device for calculation of systems of Boolean functions.
A.S. The USSR №1032451, 1980, the unit for the calculation of symmetric Boolean functions, as well as signal generators, changing to orthogonal functions, Rademacher-Walsh (inventor's certificate №221757 published 17.07.1968), as well as generators of orthogonal functions.
A.S. USSR # 92783 MCI G06S 7/26, G06F 1/00, A.S. USSR №131092 MCI 2 G06S 7/26, A.S. USSR №170298 MCI 3 G06S 7/22, the generator binary orthogonal sequences «Electronique» №17, 1967
The closest to the technical nature of the present invention is a device for calculating the coefficients of transformation » (US Patent # 3742201, cl. G01F 7/38, 26.06.1973, U.S. patent no 3792355, cl. H04J 3/18, 12.02.1974).
The named device containing N-speed transmission unit conversion series. Each step is a single conversion includes blocks of points of convergence «And»the element of delay and the adder-calculator. The disadvantage of the prototype of the device is its complexity, the inability to function with logical functions, as well as to carry out conversion in real time. U.S. patents contain log 2 N stages of a single transformation, where N is the number of digits transformed sequence. Each degree contains first the shift register the input and output of which is connected to the input of the adder calculator, the first input of which is connected to the first inputs of the elements of the group matches, «And», and the second is connected with the second inputs of the elements of the group matches, «And» through the second shift register, the outputs of the elements of the group matches And each stage are connected to the inputs of the shift register subsequent stage, and the control unit, the outputs of which are connected with the second inputs of elements of a group «And» matches all stages of a single transformation. The disadvantage of this device is that it cannot work in real time, since the first conversion factor output device appears after N-oe value of a discrete signal arrives at the input of the device. Over the next N cycles, i.e. from N to 2N quantum output is a N conversion factors from the sequence composed of the first, i.e. from 1 to N values of the input signal. Over the next N cycles, i.e. to 2N 3N quantum of output devices appears N conversion factors from the sequence composed of the following N values of the input signal, i.e., N+1 no 2N etc.
The purpose of the invention is extended field of application, which consists in the operation of the device in real time, as well as with logical Boolean functions.
The purpose of the invention is achieved by the fact that it introduced a logical adder, or scheme , the output of which each stage unit conversion connected with other inputs of the elements of the group matches «And». Figure 1 presents a diagram of the device figure 2 - a sequence of calculations.
The device contains a shift register 1, a logical adder in the form of a scheme , functioning according to the following rule:
Table 1 e X 1 X 2X 1 - register entry 1 X 2 - output register 1 f output adder or scheme . group of items matching «And» - 3 and the control unit - 4.
0 0 0 1 0 1 1 1 0 0 1 1The device works as follows. Registers shift 1 in all stages of the unit conversion delay discrete signal on the same number of cycles, namely N/2. Clocked into the shift register 1 first stage of transformation is equal to the repetition frequency of the input signal and clocked shift registers 1 in each subsequent stage conversion in 2 times more, than in previous. This allows you to obtain the coefficients of conversion of sequences obtained after each new value of the input signal, i.e., composed of input values from 1 to N, 2 N+1, 3 N+2, etc. Consider the work of the device on the example of N=8. In this case, the registers 1 shift at any stage of transformation length-2. With the frequency of the heartbeat in the register of 1 shift of the first stage of the transformation of values of a discrete signal consistently fed to the input of first stage of transformation. Logical adder 2 produces the summation or does not produce the summation of the values of the signal from the output of the shift register 1 and login stages of transformation. Are summed up the first and the fifth, second, and sixth etc. values of the signal in the degree of conversion. Block elements match «And» - 3 works with a frequency of 2 times more than the clock speed in the register of 1 shift, and displays the input to the next stage of converting a sequence of either the amount or the sequence of entering the logical adder 2.
Thus in 2 stages of a single converting number from the output of the block elements «And» the first stage of the transformation comes with a frequency doubling in the frequency of following values of the input signal, level 2 unit conversion, as each subsequent works similarly to the first, but only with a frequency twice larger than the previous one. The output of a 3-unit conversion frequency, 8 times greater repetition frequency of the input signal, receive factors for converting a sequence listing in the form of Boolean functions in algebra , consisting of input values from 1 to N, 2 N-1, 3 to N+2, and so the control Unit performs the control and synchronization.
The proposed device to each new value of the input signal calculates the coefficient Boolean transformations of sequences consisting of N previous values of the signal, which allows to use it in real-time systems, and uniformity of delays in the schemes of unit conversion enables the use of the identical stages of a single transformation.
In matrix form these changes after the first stage presented in the form of the following sequences:
After 2 stages:
After 3 stages:
As a result, after a 3-on lines appeared sequence in the form of Boolean functions in algebra : 1, X 1 X 2 X 1 X 2 , X 3 , X 1 X 3 , X 2, X 3 , X 1 , x 2 X 3 ;
This transformation has a remarkable property.
The resulting Boolean matrix A coincides with A -1 , i.e.
AND·-7 =E,
Where E is the identity matrix.
Which implies that if the input file sequence in the form of - form the basis :
at the output we get the values of Boolean functions in the algebra of polynomials .
Such conversions are widely used in systems of information processing in the problems of classification and recognition of objects. The proposed device provides these transformations in real time by simple means.
Currently laboratory studies generator of Boolean functions on a computer, and the presentation of the equipment of information transmission for in-situ underwater researches on the basis of the proposed generator.
The proposed device is used for carrying out the planned works on modernization of one of the developed in the Institute of appliances, which is considered by the STC dated 26.02.2009 and recommended for consideration by the official protectable result of intellectual activities of the authors.
Signal generator, the evolving Boolean functions containing a log 2 N stops single conversion, where N is the number of digits transformed sequence, each degree contains a synchronized from the control unit, the shift register, the elements of the group matches, the outputs of the elements of the group matches And each stage are connected to the inputs of the shift register subsequent stage, and the control unit, the outputs of which are connected with the second inputs of the elements of the group matches And all stages of a single conversion, characterized in that in each stage of a single transformation has introduced an element of «exclusive OR», the first input of which is connected to the input shift register the same stage, and the second input - to the output of the shift register this level, the outputs of the elements «exclusive OR» connected with the first inputs of the elements of the group a match «And» the level of a single transformation.