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Logic module |
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IPC classes for russian patent Logic module (RU 2249844):
Symmetric module / 2248035
Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered And element is connected to first input of i-numbered OR element, connected by second input to data input of i-numbered D-trigger, setting input and clock input of which are connected respectively to first and second control inputs of module, connected by i-numbered information input to first input of i-numbered And element, second input of which is connected to non-inverse output of i-numbered D-trigger, output of each previous OR element is connected to second input of following OR element, and second input of first and output of n-numbered OR elements are connected respectively to zero potential bus and module output.
Logical converter / 2248034
Device has eleven majority elements, four information inputs, two adjustment inputs.
High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751
System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states.
High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751
System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states.
Logical converter / 2248034
Device has eleven majority elements, four information inputs, two adjustment inputs.
Symmetric module / 2248035
Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered And element is connected to first input of i-numbered OR element, connected by second input to data input of i-numbered D-trigger, setting input and clock input of which are connected respectively to first and second control inputs of module, connected by i-numbered information input to first input of i-numbered And element, second input of which is connected to non-inverse output of i-numbered D-trigger, output of each previous OR element is connected to second input of following OR element, and second input of first and output of n-numbered OR elements are connected respectively to zero potential bus and module output.
Logic module / 2249844
Logic module has And element, first, second majority elements, OR element, three data inputs and two adjustment inputs.
Logical processor / 2251142
Device has majority elements, grouped in V+1 group in such a way, that i-numbered (I = 1, V) and V+1 numbered groups contain respectively n and V-1 majority element groups.
Singular signals number identifier / 2256211
Identifier has twenty two cells, each of which has two inputs, two outputs, AND, XOR elements, while all cells are grouped as a matrix of four rows and seven columns in such a way, that i-numbered (i=1,4) string and j-numbered (j=1,4) column contain respectively 8-i and j cells.
Logic calculator / 2257608
Device has n computing cells, each of which has AND element, OR element, D-trigger.
Logical processor / 2260205
Device has closing and opening keys, register and calculating cells, each of which consists of OR element, AND element.
Unary signals adder / 2260836
Device has n calculating cells, each of which consists of AND element and XOR element, n AND elements, n D-triggers.
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FIELD: computers. SUBSTANCE: logic module has And element, first, second majority elements, OR element, three data inputs and two adjustment inputs. EFFECT: broader functional capabilities. 1 dwg
The invention relates to computer technology and can be used for building automation, functional units of the control systems and other Known logical units (see, for example, Fig. 3.3 on page 39 in the book of Jakubaitis E.A. Asynchronous logic automata. Riga: zinatne, 1966), which implement a simple symmetric Boolean functiondepending on the three arguments - input binary signals x1, x2, x3∈ {0, 1}. For the reason that impede the achievement of specified following technical result when using known logic modules include limited functionality due to the fact that there is no implementation of other simple symmetric Boolean functionsand τ3=x1x2x3that depends on three arguments - input binary signals x1, x2, x3∈ {0, 1}. The closest device to the same destination to the claimed invention by the combination of features is adopted for the prototype logic module (see Fig. 18,2A on page 315 in the book Kazkas A.A. Basics of electronics. M: The High. HQ., 1988), which contains an element of "And" and implements a simple symmetric Boolean function The obstacle to achieving the Oia specified below technical result when using prototype includes limited functionality due to the fact that there is no implementation of a simple symmetric Boolean functionsand τ3=x1x2x3. The technical result of the invention is the extension of functionality by ensuring the implementation of any of the three simple symmetric Boolean functions that depend on three arguments - input binary signals. This technical result in the implementation of the invention is achieved in that in the logic module containing the element "And"the peculiarity lies in the fact that it introduced the first, second majoritarian elements and element "OR", and output first and second inputs of the element OR respectively connected with the third input of the first majority element and the first, second inputs of the element And connected the output to the third input of the second majority element, the first and second inputs which are connected respectively with the second tuning input of the logic module and the output of the first majority element connected to the first and the second inputs respectively to the first configuration and the first information input of the logic module, the second, third information input and the output of which is formed respectively a first, a second input element And The And and the output of the second majority element. The drawing shows the proposed scheme logic module. The logic module contains the element "And" 1, item OR 2, the first and second majoritarian elements 31and 32and output first and second inputs of the element 2 are connected respectively with the third input element 31and the first, second inputs of the element 1, output connected to the third input element 32the first and second inputs which are connected respectively with the second tuning input of the logic module and the output element 31connected first and second inputs respectively to the first configuration and the first information input of the logic module, the second, third information input and the output of which is formed respectively first, second inputs of the element 2 and the output element 32. The work of the proposed logic module is as follows. At its first, second, third information and the first, second tuning inputs are given correspondingly binary signals x1, x2, x3∈{0, 1} and y1,2∈{0, 1}. The signal at the output of the majority element 3i(i∈ {1, 2}) is equal to "1" ("0") only when on two or on all inputs of this element signals are equal to "1" ("0"). Therefore, if the first input element 3iis"1" ("0"), this element will perform the operation "OR" ("AND") over signals acting on its second and third inputs. Thus, operation, reproducible offered by the module is defined by the expression where the symboland · marked accordingly surgery "OR" and "And". The above data allow us to conclude that the proposed logic module has a wider compared to the prototype functionality, as it provides the implementation of any of the three simple symmetric Boolean functions τ1=x1∨ x2∨ x3that τ2=x1x2∨ x1x3∨ x2x3that τ3=x1x2x3that depends on three arguments - input binary signals. The logic module that is designed to implement any of the three simple symmetric Boolean functions that depend on three arguments - input binary signals containing element And, characterized in that it introduced the first, second majoritarian elements and element "OR", and output first and second inputs of the element OR respectively connected with the third input of the first majority element and the first, second inputs of the element And connected the output to the third input of the second the th majority element, the first and second inputs which are connected respectively with the second tuning input of the logic module and the output of the first majority element, connected to the first and second inputs respectively to the first configuration and the first information input of the logic module, the second, third information input and the output of which is formed respectively a first, a second input element "OR" and the output of the second majority element.
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