|
IPC classes for russian patent Singular signals number identifier (RU 2256211):
Another patents in same IPC classes:
 Logical processor / 2251142
Device has majority elements, grouped in V+1 group in such a way, that i-numbered (I = 1, V) and V+1 numbered groups contain respectively n and V-1 majority element groups.
 Logic module / 2249844
Logic module has And element, first, second majority elements, OR element, three data inputs and two adjustment inputs.
 Symmetric module / 2248035
Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered ![]() And element is connected to first input of i-numbered OR element, connected by second input to data input of i-numbered D-trigger, setting input and clock input of which are connected respectively to first and second control inputs of module, connected by i-numbered information input to first input of i-numbered And element, second input of which is connected to non-inverse output of i-numbered D-trigger, output of each previous OR element is connected to second input of following OR element, and second input of first and output of n-numbered OR elements are connected respectively to zero potential bus and module output.
 Logical converter / 2248034
Device has eleven majority elements, four information inputs, two adjustment inputs.
 High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751
System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states.
High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751
System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states.
Logical converter / 2248034
Device has eleven majority elements, four information inputs, two adjustment inputs.
Symmetric module / 2248035
Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered ![]() And element is connected to first input of i-numbered OR element, connected by second input to data input of i-numbered D-trigger, setting input and clock input of which are connected respectively to first and second control inputs of module, connected by i-numbered information input to first input of i-numbered And element, second input of which is connected to non-inverse output of i-numbered D-trigger, output of each previous OR element is connected to second input of following OR element, and second input of first and output of n-numbered OR elements are connected respectively to zero potential bus and module output.
Logic module / 2249844
Logic module has And element, first, second majority elements, OR element, three data inputs and two adjustment inputs.
Logical processor / 2251142
Device has majority elements, grouped in V+1 group in such a way, that i-numbered (I = 1, V) and V+1 numbered groups contain respectively n and V-1 majority element groups.
 Singular signals number identifier / 2256211
Identifier has twenty two cells, each of which has two inputs, two outputs, AND, XOR elements, while all cells are grouped as a matrix of four rows and seven columns in such a way, that i-numbered (i=1,4) string and j-numbered (j=1,4) column contain respectively 8-i and j cells.
 Logic calculator / 2257608
Device has n computing cells, each of which has AND element, OR element, D-trigger.
 Logical processor / 2260205
Device has closing and opening keys, register and calculating cells, each of which consists of OR element, AND element.
 Unary signals adder / 2260836
Device has n calculating cells, each of which consists of AND element and XOR element, n AND elements, n D-triggers.
|
FIELD: computer science.
SUBSTANCE: identifier has twenty two cells, each of which has two inputs, two outputs, AND, XOR elements, while all cells are grouped as a matrix of four rows and seven columns in such a way, that i-numbered (i=1,4) string and j-numbered (j=1,4) column contain respectively 8-i and j cells.
EFFECT: simplified construction.
2 dwg
The invention relates to computer technology and can be used for building automation, functional units of the control systems and other
Known identifiers the number of single signals (see, for example, figure 2 in the article by OLGA Muzychenko. Uniform and regular structure for the realization of symmetric functions of the algebra of logic. // Automatics and telemechanics. 1998. No. 4. S-165), which identify the number of individual signals of the input tuple (x1,... ,x8), where xq∈{0,1} (as increasing the number of individual signals in the tuple (x1,... ,x8) the outputs of the above-mentioned identifiers downward moving “mercury” of the logical units).
For the reason that impede the achievement of specified following technical result when using the known identifiers the number of individual signals is a complex structure, since these IDs are eight outputs.
The closest device to the same destination to the claimed invention by the combination of features is adopted for the prototype ID number of single signals (see RIS on str in the book Shevkoplyas BV Microprocessor structure. Engineering solutions: a Handbook. M.: Radio and communication, 1990), contains twenty-two cells, each of which contains two input, two output, e is ement “And”, and identifying number of individual signals of the input tuple (x1,... ,x8), where xq∈{0,1}.
For the reason that impede the achievement of specified following technical result when using the prototype, is a complex structure, because the prototype has eight outputs.
The technical result of the invention is to simplify the structure by reducing the number of outputs in two times.
This technical result in the implementation of the invention is achieved by the fact that the ID number of single signals, containing twenty-two cells, each of which contains two inputs, two outputs and element And connected first, second inputs and output respectively to its first, second inputs and the first output, all cells are grouped into a matrix of four rows and seven columns so that the i-th row and j-th the columns contain, respectively, 8-i and j cells in the i-th line, the second output of each previous cell and the second output of the last cell are connected respectively to a second input of the subsequent cell and the i-th output of the ID number of individual signals, and the j-th the first column of the output of each preceding cell and the first input of the first cell is connected are appropriate to estwenno to the first input of a subsequent cell in the j-th input of the ID number of individual signals, the first output of the j-th cell of the j-th the column is connected to the second input of the (j+1)-th cell (j+1)-th column, and the second input of the first cell of the first column to the eighth input of the ID number of individual signals, the peculiarity lies in the fact that each cell has introduced an element of “exclusive OR”connected first, second inputs and output respectively to its first, second inputs and a second output.
Figure 1 and 2 show, respectively, the proposed scheme ID number of single signals and the cell circuit that was used to build the specified ID.
The ID number of single signals contains twenty-two cell 111,... ,147. Each cell contains an element “And” 2, the element of the “exclusive OR” 3, the first and second inputs 41and 42the first and second outputs 51and 52and input 41, entry 42and outputs 51, 52formed, respectively, are combined first, second United inputs of the elements 2, 3 and the output element 2, the output element 3. All cells are grouped into a matrix of four rows and seven columns so that the i-th row and j-th the columns contain, respectively, 8-i and j cells in the i-th line output 52each before the leading cell and exit 5 2cell 1i7connected respectively with the input 42subsequent cell and the i-th output of the ID number of individual signals, and the j-th column 51each previous cell and input 41cell 11jconnected respectively with the input 41subsequent cell and the j-th input of the ID number of single signals, exit 51cell 1ij connected to the input 42cell 1(i+1)(j+1)and input 42cell 111- for the eighth input of the ID number of single signals.
Job offer ID number of single signals as follows. On his first,..., eighth inputs are given correspondingly signals x1,... ,x8∈{0,1). Then the signal for the i-th the output will be determined by the expression
 ,
where the characters ⊕ and & marked, respectively, the operation “EXCLUSIVE OR” and “And”; m=2i-1; xk1,... ,xkm∈{x1,... ,x8} (1≤ k1<... <km≤ 8); there are a number of non-repeating conjuncti xk1&... & xkmdefined as the number of combinations of 8 m. In particular, have Z1=x1⊕ ... ⊕ x8,
Z2=x1 & x2⊕ ... ⊕ x1& x8⊕ x2& x3⊕ ... ⊕ x2& x8⊕
⊕ x3& x4⊕ ... ⊕ x3& x8⊕ x4& x5⊕ ... ⊕ x4& x8⊕ x5& x6⊕ ... ⊕ x5& x8⊕
⊕ x6& x7⊕ x6& x8⊕ x7& x8.
Thus, we get where there is a binary code the number of individual signals in the tuple (x1,... ,x8).
The above data allow us to conclude that the proposed device provides identification of the number of individual signals of the input tuple (x1,... ,x8) and has a more simple compared to the prototype structure, as it has only four.
The ID number of single signals, containing twenty-two cells, each of which contains two inputs, two outputs and the element And connected first, second inputs and output respectively to its first, second inputs and a first output, and all the cells are grouped into a matrix of four rows and seven columns so that i-I (i=1,4) row and j-th (j=1,4) column containing respectively 8-i and j cells in the i-th (i=1,4) line, the second output of each previous cell and the second output of the latter CACI connected respectively to the second input of the subsequent cell and the i-th output of the ID number of individual signals, and in the j-th (j=1,7) column of the first output of each previous cell and the first input of the first cell are connected respectively to the first input of the subsequent cell and the j-th entry of the ID number of individual signals, the first output of the j-th cell of the j-th (j=1,3) column connected to the second input of the (j+1)-th cell (j+1)-th column, and the second input of the first cell of the first column to the eighth input of the ID number of single signals, characterized in that each cell has introduced an element Excluding OR connected first, second inputs and output respectively to its first, second inputs and a second output.
|
