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IPC classes for russian patent Logical calculator (RU 2260837):
Another patents in same IPC classes:
 Unary signals adder / 2260836
Device has n calculating cells, each of which consists of AND element and XOR element, n AND elements, n D-triggers.
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Device has closing and opening keys, register and calculating cells, each of which consists of OR element, AND element.
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Identifier has twenty two cells, each of which has two inputs, two outputs, AND, XOR elements, while all cells are grouped as a matrix of four rows and seven columns in such a way, that i-numbered (i=1,4) string and j-numbered (j=1,4) column contain respectively 8-i and j cells.
Logic calculator / 2257608
Device has n computing cells, each of which has AND element, OR element, D-trigger.
Logical processor / 2260205
Device has closing and opening keys, register and calculating cells, each of which consists of OR element, AND element.
Unary signals adder / 2260836
Device has n calculating cells, each of which consists of AND element and XOR element, n AND elements, n D-triggers.
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FIELD: computer science.
SUBSTANCE: device has five OR elements, five AND elements, register, six closing and six opening keys.
EFFECT: higher speed of operation.
2 dwg
The invention relates to computer technology and can be used for building automation, functional units of the control systems and other
Known logic solvers (see, for example, in figure 1 the description of the invention to the patent of the Russian Federation 2172980, CL G 06 G 7/25, 2001), which can be used to implement six simple symmetric Boolean functions that depend on six arguments - input binary signals x1,..., x6∈{0,1}.
For the reason that impede the achievement of specified following technical result when using known logic solvers, is the low speed, because the implementation of these functions will require ten cycles of computation.
The closest device to the same destination to the claimed invention by the combination of features is adopted for the prototype logic solver (see figure 2 in the article Savchenko YG, Hop A.V. methods consistent implementation of symmetric Boolean functions// Automatic control and computer engineering. 1974. No. 3. P.24-29), which contains the register n-1 elements And n-1 elements OR when n=6 implements six simple symmetric Boolean functions that depend on six arguments - input binary signals x1,..., x6∈{0,1}.
For the reason that impede the achievement of specified below technical the second result when using prototype is poor performance, because of the implementation of these functions will require six cycles of calculation, and the minimum duration of each beat is determined by the amount of ΔtP+5ΔtEwhere ΔtPand ΔtEthere is duration of the delay introduced respectively by the register and the parallel cascade triggered elements OR I.
The technical result of the invention is to improve performance.
This technical result in the implementation of the invention is achieved by the logic solver, which contains five elements OR five elements And the register, the first and second inputs of the r-th ( element OR is connected respectively with the first and second inputs of the r-th element And the peculiarity lies in the fact that it introduced six guard and six NC key output and input of the i-th ( ) NC key connected respectively with the output of the i-th closing key and United the i-th output of the register, the i-th output of the logic solver, connected first, second configuration and the i-th information inputs respectively to the control input of all keys input register entries and the input of the i-th closing of the key outputs of the first, second and third ends of the keys are connected to sootvetstvenno first the second inputs of the first and the first input of the second elements OR outputs connected respectively to the first input register and the second input of the fourth element, OR the first input and the output of which is connected respectively with the output of the first element And the second input register, and the outputs of the sixth, fifth and fourth ends of the keys are connected respectively with the second and first inputs of the third and the second input of the second elements And outputs connected respectively to the sixth input of the register and the first input of the fifth element And the second input and the output of which is connected respectively with the output of the third and the fifth element OR the input register connected to the third and fourth inputs respectively to the output of the fourth element And the output of the fifth element OR.
Figure 1 and figure 2 presents respectively the proposed scheme logic solver and time diagrams of signals settings.
Logic solver contains elements OR 11,..., 15elements And 21,..., 25, register 3, trailing keys 41,..., 46release keys 51,..., 56and the first and second inputs of the element 1r( ) connected respectively with the first and second inputs of the element 2rthe output and input key 5i( ) are connected according to the respectively with the release key 4 iand United the i-th output of the register 3, the i-th output of the logic solver, connected first, second configuration and the i-th information inputs respectively to the control input of all keys input register entries 3 and input 4 keyithe outputs of keys 41, 42and 43connected respectively with the first, the second inputs of the element 11and the first input element 12connected outputs respectively to the first input register 3 and the second input element 14the first input and the output of which is connected respectively with the output element 21and the second input register 3, and the outputs of keys 46, 45and 44connected respectively with the second and first inputs of the element 23and a second input element 22connected outputs, respectively, to the sixth input of the register 3 and the first input element 25second input and output of which are connected respectively with the output of the element 13and the fifth input of the register 3 is connected to third and fourth inputs, respectively, to the output element 24and the output of the element 15.
The work of the proposed logic solver is as follows. On his first,...,sixth information and the first, second tuning inputs are given correspondingly binary signals x1,..., x6∈{0,1} and y 1,2∈{0,1} (figure 2). Loading data into the register 3 is on the positive difference (from "0" to "1") signal at the input record, so the register can be hardware implemented using, for example, chip CIR. If the control input keys 4i, 5i( is there a logical "1" or a logical "0", the key 4irespectively closed or open, and the key 5irespectively open or closed. Then the signals at the outputs of the transmitter (figure 1) will be determined by recurrent expressions , ,  , , where the characters ∨ and · marked accordingly OR and and operations; there are a number of time tj(figure 2); Zi0=xi.
Duration Δt a high level signal at1and the period T of the signal y2must satisfy the conditions Δt≥2ΔtEand T≥ΔtP+2ΔtEwhere ΔtPand ΔtEthere is duration of the delay introduced respectively by the register 3 and the parallel cascade triggered elements OR I. as described in the recurrent expressions get where xk1,..., xki∈{x1,..., x6} (1≤k1<...<ki≤6); N=C6 ithere are a number of non-repeating conjuncti xk1...xkidefined as the number of combinations of 6 i. Thus, we have Zi3=τiwhere τiis the i-th ( simple symmetric Boolean function of six arguments.
The above data allow us to conclude that the proposed logic solver implements six simple symmetric Boolean functions that depend on six arguments - input binary signals, and has higher compared to the prototype performance, since it performs only three quantum computing, and the minimum duration of each beat is determined by the amount of ΔtP+2ΔtE.
Logic solver, designed for the implementation of the six simple symmetric Boolean functions that depend on six arguments - input binary signals containing five elements OR five elements "And" register, and the first and second inputs of the r-th ( element "OR" are connected respectively with the first and second inputs of the r-th element And, characterized in that it introduced six guard and six NC key output and input of the i-th ( ) rashmika the corresponding key are connected respectively with the output of the i-th closing key and United the i-th output of the register, i-th output of the logic solver, connected first, second configuration and the i-th information inputs respectively to the control input of all keys input register entries and the input of the i-th closing of the key outputs of the first, second and third ends of the keys are connected respectively to the first, second inputs of the first and the first input of the second elements OR outputs connected respectively to the first input register and the second input of the fourth element, "OR", the first input and the output of which is connected respectively with the output of the first element And the second input register, and outputs the sixth, the fifth and fourth ends of the keys are connected respectively with the second and first inputs of the third and the second input of the second elements And outputs connected respectively to the sixth input of the register and the first input of the fifth element "And", the second input and the output of which is connected respectively with the output of the third element "OR" and the fifth input register connected to third and fourth inputs respectively to the output of the fourth NAND gate and the output of the fifth element "OR".
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