Logical calculator
 Symmetric module / 2248035Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered |
 Logical converter / 2248034Device has eleven majority elements, four information inputs, two adjustment inputs. |
 High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states. |
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High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751 System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states. |
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Logical converter / 2248034 Device has eleven majority elements, four information inputs, two adjustment inputs. |
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Symmetric module / 2248035 Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered |
 Logical calculator / 2248036Device has 2n AND elements, n OR elements, n D-triggers. |
 Logic module / 2249844Logic module has And element, first, second majority elements, OR element, three data inputs and two adjustment inputs. |
 Logical processor / 2251142Device has majority elements, grouped in V+1 group in such a way, that i-numbered (I = 1, V) and V+1 numbered groups contain respectively n and V-1 majority element groups. |
 Singular signals number identifier / 2256211Identifier has twenty two cells, each of which has two inputs, two outputs, AND, XOR elements, while all cells are grouped as a matrix of four rows and seven columns in such a way, that i-numbered (i=1,4) string and j-numbered (j=1,4) column contain respectively 8-i and j cells. |
 Logic calculator / 2257608Device has n computing cells, each of which has AND element, OR element, D-trigger. |
 Logical processor / 2260205Device has closing and opening keys, register and calculating cells, each of which consists of OR element, AND element. |
 Unary signals adder / 2260836Device has n calculating cells, each of which consists of AND element and XOR element, n AND elements, n D-triggers. |
FIELD: computers.
SUBSTANCE: device has 2n AND elements, n OR elements, n D-triggers.
EFFECT: simplified construction.
2 dwg, 1 tbl
The invention relates to computer technology and can be used for building automation, functional units of the control systems and other
Known logic solvers (see, for example, is on page 144 in the book Gutnikov VS Integrated electronics in the measuring devices. HP: Energoatomizdat, 1988), which implement a simple symmetric Boolean function τ2=x1x2∨x1x3∨x2x3that depends on three arguments - input binary signals x1x2x3∈{0,1}.
For the reason that impede the achievement of specified following technical result when using known logic solvers, is limited functionality due to the fact that there is no implementation of any of the n simple symmetric Boolean functions that depend on n arguments - input binary signals x1,..., xn∈{0,1}.
The closest device to the same destination to the claimed invention by the combination of features is adopted for the prototype, logic solver (see figure 2 in the article Savchenko YG, Hop A.V. methods consistent implementation of symmetric Boolean functions// Automatic control and computer engineering. 1974. No. 3. P.24-29), which contains n-1 elements “And”n-1 is the ways “OR” implements any of the n simple symmetric Boolean functions, depend on n arguments - input binary signals x1,... ,xn∈{0,1}.
For the reason that impede the achievement of specified following technical result when using the prototype, is a complex structure, because the prototype has n outputs.
The technical result of the invention is to simplify the structure by reducing the number of outputs n times while maintaining the functionality of the prototype.
This technical result in the implementation of the invention is achieved in that in a logical computer containing n-1 elements “And” n-1 elements “OR”peculiarity lies in the fact that it introduced n+1 elements “And”, n D-flip-flops and control “OR”, and the output of the i-thelement And connected to a second input of the i-th element of “OR” and the first entry (n+i)-th element And connected to the second input and output respectively to the first input of the i-th element of “OR” and the input data of the i-th D-flip-flop, the input set and the clock input of which is connected respectively with the first and second control inputs of the logic solver, connected to the i-th information input to the second input of the i-th element And the first input of which is connected to reinvestiruet output of the i-th D-flip-flop, the output of each previous element OR is connected to the first the course of the next item “OR”, and the first input and first output of the n-th elements “OR” are connected respectively to the bus zero potential and the output of the logic solver.
Figure 1 and figure 2 presents respectively the proposed scheme logic solver and time diagrams of signals settings.
Logic solver contains the elements “And” 11,... ,12nelements “OR” 21,... ,2nand D-flip-31,... ,3nand the output elementconnected with the second input element 2iand the first input element 1n+iconnected to the second input and output respectively to the first input element 2iand the data input of D-flip-flop 3ithe input set and the clock input of which is connected respectively with the first and second control inputs of the logic solver, connected to the i-th information input to the second input element 1ifirst input connected to reinvestiruet output of D-flip-flop 3ithe output of
connected to the first input element 2k+1the first input element 21and the output element 2nconnected respectively with the bus zero potential and the output of the logic solver.
The work of the proposed logic solver is as follows. On his first,... ,n-th information is installed first, second control inputs are given correspondingly binary signals x1,... , xn∈{0,1} and pulse signals y1,y2∈{0,1} (figure 2). Then the signals at the outputs of the elements 1n+iandwill be determined accordingly recurrent expressions
and
wherethere are a number of time tj(figure 2); Vi0=1; W0j=0. The period T of the signal y2must satisfy the condition T>Δ t, where Δ t=Δ t1+nΔ t2+Δ t3and Δ t1that Δ t2and Δ t3there is duration of the delay introduced respectively by the elements 1i, 2iand D-trigger 3i. Since according to (1.1) have Vi(j-1)=Vi(j-2)xiW(i-1)(j-1)=Vi(j-4)xiW(i-1)(j-3)W(i-1)(j-2)W(i-1)(j-1)=Vi0xiW(i-1)1...W(i-1)(j-1)=xiW(i-1)1...W(i-1)(j-1)then taking into account (1.2) we get
The following table summarizes the value of the expression (2) when n=4.
| W11=x1 | W21=x1∨x2 | W31=x1∨x2∨x3 | W41=x1∨x2∨x3∨x4 |
| W12=0 | W22=x1x2 | W32=x1x2∨x1x3∨x2x3 | W42=x1x2∨x1x3∨x1x4∨x2x3∨x2x4∨x3x4 |
| W13=0 | W23=0 | W33=x1x2x3 | W43=x1x2x3∨x1x2x4∨x1x3x4∨x2x3x4 |
| W14=0 | W24=0 | W34=0 | W44=x1x2x3x4 |
Thus, the proposed logic solver at its output implements function
where τ1,... ,τnthere is a simple symmetric Boolean functions (see page 126 in the book Pospelov D.A. Logical methods of analysis and synthesis schemes. M: Energy, 1974). According to (3) and figure 2 setup of the transmitter (figure 1) on the implementation of the function τjis the appropriate number m=j-1 pulse signal y2.
In seismogenic information to make a conclusion, the proposed logic solver implements any of the n simple symmetric Boolean functions that depend on n arguments - input binary signals, and has a more simple compared to the prototype structure, as it has only one output.
Logic solver to implement any of the n simple symmetric Boolean functions containing n-1 elements "And" n-1 elements OR, characterized in that it introduced n+1 elements And nD-triggers and control "OR", and the output of the i-thelement And connected to a second input of the i-th element of "OR" and the first entry (n+i)-th element And connected to the second input and output respectively to the first input of the i-th element of "OR" and the input data of the i-th D-flip-flop, the input set and the clock input of which is connected respectively with the first and second control inputs of the logic solver, connected to the i-th information input to the second input of the i-th element And the first input of which is connected to reinvestiruet output of the i-th D-flip-flop, the output of each previous element "OR" connected to the first input of the subsequent element "OR", and the first input and first output of the n-th elements "OR" are connected respectively to the bus zero potential and the output of the logic solver.